2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com)
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <ppc_asm.tmpl>
15 #include <linux/compiler.h>
16 #include <asm/processor.h>
19 DECLARE_GLOBAL_DATA_PTR;
22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6
25 /* --------------------------------------------------------------- */
27 void get_sys_info(sys_info_t *sys_info)
29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
34 #ifdef CONFIG_FSL_CORENET
35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
40 __maybe_unused u32 svr;
42 const u8 core_cplx_PLL[16] = {
43 [ 0] = 0, /* CC1 PPL / 1 */
44 [ 1] = 0, /* CC1 PPL / 2 */
45 [ 2] = 0, /* CC1 PPL / 4 */
46 [ 4] = 1, /* CC2 PPL / 1 */
47 [ 5] = 1, /* CC2 PPL / 2 */
48 [ 6] = 1, /* CC2 PPL / 4 */
49 [ 8] = 2, /* CC3 PPL / 1 */
50 [ 9] = 2, /* CC3 PPL / 2 */
51 [10] = 2, /* CC3 PPL / 4 */
52 [12] = 3, /* CC4 PPL / 1 */
53 [13] = 3, /* CC4 PPL / 2 */
54 [14] = 3, /* CC4 PPL / 4 */
57 const u8 core_cplx_pll_div[16] = {
58 [ 0] = 1, /* CC1 PPL / 1 */
59 [ 1] = 2, /* CC1 PPL / 2 */
60 [ 2] = 4, /* CC1 PPL / 4 */
61 [ 4] = 1, /* CC2 PPL / 1 */
62 [ 5] = 2, /* CC2 PPL / 2 */
63 [ 6] = 4, /* CC2 PPL / 4 */
64 [ 8] = 1, /* CC3 PPL / 1 */
65 [ 9] = 2, /* CC3 PPL / 2 */
66 [10] = 4, /* CC3 PPL / 4 */
67 [12] = 1, /* CC4 PPL / 1 */
68 [13] = 2, /* CC4 PPL / 2 */
69 [14] = 4, /* CC4 PPL / 4 */
71 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
72 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
75 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
76 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
79 sys_info->freq_systembus = sysclk;
80 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
82 unsigned int porsr1_sys_clk;
83 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
84 & FSL_DCFG_PORSR1_SYSCLK_MASK;
85 if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
86 sys_info->diff_sysclk = 1;
88 sys_info->diff_sysclk = 0;
91 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
92 * are driven by separate DDR Refclock or single source
95 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
96 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
97 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
99 * For single source clocking, both ddrclock and sysclock
100 * are driven by differential sysclock.
102 if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
103 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
106 #ifdef CONFIG_DDR_CLK_FREQ
107 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
109 sys_info->freq_ddrbus = sysclk;
112 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
113 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
114 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
115 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
116 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
117 if (mem_pll_rat == 0) {
118 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
119 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
120 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
123 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
124 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
126 * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
128 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
129 defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080)
131 switch (SVR_SOC_VER(svr)) {
136 if (SVR_MAJ(svr) >= 2)
141 if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
149 sys_info->freq_ddrbus *= mem_pll_rat;
151 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
153 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
154 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
156 freq_c_pll[i] = sysclk * ratio[i];
158 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
160 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
162 * As per CHASSIS2 architeture total 12 clusters are posible and
163 * Each cluster has up to 4 cores, sharing the same PLL selection.
164 * The cluster clock assignment is SoC defined.
166 * Total 4 clock groups are possible with 3 PLLs each.
167 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
168 * clock group B has 3, 4, 6 and so on.
170 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
171 * depends upon the SoC architeture. Same applies to other
172 * clock groups and clusters.
175 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
176 int cluster = fsl_qoriq_core_to_cluster(cpu);
177 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
179 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
180 cplx_pll += cc_group[cluster] - 1;
181 sys_info->freq_processor[cpu] =
182 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
184 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
185 defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
186 #define FM1_CLK_SEL 0xe0000000
187 #define FM1_CLK_SHIFT 29
189 #define PME_CLK_SEL 0xe0000000
190 #define PME_CLK_SHIFT 29
191 #define FM1_CLK_SEL 0x1c000000
192 #define FM1_CLK_SHIFT 26
194 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
195 rcw_tmp = in_be32(&gur->rcwsr[7]);
198 #ifdef CONFIG_SYS_DPAA_PME
199 #ifndef CONFIG_PME_PLAT_CLK_DIV
200 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
202 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
205 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
208 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
211 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
214 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
217 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
220 printf("Error: Unknown PME clock select!\n");
222 sys_info->freq_pme = sys_info->freq_systembus / 2;
227 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
232 #ifdef CONFIG_SYS_DPAA_QBMAN
233 sys_info->freq_qman = sys_info->freq_systembus / 2;
236 #ifdef CONFIG_SYS_DPAA_FMAN
237 #ifndef CONFIG_FM_PLAT_CLK_DIV
238 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
240 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
243 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
246 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
249 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
252 sys_info->freq_fman[0] = sys_info->freq_systembus;
255 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
258 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
261 printf("Error: Unknown FMan1 clock select!\n");
263 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
266 #if (CONFIG_SYS_NUM_FMAN) == 2
267 #ifdef CONFIG_SYS_FM2_CLK
268 #define FM2_CLK_SEL 0x00000038
269 #define FM2_CLK_SHIFT 3
270 rcw_tmp = in_be32(&gur->rcwsr[15]);
271 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
273 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
276 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
279 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
282 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
285 sys_info->freq_fman[1] = sys_info->freq_systembus;
288 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
291 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
294 printf("Error: Unknown FMan2 clock select!\n");
296 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
300 #endif /* CONFIG_SYS_NUM_FMAN == 2 */
302 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
306 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
308 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
309 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
311 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
313 sys_info->freq_processor[cpu] =
314 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
316 #define PME_CLK_SEL 0x80000000
317 #define FM1_CLK_SEL 0x40000000
318 #define FM2_CLK_SEL 0x20000000
319 #define HWA_ASYNC_DIV 0x04000000
320 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
322 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
324 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
327 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
329 rcw_tmp = in_be32(&gur->rcwsr[7]);
331 #ifdef CONFIG_SYS_DPAA_PME
332 if (rcw_tmp & PME_CLK_SEL) {
333 if (rcw_tmp & HWA_ASYNC_DIV)
334 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
336 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
338 sys_info->freq_pme = sys_info->freq_systembus / 2;
342 #ifdef CONFIG_SYS_DPAA_FMAN
343 if (rcw_tmp & FM1_CLK_SEL) {
344 if (rcw_tmp & HWA_ASYNC_DIV)
345 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
347 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
349 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
351 #if (CONFIG_SYS_NUM_FMAN) == 2
352 if (rcw_tmp & FM2_CLK_SEL) {
353 if (rcw_tmp & HWA_ASYNC_DIV)
354 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
356 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
358 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
363 #ifdef CONFIG_SYS_DPAA_QBMAN
364 sys_info->freq_qman = sys_info->freq_systembus / 2;
367 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
370 sys_info->freq_qe = sys_info->freq_systembus / 2;
373 #else /* CONFIG_FSL_CORENET */
374 uint plat_ratio, e500_ratio, half_freq_systembus;
377 __maybe_unused u32 qe_ratio;
380 plat_ratio = (gur->porpllsr) & 0x0000003e;
382 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
384 /* Divide before multiply to avoid integer
385 * overflow for processor speeds above 2GHz */
386 half_freq_systembus = sys_info->freq_systembus/2;
387 for (i = 0; i < cpu_numcores(); i++) {
388 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
389 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
392 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
393 sys_info->freq_ddrbus = sys_info->freq_systembus;
395 #ifdef CONFIG_DDR_CLK_FREQ
397 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
398 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
399 if (ddr_ratio != 0x7)
400 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
405 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
406 sys_info->freq_qe = sys_info->freq_systembus;
408 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
409 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
410 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
414 #ifdef CONFIG_SYS_DPAA_FMAN
415 sys_info->freq_fman[0] = sys_info->freq_systembus;
418 #endif /* CONFIG_FSL_CORENET */
420 #if defined(CONFIG_FSL_LBC)
422 #if defined(CONFIG_SYS_LBC_LCRR)
423 /* We will program LCRR to this value later */
424 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
426 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
428 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
429 #if defined(CONFIG_FSL_CORENET)
430 /* If this is corenet based SoC, bit-representation
431 * for four times the clock divider values.
434 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
435 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
437 * Yes, the entire PQ38 family use the same
438 * bit-representation for twice the clock divider values.
442 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
444 /* In case anyone cares what the unknown value is */
445 sys_info->freq_localbus = lcrr_div;
449 #if defined(CONFIG_FSL_IFC)
450 ccr = ifc_in32(&ifc_regs->ifc_ccr);
451 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
453 sys_info->freq_localbus = sys_info->freq_systembus / ccr;
458 int get_clocks (void)
461 #ifdef CONFIG_MPC8544
462 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
464 #if defined(CONFIG_CPM2)
465 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
468 /* set VCO = 4 * BRG */
469 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
470 sccr = cpm->im_cpm_intctl.sccr;
471 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
473 get_sys_info (&sys_info);
474 gd->cpu_clk = sys_info.freq_processor[0];
475 gd->bus_clk = sys_info.freq_systembus;
476 gd->mem_clk = sys_info.freq_ddrbus;
477 gd->arch.lbc_clk = sys_info.freq_localbus;
480 gd->arch.qe_clk = sys_info.freq_qe;
481 gd->arch.brg_clk = gd->arch.qe_clk / 2;
484 * The base clock for I2C depends on the actual SOC. Unfortunately,
485 * there is no pattern that can be used to determine the frequency, so
486 * the only choice is to look up the actual SOC number and use the value
487 * for that SOC. This information is taken from application note
490 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
491 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
492 defined(CONFIG_P1022)
493 gd->arch.i2c1_clk = sys_info.freq_systembus;
494 #elif defined(CONFIG_MPC8544)
496 * On the 8544, the I2C clock is the same as the SEC clock. This can be
497 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
498 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
499 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
500 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
502 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
503 gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
505 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
507 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
508 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
510 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
512 #if defined(CONFIG_FSL_ESDHC)
513 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
514 defined(CONFIG_P1014)
515 gd->arch.sdhc_clk = gd->bus_clk;
517 gd->arch.sdhc_clk = gd->bus_clk / 2;
519 #endif /* defined(CONFIG_FSL_ESDHC) */
521 #if defined(CONFIG_CPM2)
522 gd->arch.vco_out = 2*sys_info.freq_systembus;
523 gd->arch.cpm_clk = gd->arch.vco_out / 2;
524 gd->arch.scc_clk = gd->arch.vco_out / 4;
525 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
528 if(gd->cpu_clk != 0) return (0);
533 /********************************************
535 * return system bus freq in Hz
536 *********************************************/
537 ulong get_bus_freq (ulong dummy)
542 /********************************************
544 * return ddr bus freq in Hz
545 *********************************************/
546 ulong get_ddr_freq (ulong dummy)