2 * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
33 #include <timestamp.h>
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
44 #ifndef CONFIG_IDENT_STRING
45 #define CONFIG_IDENT_STRING ""
49 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
52 * Set up GOT: Global Offset Table
54 * Use r12 to access the GOT
57 GOT_ENTRY(_GOT2_TABLE_)
58 GOT_ENTRY(_FIXUP_TABLE_)
60 #ifndef CONFIG_NAND_SPL
62 GOT_ENTRY(_start_of_vectors)
63 GOT_ENTRY(_end_of_vectors)
64 GOT_ENTRY(transfer_to_handler)
69 GOT_ENTRY(__bss_start)
73 * e500 Startup -- after reset only the last 4KB of the effective
74 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
75 * section is located at THIS LAST page and basically does three
76 * things: clear some registers, set up exception tables and
77 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
78 * continue the boot procedure.
80 * Once the boot rom is mapped by TLB entries we can proceed
81 * with normal startup.
90 /* clear registers/arrays not reset by hardware */
94 mtspr L1CSR0,r0 /* invalidate d-cache */
95 mtspr L1CSR1,r0 /* invalidate i-cache */
98 mtspr DBSR,r1 /* Clear all valid bits */
101 * Enable L1 Caches early
105 #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
106 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
111 /* Enable/invalidate the I-Cache */
112 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
113 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
120 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
121 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
126 andi. r1,r3,L1CSR1_ICE@l
129 /* Enable/invalidate the D-Cache */
130 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
131 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
138 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
139 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
144 andi. r1,r3,L1CSR0_DCE@l
147 /* Setup interrupt vectors */
152 mtspr IVOR0,r1 /* 0: Critical input */
154 mtspr IVOR1,r1 /* 1: Machine check */
156 mtspr IVOR2,r1 /* 2: Data storage */
158 mtspr IVOR3,r1 /* 3: Instruction storage */
160 mtspr IVOR4,r1 /* 4: External interrupt */
162 mtspr IVOR5,r1 /* 5: Alignment */
164 mtspr IVOR6,r1 /* 6: Program check */
166 mtspr IVOR7,r1 /* 7: floating point unavailable */
168 mtspr IVOR8,r1 /* 8: System call */
169 /* 9: Auxiliary processor unavailable(unsupported) */
171 mtspr IVOR10,r1 /* 10: Decrementer */
173 mtspr IVOR11,r1 /* 11: Interval timer */
175 mtspr IVOR12,r1 /* 12: Watchdog timer */
177 mtspr IVOR13,r1 /* 13: Data TLB error */
179 mtspr IVOR14,r1 /* 14: Instruction TLB error */
181 mtspr IVOR15,r1 /* 15: Debug */
183 /* Clear and set up some registers. */
186 mtspr DEC,r0 /* prevent dec exceptions */
187 mttbl r0 /* prevent fit & wdt exceptions */
189 mtspr TSR,r1 /* clear all timer exception status */
190 mtspr TCR,r0 /* disable all */
191 mtspr ESR,r0 /* clear exception syndrome register */
192 mtspr MCSR,r0 /* machine check syndrome register */
193 mtxer r0 /* clear integer exception register */
195 #ifdef CONFIG_SYS_BOOK3E_HV
196 mtspr MAS8,r0 /* make sure MAS8 is clear */
199 /* Enable Time Base and Select Time Base Clock */
200 lis r0,HID0_EMCP@h /* Enable machine check */
201 #if defined(CONFIG_ENABLE_36BIT_PHYS)
202 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
204 #ifndef CONFIG_E500MC
205 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
209 #ifndef CONFIG_E500MC
210 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
213 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
215 /* Set MBDD bit also */
216 ori r0, r0, HID1_MBDD@l
221 /* Enable Branch Prediction */
222 #if defined(CONFIG_BTB)
223 lis r0,BUCSR_ENABLE@h
224 ori r0,r0,BUCSR_ENABLE@l
228 #if defined(CONFIG_SYS_INIT_DBCR)
231 mtspr DBSR,r1 /* Clear all status bits */
232 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
233 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
237 #ifdef CONFIG_MPC8569
238 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
239 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
241 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
242 * use address space which is more than 12bits, and it must be done in
243 * the 4K boot page. So we set this bit here.
246 /* create a temp mapping TLB0[0] for LBCR */
247 lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h
248 ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
250 lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
251 ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
253 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
254 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
256 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
257 (MAS3_SX|MAS3_SW|MAS3_SR))@h
258 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
259 (MAS3_SX|MAS3_SW|MAS3_SR))@l
269 /* Set LBCR register */
270 lis r4,CONFIG_SYS_LBCR_ADDR@h
271 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
273 lis r5,CONFIG_SYS_LBC_LBCR@h
274 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
278 /* invalidate this temp TLB */
279 lis r4,CONFIG_SYS_LBC_ADDR@h
280 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
284 #endif /* CONFIG_MPC8569 */
286 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
287 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
289 #ifndef CONFIG_SYS_RAMBOOT
290 /* create a temp mapping in AS=1 to the 4M boot window */
291 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
292 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
294 lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
295 ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
297 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
298 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
299 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
302 * create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main
303 * image has been relocated to TEXT_BASE on the second stage.
305 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
306 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
308 lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
309 ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
311 lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
312 ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
323 /* create a temp mapping in AS=1 to the stack */
324 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
325 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
327 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
328 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
330 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
331 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
333 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
334 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
335 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
336 (MAS3_SX|MAS3_SW|MAS3_SR))@h
337 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
338 (MAS3_SX|MAS3_SW|MAS3_SR))@l
339 li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
342 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
343 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
354 lis r6,MSR_IS|MSR_DS@h
355 ori r6,r6,MSR_IS|MSR_DS@l
357 ori r7,r7,switch_as@l
364 /* L1 DCache is used for initial RAM */
366 /* Allocate Initial RAM in data cache.
368 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
369 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
372 /* cache size * 1024 / (2 * L1 line size) */
373 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
379 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
382 /* Jump out the last 4K page and continue to 'normal' start */
383 #ifdef CONFIG_SYS_RAMBOOT
386 /* Calculate absolute address in FLASH and jump there */
387 /*--------------------------------------------------------------*/
388 lis r3,CONFIG_SYS_MONITOR_BASE@h
389 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
390 addi r3,r3,_start_cont - _start + _START_OFFSET
398 .long 0x27051956 /* U-BOOT Magic Number */
399 .globl version_string
401 .ascii U_BOOT_VERSION
402 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
403 .ascii CONFIG_IDENT_STRING, "\0"
408 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
409 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
410 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
414 stwu r0,-4(r1) /* Terminate call chain */
416 stwu r1,-8(r1) /* Save back chain and move SP */
417 lis r0,RESET_VECTOR@h /* Address of reset vector */
418 ori r0,r0,RESET_VECTOR@l
419 stwu r1,-8(r1) /* Save back chain and move SP */
420 stw r0,+12(r1) /* Save return addr (underflow vect) */
425 /* switch back to AS = 0 */
426 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
427 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
435 /* NOTREACHED - board_init_f() does not return */
437 #ifndef CONFIG_NAND_SPL
438 . = EXC_OFF_SYS_RESET
439 .globl _start_of_vectors
442 /* Critical input. */
443 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
446 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
448 /* Data Storage exception. */
449 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
451 /* Instruction Storage exception. */
452 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
454 /* External Interrupt exception. */
455 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
457 /* Alignment exception. */
460 EXCEPTION_PROLOG(SRR0, SRR1)
465 addi r3,r1,STACK_FRAME_OVERHEAD
466 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
468 /* Program check exception */
471 EXCEPTION_PROLOG(SRR0, SRR1)
472 addi r3,r1,STACK_FRAME_OVERHEAD
473 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
476 /* No FPU on MPC85xx. This exception is not supposed to happen.
478 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
482 * r0 - SYSCALL number
486 addis r11,r0,0 /* get functions table addr */
487 ori r11,r11,0 /* Note: this code is patched in trap_init */
488 addis r12,r0,0 /* get number of functions */
494 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
498 li r20,0xd00-4 /* Get stack pointer */
500 subi r12,r12,12 /* Adjust stack pointer */
501 li r0,0xc00+_end_back-SystemCall
502 cmplw 0,r0,r12 /* Check stack overflow */
513 li r12,0xc00+_back-SystemCall
521 mfmsr r11 /* Disable interrupts */
525 SYNC /* Some chip revs need this... */
529 li r12,0xd00-4 /* restore regs */
539 addi r12,r12,12 /* Adjust stack pointer */
547 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
548 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
549 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
551 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
552 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
554 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
556 .globl _end_of_vectors
560 . = . + (0x100 - ( . & 0xff )) /* align for debug */
563 * This code finishes saving the registers to the exception frame
564 * and jumps to the appropriate handler for the exception.
565 * Register r21 is pointer into trap frame, r1 has new stack pointer.
567 .globl transfer_to_handler
579 andi. r24,r23,0x3f00 /* get vector offset */
583 mtspr SPRG2,r22 /* r1 is now kernel sp */
585 lwz r24,0(r23) /* virtual address of handler */
586 lwz r23,4(r23) /* where to go when done */
591 rfi /* jump to handler, enable MMU */
594 mfmsr r28 /* Disable interrupts */
598 SYNC /* Some chip revs need this... */
613 lwz r2,_NIP(r1) /* Restore environment */
624 mfmsr r28 /* Disable interrupts */
628 SYNC /* Some chip revs need this... */
643 lwz r2,_NIP(r1) /* Restore environment */
654 mfmsr r28 /* Disable interrupts */
658 SYNC /* Some chip revs need this... */
673 lwz r2,_NIP(r1) /* Restore environment */
685 .globl invalidate_icache
688 ori r0,r0,L1CSR1_ICFI
693 blr /* entire I cache */
695 .globl invalidate_dcache
698 ori r0,r0,L1CSR0_DCFI
718 .globl icache_disable
731 andi. r3,r3,L1CSR1_ICE
749 .globl dcache_disable
762 andi. r3,r3,L1CSR0_DCE
785 /*------------------------------------------------------------------------------- */
787 /* Description: Input 8 bits */
788 /*------------------------------------------------------------------------------- */
794 /*------------------------------------------------------------------------------- */
796 /* Description: Output 8 bits */
797 /*------------------------------------------------------------------------------- */
804 /*------------------------------------------------------------------------------- */
805 /* Function: out16 */
806 /* Description: Output 16 bits */
807 /*------------------------------------------------------------------------------- */
814 /*------------------------------------------------------------------------------- */
815 /* Function: out16r */
816 /* Description: Byte reverse and output 16 bits */
817 /*------------------------------------------------------------------------------- */
824 /*------------------------------------------------------------------------------- */
825 /* Function: out32 */
826 /* Description: Output 32 bits */
827 /*------------------------------------------------------------------------------- */
834 /*------------------------------------------------------------------------------- */
835 /* Function: out32r */
836 /* Description: Byte reverse and output 32 bits */
837 /*------------------------------------------------------------------------------- */
844 /*------------------------------------------------------------------------------- */
846 /* Description: Input 16 bits */
847 /*------------------------------------------------------------------------------- */
853 /*------------------------------------------------------------------------------- */
854 /* Function: in16r */
855 /* Description: Input 16 bits and byte reverse */
856 /*------------------------------------------------------------------------------- */
862 /*------------------------------------------------------------------------------- */
864 /* Description: Input 32 bits */
865 /*------------------------------------------------------------------------------- */
871 /*------------------------------------------------------------------------------- */
872 /* Function: in32r */
873 /* Description: Input 32 bits and byte reverse */
874 /*------------------------------------------------------------------------------- */
879 #endif /* !CONFIG_NAND_SPL */
881 /*------------------------------------------------------------------------------*/
884 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
892 #ifdef CONFIG_ENABLE_36BIT_PHYS
896 #ifdef CONFIG_SYS_BOOK3E_HV
906 * void relocate_code (addr_sp, gd, addr_moni)
908 * This "function" does not return, instead it continues in RAM
909 * after relocating the monitor code.
913 * r5 = length in bytes
918 mr r1,r3 /* Set new stack pointer */
919 mr r9,r4 /* Save copy of Init Data pointer */
920 mr r10,r5 /* Save copy of Destination Address */
923 mr r3,r5 /* Destination Address */
924 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
925 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
926 lwz r5,GOT(__init_end)
928 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
933 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
939 /* First our own GOT */
941 /* the the one used by the C code */
951 beq cr1,4f /* In place copy is not necessary */
952 beq 7f /* Protect against 0 count */
971 * Now flush the cache: note that we must start from a cache aligned
972 * address. Otherwise we might miss one cache line.
976 beq 7f /* Always flush prefetch queue in any case */
984 sync /* Wait for all dcbst to complete on bus */
990 7: sync /* Wait for all icbi to complete on bus */
994 * Re-point the IVPR at RAM
999 * We are done. Do not return, instead branch to second part of board
1000 * initialization, now running from RAM.
1003 addi r0,r10,in_ram - _start + _START_OFFSET
1005 blr /* NEVER RETURNS! */
1010 * Relocation Function, r12 point to got2+0x8000
1012 * Adjust got2 pointers, no need to check for 0, this code
1013 * already puts a few entries in the table.
1015 li r0,__got2_entries@sectoff@l
1016 la r3,GOT(_GOT2_TABLE_)
1017 lwz r11,GOT(_GOT2_TABLE_)
1029 * Now adjust the fixups and the pointers to the fixups
1030 * in case we need to move ourselves again.
1032 li r0,__fixup_entries@sectoff@l
1033 lwz r3,GOT(_FIXUP_TABLE_)
1047 * Now clear BSS segment
1049 lwz r3,GOT(__bss_start)
1063 mr r3,r9 /* Init Data pointer */
1064 mr r4,r10 /* Destination Address */
1067 #ifndef CONFIG_NAND_SPL
1069 * Copy exception vector code to low memory
1072 * r7: source address, r8: end address, r9: target address
1076 mflr r4 /* save link register */
1078 lwz r7,GOT(_start_of_vectors)
1079 lwz r8,GOT(_end_of_vectors)
1081 li r9,0x100 /* reset vector always at 0x100 */
1084 bgelr /* return if r7>=r8 - just in case */
1094 * relocate `hdlr' and `int_return' entries
1096 li r7,.L_CriticalInput - _start + _START_OFFSET
1098 li r7,.L_MachineCheck - _start + _START_OFFSET
1100 li r7,.L_DataStorage - _start + _START_OFFSET
1102 li r7,.L_InstStorage - _start + _START_OFFSET
1104 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1106 li r7,.L_Alignment - _start + _START_OFFSET
1108 li r7,.L_ProgramCheck - _start + _START_OFFSET
1110 li r7,.L_FPUnavailable - _start + _START_OFFSET
1112 li r7,.L_Decrementer - _start + _START_OFFSET
1114 li r7,.L_IntervalTimer - _start + _START_OFFSET
1115 li r8,_end_of_vectors - _start + _START_OFFSET
1118 addi r7,r7,0x100 /* next exception vector */
1125 mtlr r4 /* restore link register */
1128 .globl unlock_ram_in_cache
1129 unlock_ram_in_cache:
1130 /* invalidate the INIT_RAM section */
1131 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1132 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1135 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1138 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1142 /* Invalidate the TLB entries for the cache */
1143 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1144 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1157 mfspr r3,SPRN_L1CFG0
1159 rlwinm r5,r3,9,3 /* Extract cache block size */
1160 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1161 * are currently defined.
1164 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1165 * log2(number of ways)
1167 slw r5,r4,r5 /* r5 = cache block size */
1169 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1170 mulli r7,r7,13 /* An 8-way cache will require 13
1175 /* save off HID0 and set DCFA */
1177 ori r9,r8,HID0_DCFA@l
1184 1: lwz r3,0(r4) /* Load... */
1192 1: dcbf 0,r4 /* ...and flush. */
1205 #include "fixed_ivor.S"
1207 #endif /* !CONFIG_NAND_SPL */