2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
31 #include <asm-offsets.h>
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
45 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
48 * Set up GOT: Global Offset Table
50 * Use r12 to access the GOT
53 GOT_ENTRY(_GOT2_TABLE_)
54 GOT_ENTRY(_FIXUP_TABLE_)
56 #ifndef CONFIG_NAND_SPL
58 GOT_ENTRY(_start_of_vectors)
59 GOT_ENTRY(_end_of_vectors)
60 GOT_ENTRY(transfer_to_handler)
64 GOT_ENTRY(__bss_end__)
65 GOT_ENTRY(__bss_start)
69 * e500 Startup -- after reset only the last 4KB of the effective
70 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
71 * section is located at THIS LAST page and basically does three
72 * things: clear some registers, set up exception tables and
73 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
74 * continue the boot procedure.
76 * Once the boot rom is mapped by TLB entries we can proceed
77 * with normal startup.
86 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
87 /* ISBC uses L2 as stack.
88 * Disable L2 cache here so that u-boot can enable it later
89 * as part of it's normal flow
92 /* Check if L2 is enabled */
95 ori r2, r2, L2CSR0_L2E@l
101 lis r2,(L2CSR0_L2FL)@h
102 ori r2, r2, (L2CSR0_L2FL)@l
109 mfspr r3, SPRN_L2CSR0
113 mfspr r3, SPRN_L2CSR0
115 ori r2, r2, L2CSR0_L2E@l
125 /* clear registers/arrays not reset by hardware */
129 mtspr L1CSR0,r0 /* invalidate d-cache */
130 mtspr L1CSR1,r0 /* invalidate i-cache */
133 mtspr DBSR,r1 /* Clear all valid bits */
136 * Enable L1 Caches early
140 #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
141 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
146 /* Enable/invalidate the I-Cache */
147 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
148 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
155 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
156 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
161 andi. r1,r3,L1CSR1_ICE@l
164 /* Enable/invalidate the D-Cache */
165 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
166 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
173 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
174 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
179 andi. r1,r3,L1CSR0_DCE@l
183 * Ne need to setup interrupt vector for NAND SPL
184 * because NAND SPL never compiles it.
186 #if !defined(CONFIG_NAND_SPL)
187 /* Setup interrupt vectors */
188 lis r1,CONFIG_SYS_MONITOR_BASE@h
191 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
192 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
194 addi r4,r3,CriticalInput - _start + _START_OFFSET
195 mtspr IVOR0,r4 /* 0: Critical input */
196 addi r4,r3,MachineCheck - _start + _START_OFFSET
197 mtspr IVOR1,r4 /* 1: Machine check */
198 addi r4,r3,DataStorage - _start + _START_OFFSET
199 mtspr IVOR2,r4 /* 2: Data storage */
200 addi r4,r3,InstStorage - _start + _START_OFFSET
201 mtspr IVOR3,r4 /* 3: Instruction storage */
202 addi r4,r3,ExtInterrupt - _start + _START_OFFSET
203 mtspr IVOR4,r4 /* 4: External interrupt */
204 addi r4,r3,Alignment - _start + _START_OFFSET
205 mtspr IVOR5,r4 /* 5: Alignment */
206 addi r4,r3,ProgramCheck - _start + _START_OFFSET
207 mtspr IVOR6,r4 /* 6: Program check */
208 addi r4,r3,FPUnavailable - _start + _START_OFFSET
209 mtspr IVOR7,r4 /* 7: floating point unavailable */
210 addi r4,r3,SystemCall - _start + _START_OFFSET
211 mtspr IVOR8,r4 /* 8: System call */
212 /* 9: Auxiliary processor unavailable(unsupported) */
213 addi r4,r3,Decrementer - _start + _START_OFFSET
214 mtspr IVOR10,r4 /* 10: Decrementer */
215 addi r4,r3,IntervalTimer - _start + _START_OFFSET
216 mtspr IVOR11,r4 /* 11: Interval timer */
217 addi r4,r3,WatchdogTimer - _start + _START_OFFSET
218 mtspr IVOR12,r4 /* 12: Watchdog timer */
219 addi r4,r3,DataTLBError - _start + _START_OFFSET
220 mtspr IVOR13,r4 /* 13: Data TLB error */
221 addi r4,r3,InstructionTLBError - _start + _START_OFFSET
222 mtspr IVOR14,r4 /* 14: Instruction TLB error */
223 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
224 mtspr IVOR15,r4 /* 15: Debug */
227 /* Clear and set up some registers. */
230 mtspr DEC,r0 /* prevent dec exceptions */
231 mttbl r0 /* prevent fit & wdt exceptions */
233 mtspr TSR,r1 /* clear all timer exception status */
234 mtspr TCR,r0 /* disable all */
235 mtspr ESR,r0 /* clear exception syndrome register */
236 mtspr MCSR,r0 /* machine check syndrome register */
237 mtxer r0 /* clear integer exception register */
239 #ifdef CONFIG_SYS_BOOK3E_HV
240 mtspr MAS8,r0 /* make sure MAS8 is clear */
243 /* Enable Time Base and Select Time Base Clock */
244 lis r0,HID0_EMCP@h /* Enable machine check */
245 #if defined(CONFIG_ENABLE_36BIT_PHYS)
246 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
248 #ifndef CONFIG_E500MC
249 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
253 #ifndef CONFIG_E500MC
254 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
257 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
259 /* Set MBDD bit also */
260 ori r0, r0, HID1_MBDD@l
265 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
271 /* Enable Branch Prediction */
272 #if defined(CONFIG_BTB)
273 lis r0,BUCSR_ENABLE@h
274 ori r0,r0,BUCSR_ENABLE@l
278 #if defined(CONFIG_SYS_INIT_DBCR)
281 mtspr DBSR,r1 /* Clear all status bits */
282 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
283 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
287 #ifdef CONFIG_MPC8569
288 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
289 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
291 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
292 * use address space which is more than 12bits, and it must be done in
293 * the 4K boot page. So we set this bit here.
296 /* create a temp mapping TLB0[0] for LBCR */
297 lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h
298 ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
300 lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
301 ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
303 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
304 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
306 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
307 (MAS3_SX|MAS3_SW|MAS3_SR))@h
308 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
309 (MAS3_SX|MAS3_SW|MAS3_SR))@l
319 /* Set LBCR register */
320 lis r4,CONFIG_SYS_LBCR_ADDR@h
321 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
323 lis r5,CONFIG_SYS_LBC_LBCR@h
324 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
328 /* invalidate this temp TLB */
329 lis r4,CONFIG_SYS_LBC_ADDR@h
330 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
334 #endif /* CONFIG_MPC8569 */
337 * Search for the TLB that covers the code we're executing, and shrink it
338 * so that it covers only this 4K page. That will ensure that any other
339 * TLB we create won't interfere with it. We assume that the TLB exists,
340 * which is why we don't check the Valid bit of MAS1.
342 * This is necessary, for example, when booting from the on-chip ROM,
343 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
344 * If we don't shrink this TLB now, then we'll accidentally delete it
345 * in "purge_old_ccsr_tlb" below.
347 bl nexti /* Find our address */
348 nexti: mflr r1 /* R1 = our PC */
350 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
353 tlbsx 0, r1 /* This must succeed */
355 /* Set the size of the TLB to 4KB */
358 andc r3, r3, r2 /* Clear the TSIZE bits */
359 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
363 * Set the base address of the TLB to our PC. We assume that
364 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
367 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
369 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
374 mtspr MAS2, r2 /* Set the EPN to our PC base address */
379 mtspr MAS3, r2 /* Set the RPN to our PC base address */
386 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
387 * location is not where we want it. This typically happens on a 36-bit
388 * system, where we want to move CCSR to near the top of 36-bit address space.
390 * To move CCSR, we create two temporary TLBs, one for the old location, and
391 * another for the new location. On CoreNet systems, we also need to create
392 * a special, temporary LAW.
394 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
395 * long-term TLBs, so we use TLB0 here.
397 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
399 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
400 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
404 lis r8, CONFIG_SYS_CCSRBAR@h
405 ori r8, r8, CONFIG_SYS_CCSRBAR@l
406 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
407 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
410 * In a multi-stage boot (e.g. NAND boot), a previous stage may have
411 * created a TLB for CCSR, which will interfere with our relocation
412 * code. Since we're going to create a new TLB for CCSR anyway,
413 * it should be safe to delete this old TLB here. We have to search
418 mtspr MAS6, r1 /* Search the current address space and PID */
423 andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */
424 beq 1f /* Skip if no TLB found */
426 rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */
435 * Create a TLB for the new location of CCSR. Register R8 is reserved
436 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
438 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
439 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
440 lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
441 ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
442 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
443 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
444 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
445 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
446 #ifdef CONFIG_ENABLE_36BIT_PHYS
447 lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
448 ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
460 * Create a TLB for the current location of CCSR. Register R9 is reserved
461 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
464 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
465 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
466 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
467 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
468 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h
469 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l
470 #ifdef CONFIG_ENABLE_36BIT_PHYS
471 li r7, 0 /* The default CCSR address is always a 32-bit number */
475 /* MAS1 is the same as above */
483 * We have a TLB for what we think is the current (old) CCSR. Let's
484 * verify that, otherwise we won't be able to move it.
485 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
486 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
489 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
490 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
491 #ifdef CONFIG_FSL_CORENET
492 lwz r1, 4(r9) /* CCSRBARL */
494 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
501 * If the value we read from CCSRBARL is not what we expect, then
502 * enter an infinite loop. This will at least allow a debugger to
503 * halt execution and examine TLBs, etc. There's no point in going
507 bne infinite_debug_loop
509 #ifdef CONFIG_FSL_CORENET
511 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
512 #define LAW_EN 0x80000000
513 #define LAW_SIZE_4K 0xb
514 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
515 #define CCSRAR_C 0x80000000 /* Commit */
519 * On CoreNet systems, we create the temporary LAW using a special LAW
520 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
522 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
523 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
524 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
525 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
526 lis r2, CCSRBAR_LAWAR@h
527 ori r2, r2, CCSRBAR_LAWAR@l
529 stw r0, 0xc00(r9) /* LAWBARH0 */
530 stw r1, 0xc04(r9) /* LAWBARL0 */
532 stw r2, 0xc08(r9) /* LAWAR0 */
535 * Read back from LAWAR to ensure the update is complete. e500mc
536 * cores also require an isync.
538 lwz r0, 0xc08(r9) /* LAWAR0 */
542 * Read the current CCSRBARH and CCSRBARL using load word instructions.
543 * Follow this with an isync instruction. This forces any outstanding
544 * accesses to configuration space to completion.
547 lwz r0, 0(r9) /* CCSRBARH */
548 lwz r0, 4(r9) /* CCSRBARL */
552 * Write the new values for CCSRBARH and CCSRBARL to their old
553 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
554 * has a new value written it loads a CCSRBARH shadow register. When
555 * the CCSRBARL is written, the CCSRBARH shadow register contents
556 * along with the CCSRBARL value are loaded into the CCSRBARH and
557 * CCSRBARL registers, respectively. Follow this with a sync
561 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
562 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
563 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
564 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
566 ori r2, r2, CCSRAR_C@l
568 stw r0, 0(r9) /* Write to CCSRBARH */
569 sync /* Make sure we write to CCSRBARH first */
570 stw r1, 4(r9) /* Write to CCSRBARL */
574 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
575 * Follow this with a sync instruction.
580 /* Delete the temporary LAW */
589 #else /* #ifdef CONFIG_FSL_CORENET */
593 * Read the current value of CCSRBAR using a load word instruction
594 * followed by an isync. This forces all accesses to configuration
601 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
602 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
603 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
605 /* Write the new value to CCSRBAR. */
606 lis r0, CCSRBAR_PHYS_RS12@h
607 ori r0, r0, CCSRBAR_PHYS_RS12@l
612 * The manual says to perform a load of an address that does not
613 * access configuration space or the on-chip SRAM using an existing TLB,
614 * but that doesn't appear to be necessary. We will do the isync,
620 * Read the contents of CCSRBAR from its new location, followed by
626 #endif /* #ifdef CONFIG_FSL_CORENET */
628 /* Delete the temporary TLBs */
630 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
631 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
633 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
634 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
642 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
643 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
644 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
645 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
651 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
653 create_init_ram_area:
654 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
655 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
657 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
658 /* create a temp mapping in AS=1 to the 4M boot window */
659 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
660 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
662 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
663 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
665 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
666 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
667 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
668 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
669 /* create a temp mapping in AS = 1 for Flash mapping
670 * created by PBL for ISBC code
672 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
673 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
675 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
676 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
678 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
679 (MAS3_SX|MAS3_SW|MAS3_SR))@h
680 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
681 (MAS3_SX|MAS3_SW|MAS3_SR))@l
684 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
685 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
687 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
688 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
690 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
691 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
693 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
694 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
705 /* create a temp mapping in AS=1 to the stack */
706 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
707 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
709 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
710 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
712 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
713 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
715 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
716 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
717 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
718 (MAS3_SX|MAS3_SW|MAS3_SR))@h
719 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
720 (MAS3_SX|MAS3_SW|MAS3_SR))@l
721 li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
724 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
725 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
736 lis r6,MSR_IS|MSR_DS@h
737 ori r6,r6,MSR_IS|MSR_DS@l
739 ori r7,r7,switch_as@l
746 /* L1 DCache is used for initial RAM */
748 /* Allocate Initial RAM in data cache.
750 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
751 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
754 /* cache size * 1024 / (2 * L1 line size) */
755 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
761 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
764 /* Jump out the last 4K page and continue to 'normal' start */
765 #ifdef CONFIG_SYS_RAMBOOT
768 /* Calculate absolute address in FLASH and jump there */
769 /*--------------------------------------------------------------*/
770 lis r3,CONFIG_SYS_MONITOR_BASE@h
771 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
772 addi r3,r3,_start_cont - _start + _START_OFFSET
780 .long 0x27051956 /* U-BOOT Magic Number */
781 .globl version_string
783 .ascii U_BOOT_VERSION_STRING, "\0"
788 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
789 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
790 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
794 stwu r0,-4(r1) /* Terminate call chain */
796 stwu r1,-8(r1) /* Save back chain and move SP */
797 lis r0,RESET_VECTOR@h /* Address of reset vector */
798 ori r0,r0,RESET_VECTOR@l
799 stwu r1,-8(r1) /* Save back chain and move SP */
800 stw r0,+12(r1) /* Save return addr (underflow vect) */
805 /* switch back to AS = 0 */
806 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
807 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
815 /* NOTREACHED - board_init_f() does not return */
817 #ifndef CONFIG_NAND_SPL
818 . = EXC_OFF_SYS_RESET
819 .globl _start_of_vectors
822 /* Critical input. */
823 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
826 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
828 /* Data Storage exception. */
829 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
831 /* Instruction Storage exception. */
832 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
834 /* External Interrupt exception. */
835 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
837 /* Alignment exception. */
840 EXCEPTION_PROLOG(SRR0, SRR1)
845 addi r3,r1,STACK_FRAME_OVERHEAD
846 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
848 /* Program check exception */
851 EXCEPTION_PROLOG(SRR0, SRR1)
852 addi r3,r1,STACK_FRAME_OVERHEAD
853 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
856 /* No FPU on MPC85xx. This exception is not supposed to happen.
858 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
862 * r0 - SYSCALL number
866 addis r11,r0,0 /* get functions table addr */
867 ori r11,r11,0 /* Note: this code is patched in trap_init */
868 addis r12,r0,0 /* get number of functions */
874 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
878 li r20,0xd00-4 /* Get stack pointer */
880 subi r12,r12,12 /* Adjust stack pointer */
881 li r0,0xc00+_end_back-SystemCall
882 cmplw 0,r0,r12 /* Check stack overflow */
893 li r12,0xc00+_back-SystemCall
901 mfmsr r11 /* Disable interrupts */
905 SYNC /* Some chip revs need this... */
909 li r12,0xd00-4 /* restore regs */
919 addi r12,r12,12 /* Adjust stack pointer */
927 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
928 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
929 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
931 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
932 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
934 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
936 .globl _end_of_vectors
940 . = . + (0x100 - ( . & 0xff )) /* align for debug */
943 * This code finishes saving the registers to the exception frame
944 * and jumps to the appropriate handler for the exception.
945 * Register r21 is pointer into trap frame, r1 has new stack pointer.
947 .globl transfer_to_handler
959 andi. r24,r23,0x3f00 /* get vector offset */
963 mtspr SPRG2,r22 /* r1 is now kernel sp */
965 lwz r24,0(r23) /* virtual address of handler */
966 lwz r23,4(r23) /* where to go when done */
971 rfi /* jump to handler, enable MMU */
974 mfmsr r28 /* Disable interrupts */
978 SYNC /* Some chip revs need this... */
993 lwz r2,_NIP(r1) /* Restore environment */
1004 mfmsr r28 /* Disable interrupts */
1008 SYNC /* Some chip revs need this... */
1023 lwz r2,_NIP(r1) /* Restore environment */
1034 mfmsr r28 /* Disable interrupts */
1038 SYNC /* Some chip revs need this... */
1053 lwz r2,_NIP(r1) /* Restore environment */
1055 mtspr SPRN_MCSRR0,r2
1056 mtspr SPRN_MCSRR1,r0
1067 .globl invalidate_icache
1070 ori r0,r0,L1CSR1_ICFI
1075 blr /* entire I cache */
1077 .globl invalidate_dcache
1080 ori r0,r0,L1CSR0_DCFI
1087 .globl icache_enable
1090 bl invalidate_icache
1100 .globl icache_disable
1104 ori r3,r3,L1CSR1_ICE
1110 .globl icache_status
1113 andi. r3,r3,L1CSR1_ICE
1116 .globl dcache_enable
1119 bl invalidate_dcache
1131 .globl dcache_disable
1135 ori r4,r4,L1CSR0_DCE
1141 .globl dcache_status
1144 andi. r3,r3,L1CSR0_DCE
1167 /*------------------------------------------------------------------------------- */
1169 /* Description: Input 8 bits */
1170 /*------------------------------------------------------------------------------- */
1176 /*------------------------------------------------------------------------------- */
1177 /* Function: out8 */
1178 /* Description: Output 8 bits */
1179 /*------------------------------------------------------------------------------- */
1186 /*------------------------------------------------------------------------------- */
1187 /* Function: out16 */
1188 /* Description: Output 16 bits */
1189 /*------------------------------------------------------------------------------- */
1196 /*------------------------------------------------------------------------------- */
1197 /* Function: out16r */
1198 /* Description: Byte reverse and output 16 bits */
1199 /*------------------------------------------------------------------------------- */
1206 /*------------------------------------------------------------------------------- */
1207 /* Function: out32 */
1208 /* Description: Output 32 bits */
1209 /*------------------------------------------------------------------------------- */
1216 /*------------------------------------------------------------------------------- */
1217 /* Function: out32r */
1218 /* Description: Byte reverse and output 32 bits */
1219 /*------------------------------------------------------------------------------- */
1226 /*------------------------------------------------------------------------------- */
1227 /* Function: in16 */
1228 /* Description: Input 16 bits */
1229 /*------------------------------------------------------------------------------- */
1235 /*------------------------------------------------------------------------------- */
1236 /* Function: in16r */
1237 /* Description: Input 16 bits and byte reverse */
1238 /*------------------------------------------------------------------------------- */
1244 /*------------------------------------------------------------------------------- */
1245 /* Function: in32 */
1246 /* Description: Input 32 bits */
1247 /*------------------------------------------------------------------------------- */
1253 /*------------------------------------------------------------------------------- */
1254 /* Function: in32r */
1255 /* Description: Input 32 bits and byte reverse */
1256 /*------------------------------------------------------------------------------- */
1261 #endif /* !CONFIG_NAND_SPL */
1263 /*------------------------------------------------------------------------------*/
1266 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1274 #ifdef CONFIG_ENABLE_36BIT_PHYS
1278 #ifdef CONFIG_SYS_BOOK3E_HV
1288 * void relocate_code (addr_sp, gd, addr_moni)
1290 * This "function" does not return, instead it continues in RAM
1291 * after relocating the monitor code.
1295 * r5 = length in bytes
1296 * r6 = cachelinesize
1298 .globl relocate_code
1300 mr r1,r3 /* Set new stack pointer */
1301 mr r9,r4 /* Save copy of Init Data pointer */
1302 mr r10,r5 /* Save copy of Destination Address */
1305 mr r3,r5 /* Destination Address */
1306 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1307 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1308 lwz r5,GOT(__init_end)
1310 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1315 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1321 /* First our own GOT */
1323 /* the the one used by the C code */
1333 beq cr1,4f /* In place copy is not necessary */
1334 beq 7f /* Protect against 0 count */
1353 * Now flush the cache: note that we must start from a cache aligned
1354 * address. Otherwise we might miss one cache line.
1358 beq 7f /* Always flush prefetch queue in any case */
1366 sync /* Wait for all dcbst to complete on bus */
1372 7: sync /* Wait for all icbi to complete on bus */
1376 * Re-point the IVPR at RAM
1381 * We are done. Do not return, instead branch to second part of board
1382 * initialization, now running from RAM.
1385 addi r0,r10,in_ram - _start + _START_OFFSET
1387 blr /* NEVER RETURNS! */
1392 * Relocation Function, r12 point to got2+0x8000
1394 * Adjust got2 pointers, no need to check for 0, this code
1395 * already puts a few entries in the table.
1397 li r0,__got2_entries@sectoff@l
1398 la r3,GOT(_GOT2_TABLE_)
1399 lwz r11,GOT(_GOT2_TABLE_)
1411 * Now adjust the fixups and the pointers to the fixups
1412 * in case we need to move ourselves again.
1414 li r0,__fixup_entries@sectoff@l
1415 lwz r3,GOT(_FIXUP_TABLE_)
1431 * Now clear BSS segment
1433 lwz r3,GOT(__bss_start)
1434 lwz r4,GOT(__bss_end__)
1447 mr r3,r9 /* Init Data pointer */
1448 mr r4,r10 /* Destination Address */
1451 #ifndef CONFIG_NAND_SPL
1453 * Copy exception vector code to low memory
1456 * r7: source address, r8: end address, r9: target address
1460 mflr r4 /* save link register */
1462 lwz r7,GOT(_start_of_vectors)
1463 lwz r8,GOT(_end_of_vectors)
1465 li r9,0x100 /* reset vector always at 0x100 */
1468 bgelr /* return if r7>=r8 - just in case */
1478 * relocate `hdlr' and `int_return' entries
1480 li r7,.L_CriticalInput - _start + _START_OFFSET
1482 li r7,.L_MachineCheck - _start + _START_OFFSET
1484 li r7,.L_DataStorage - _start + _START_OFFSET
1486 li r7,.L_InstStorage - _start + _START_OFFSET
1488 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1490 li r7,.L_Alignment - _start + _START_OFFSET
1492 li r7,.L_ProgramCheck - _start + _START_OFFSET
1494 li r7,.L_FPUnavailable - _start + _START_OFFSET
1496 li r7,.L_Decrementer - _start + _START_OFFSET
1498 li r7,.L_IntervalTimer - _start + _START_OFFSET
1499 li r8,_end_of_vectors - _start + _START_OFFSET
1502 addi r7,r7,0x100 /* next exception vector */
1506 /* Update IVORs as per relocated vector table address */
1508 mtspr IVOR0,r7 /* 0: Critical input */
1510 mtspr IVOR1,r7 /* 1: Machine check */
1512 mtspr IVOR2,r7 /* 2: Data storage */
1514 mtspr IVOR3,r7 /* 3: Instruction storage */
1516 mtspr IVOR4,r7 /* 4: External interrupt */
1518 mtspr IVOR5,r7 /* 5: Alignment */
1520 mtspr IVOR6,r7 /* 6: Program check */
1522 mtspr IVOR7,r7 /* 7: floating point unavailable */
1524 mtspr IVOR8,r7 /* 8: System call */
1525 /* 9: Auxiliary processor unavailable(unsupported) */
1527 mtspr IVOR10,r7 /* 10: Decrementer */
1529 mtspr IVOR11,r7 /* 11: Interval timer */
1531 mtspr IVOR12,r7 /* 12: Watchdog timer */
1533 mtspr IVOR13,r7 /* 13: Data TLB error */
1535 mtspr IVOR14,r7 /* 14: Instruction TLB error */
1537 mtspr IVOR15,r7 /* 15: Debug */
1542 mtlr r4 /* restore link register */
1545 .globl unlock_ram_in_cache
1546 unlock_ram_in_cache:
1547 /* invalidate the INIT_RAM section */
1548 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1549 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1552 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1555 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1559 /* Invalidate the TLB entries for the cache */
1560 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1561 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1574 mfspr r3,SPRN_L1CFG0
1576 rlwinm r5,r3,9,3 /* Extract cache block size */
1577 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1578 * are currently defined.
1581 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1582 * log2(number of ways)
1584 slw r5,r4,r5 /* r5 = cache block size */
1586 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1587 mulli r7,r7,13 /* An 8-way cache will require 13
1592 /* save off HID0 and set DCFA */
1594 ori r9,r8,HID0_DCFA@l
1601 1: lwz r3,0(r4) /* Load... */
1609 1: dcbf 0,r4 /* ...and flush. */
1622 #include "fixed_ivor.S"
1624 #endif /* !CONFIG_NAND_SPL */