2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
10 * The processor starts at 0xfffffffc and the code is first executed in the
11 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
15 #include <asm-offsets.h>
20 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
22 #include <ppc_asm.tmpl>
25 #include <asm/cache.h>
29 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
31 #if defined(CONFIG_NAND_SPL) || \
32 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
36 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
41 * Set up GOT: Global Offset Table
43 * Use r12 to access the GOT
46 GOT_ENTRY(_GOT2_TABLE_)
47 GOT_ENTRY(_FIXUP_TABLE_)
51 GOT_ENTRY(_start_of_vectors)
52 GOT_ENTRY(_end_of_vectors)
53 GOT_ENTRY(transfer_to_handler)
58 GOT_ENTRY(__bss_start)
62 * e500 Startup -- after reset only the last 4KB of the effective
63 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
64 * section is located at THIS LAST page and basically does three
65 * things: clear some registers, set up exception tables and
66 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
67 * continue the boot procedure.
69 * Once the boot rom is mapped by TLB entries we can proceed
70 * with normal startup.
78 /* Enable debug exception */
82 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
85 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
89 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
90 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
95 /* Not a supported revision affected by erratum */
99 1: li r27,1 /* Remember for later that we have the erratum */
100 /* Erratum says set bits 55:60 to 001001 */
111 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
112 /* ISBC uses L2 as stack.
113 * Disable L2 cache here so that u-boot can enable it later
114 * as part of it's normal flow
117 /* Check if L2 is enabled */
118 mfspr r3, SPRN_L2CSR0
120 ori r2, r2, L2CSR0_L2E@l
124 mfspr r3, SPRN_L2CSR0
126 lis r2,(L2CSR0_L2FL)@h
127 ori r2, r2, (L2CSR0_L2FL)@l
134 mfspr r3, SPRN_L2CSR0
138 mfspr r3, SPRN_L2CSR0
140 ori r2, r2, L2CSR0_L2E@l
150 /* clear registers/arrays not reset by hardware */
154 mtspr L1CSR0,r0 /* invalidate d-cache */
155 mtspr L1CSR1,r0 /* invalidate i-cache */
158 mtspr DBSR,r1 /* Clear all valid bits */
161 .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
162 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
163 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
165 lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
166 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
168 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
169 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
171 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
172 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
174 lis \scratch, \phy_high@h
175 ori \scratch, \scratch, \phy_high@l
183 .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
184 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
185 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
187 lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
188 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
190 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
191 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
193 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
194 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
196 lis \scratch, \phy_high@h
197 ori \scratch, \scratch, \phy_high@l
205 .macro delete_tlb1_entry esel scratch
206 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
207 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
217 .macro delete_tlb0_entry esel epn wimg scratch
218 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
219 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
223 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
224 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
232 /* Interrupt vectors do not fit in minimal SPL. */
233 #if !defined(MINIMAL_SPL)
234 /* Setup interrupt vectors */
235 lis r1,CONFIG_SYS_MONITOR_BASE@h
238 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
239 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
241 addi r4,r3,CriticalInput - _start + _START_OFFSET
242 mtspr IVOR0,r4 /* 0: Critical input */
243 addi r4,r3,MachineCheck - _start + _START_OFFSET
244 mtspr IVOR1,r4 /* 1: Machine check */
245 addi r4,r3,DataStorage - _start + _START_OFFSET
246 mtspr IVOR2,r4 /* 2: Data storage */
247 addi r4,r3,InstStorage - _start + _START_OFFSET
248 mtspr IVOR3,r4 /* 3: Instruction storage */
249 addi r4,r3,ExtInterrupt - _start + _START_OFFSET
250 mtspr IVOR4,r4 /* 4: External interrupt */
251 addi r4,r3,Alignment - _start + _START_OFFSET
252 mtspr IVOR5,r4 /* 5: Alignment */
253 addi r4,r3,ProgramCheck - _start + _START_OFFSET
254 mtspr IVOR6,r4 /* 6: Program check */
255 addi r4,r3,FPUnavailable - _start + _START_OFFSET
256 mtspr IVOR7,r4 /* 7: floating point unavailable */
257 addi r4,r3,SystemCall - _start + _START_OFFSET
258 mtspr IVOR8,r4 /* 8: System call */
259 /* 9: Auxiliary processor unavailable(unsupported) */
260 addi r4,r3,Decrementer - _start + _START_OFFSET
261 mtspr IVOR10,r4 /* 10: Decrementer */
262 addi r4,r3,IntervalTimer - _start + _START_OFFSET
263 mtspr IVOR11,r4 /* 11: Interval timer */
264 addi r4,r3,WatchdogTimer - _start + _START_OFFSET
265 mtspr IVOR12,r4 /* 12: Watchdog timer */
266 addi r4,r3,DataTLBError - _start + _START_OFFSET
267 mtspr IVOR13,r4 /* 13: Data TLB error */
268 addi r4,r3,InstructionTLBError - _start + _START_OFFSET
269 mtspr IVOR14,r4 /* 14: Instruction TLB error */
270 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
271 mtspr IVOR15,r4 /* 15: Debug */
274 /* Clear and set up some registers. */
277 mtspr DEC,r0 /* prevent dec exceptions */
278 mttbl r0 /* prevent fit & wdt exceptions */
280 mtspr TSR,r1 /* clear all timer exception status */
281 mtspr TCR,r0 /* disable all */
282 mtspr ESR,r0 /* clear exception syndrome register */
283 mtspr MCSR,r0 /* machine check syndrome register */
284 mtxer r0 /* clear integer exception register */
286 #ifdef CONFIG_SYS_BOOK3E_HV
287 mtspr MAS8,r0 /* make sure MAS8 is clear */
290 /* Enable Time Base and Select Time Base Clock */
291 lis r0,HID0_EMCP@h /* Enable machine check */
292 #if defined(CONFIG_ENABLE_36BIT_PHYS)
293 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
295 #ifndef CONFIG_E500MC
296 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
300 #ifndef CONFIG_E500MC
301 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
304 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
306 /* Set MBDD bit also */
307 ori r0, r0, HID1_MBDD@l
312 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
318 /* Enable Branch Prediction */
319 #if defined(CONFIG_BTB)
320 lis r0,BUCSR_ENABLE@h
321 ori r0,r0,BUCSR_ENABLE@l
325 #if defined(CONFIG_SYS_INIT_DBCR)
328 mtspr DBSR,r1 /* Clear all status bits */
329 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
330 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
334 #ifdef CONFIG_MPC8569
335 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
336 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
338 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
339 * use address space which is more than 12bits, and it must be done in
340 * the 4K boot page. So we set this bit here.
343 /* create a temp mapping TLB0[0] for LBCR */
344 create_tlb0_entry 0, \
345 0, BOOKE_PAGESZ_4K, \
346 CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
347 CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
350 /* Set LBCR register */
351 lis r4,CONFIG_SYS_LBCR_ADDR@h
352 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
354 lis r5,CONFIG_SYS_LBC_LBCR@h
355 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
359 /* invalidate this temp TLB */
360 lis r4,CONFIG_SYS_LBC_ADDR@h
361 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
365 #endif /* CONFIG_MPC8569 */
368 * Search for the TLB that covers the code we're executing, and shrink it
369 * so that it covers only this 4K page. That will ensure that any other
370 * TLB we create won't interfere with it. We assume that the TLB exists,
371 * which is why we don't check the Valid bit of MAS1. We also assume
374 * This is necessary, for example, when booting from the on-chip ROM,
375 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
377 bl nexti /* Find our address */
378 nexti: mflr r1 /* R1 = our PC */
380 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
383 tlbsx 0, r1 /* This must succeed */
385 mfspr r14, MAS0 /* Save ESEL for later */
386 rlwinm r14, r14, 16, 0xfff
388 /* Set the size of the TLB to 4KB */
391 andc r3, r3, r2 /* Clear the TSIZE bits */
392 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
393 oris r3, r3, MAS1_IPROT@h
397 * Set the base address of the TLB to our PC. We assume that
398 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
401 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
403 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
408 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
411 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
412 rlwinm r2, r2, 0, ~MAS2_I
416 mtspr MAS2, r2 /* Set the EPN to our PC base address */
421 mtspr MAS3, r2 /* Set the RPN to our PC base address */
428 * Clear out any other TLB entries that may exist, to avoid conflicts.
429 * Our TLB entry is in r14.
431 li r0, TLBIVAX_ALL | TLBIVAX_TLB0
435 mfspr r4, SPRN_TLB1CFG
436 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
441 rlwinm r5, r3, 16, MAS0_ESEL_MSK
443 beq 2f /* skip the entry we're executing from */
445 oris r5, r5, MAS0_TLBSEL(1)@h
456 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
458 * TLB entry for debuggging in AS1
459 * Create temporary TLB entry in AS0 to handle debug exception
460 * As on debug exception MSR is cleared i.e. Address space is changed
461 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
467 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
468 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
469 * and this window is outside of 4K boot window.
471 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
472 0, BOOKE_PAGESZ_4M, \
473 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
474 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
477 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
478 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
479 0, BOOKE_PAGESZ_1M, \
480 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
481 CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
485 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
486 * because "nexti" will resize TLB to 4K
488 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
489 0, BOOKE_PAGESZ_256K, \
490 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
491 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
497 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
498 * location is not where we want it. This typically happens on a 36-bit
499 * system, where we want to move CCSR to near the top of 36-bit address space.
501 * To move CCSR, we create two temporary TLBs, one for the old location, and
502 * another for the new location. On CoreNet systems, we also need to create
503 * a special, temporary LAW.
505 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
506 * long-term TLBs, so we use TLB0 here.
508 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
510 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
511 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
516 * Create a TLB for the new location of CCSR. Register R8 is reserved
517 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
519 lis r8, CONFIG_SYS_CCSRBAR@h
520 ori r8, r8, CONFIG_SYS_CCSRBAR@l
521 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
522 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
523 create_tlb0_entry 0, \
524 0, BOOKE_PAGESZ_4K, \
525 CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
526 CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
527 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
529 * Create a TLB for the current location of CCSR. Register R9 is reserved
530 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
533 create_tlb0_entry 1, \
534 0, BOOKE_PAGESZ_4K, \
535 CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
536 CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
537 0, r3 /* The default CCSR address is always a 32-bit number */
541 * We have a TLB for what we think is the current (old) CCSR. Let's
542 * verify that, otherwise we won't be able to move it.
543 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
544 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
547 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
548 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
549 #ifdef CONFIG_FSL_CORENET
550 lwz r1, 4(r9) /* CCSRBARL */
552 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
559 * If the value we read from CCSRBARL is not what we expect, then
560 * enter an infinite loop. This will at least allow a debugger to
561 * halt execution and examine TLBs, etc. There's no point in going
565 bne infinite_debug_loop
567 #ifdef CONFIG_FSL_CORENET
569 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
570 #define LAW_EN 0x80000000
571 #define LAW_SIZE_4K 0xb
572 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
573 #define CCSRAR_C 0x80000000 /* Commit */
577 * On CoreNet systems, we create the temporary LAW using a special LAW
578 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
580 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
581 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
582 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
583 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
584 lis r2, CCSRBAR_LAWAR@h
585 ori r2, r2, CCSRBAR_LAWAR@l
587 stw r0, 0xc00(r9) /* LAWBARH0 */
588 stw r1, 0xc04(r9) /* LAWBARL0 */
590 stw r2, 0xc08(r9) /* LAWAR0 */
593 * Read back from LAWAR to ensure the update is complete. e500mc
594 * cores also require an isync.
596 lwz r0, 0xc08(r9) /* LAWAR0 */
600 * Read the current CCSRBARH and CCSRBARL using load word instructions.
601 * Follow this with an isync instruction. This forces any outstanding
602 * accesses to configuration space to completion.
605 lwz r0, 0(r9) /* CCSRBARH */
606 lwz r0, 4(r9) /* CCSRBARL */
610 * Write the new values for CCSRBARH and CCSRBARL to their old
611 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
612 * has a new value written it loads a CCSRBARH shadow register. When
613 * the CCSRBARL is written, the CCSRBARH shadow register contents
614 * along with the CCSRBARL value are loaded into the CCSRBARH and
615 * CCSRBARL registers, respectively. Follow this with a sync
619 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
620 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
621 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
622 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
624 ori r2, r2, CCSRAR_C@l
626 stw r0, 0(r9) /* Write to CCSRBARH */
627 sync /* Make sure we write to CCSRBARH first */
628 stw r1, 4(r9) /* Write to CCSRBARL */
632 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
633 * Follow this with a sync instruction.
638 /* Delete the temporary LAW */
647 #else /* #ifdef CONFIG_FSL_CORENET */
651 * Read the current value of CCSRBAR using a load word instruction
652 * followed by an isync. This forces all accesses to configuration
659 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
660 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
661 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
663 /* Write the new value to CCSRBAR. */
664 lis r0, CCSRBAR_PHYS_RS12@h
665 ori r0, r0, CCSRBAR_PHYS_RS12@l
670 * The manual says to perform a load of an address that does not
671 * access configuration space or the on-chip SRAM using an existing TLB,
672 * but that doesn't appear to be necessary. We will do the isync,
678 * Read the contents of CCSRBAR from its new location, followed by
684 #endif /* #ifdef CONFIG_FSL_CORENET */
686 /* Delete the temporary TLBs */
688 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
689 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
691 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
693 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
696 * Create a TLB for the MMR location of CCSR
697 * to access L2CSR0 register
699 create_tlb0_entry 0, \
700 0, BOOKE_PAGESZ_4K, \
701 CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
702 CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
703 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
705 enable_l2_cluster_l2:
706 /* enable L2 cache */
707 lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
708 ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
709 li r4, 33 /* stash id */
711 lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
712 ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
714 stw r4, 0(r3) /* invalidate L2 */
721 lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
722 ori r4, r4, (L2CSR0_L2REP_MODE)@l
724 stw r4, 0(r3) /* enable L2 */
726 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
730 * Enable the L1. On e6500, this has to be done
731 * after the L2 is up.
734 #ifdef CONFIG_SYS_CACHE_STASHING
735 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
740 /* Enable/invalidate the I-Cache */
741 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
742 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
749 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
750 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
755 andi. r1,r3,L1CSR1_ICE@l
758 /* Enable/invalidate the D-Cache */
759 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
760 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
767 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
768 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
773 andi. r1,r3,L1CSR0_DCE@l
775 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
776 #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
777 #define LAW_SIZE_1M 0x13
778 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
784 * Create a TLB entry for CCSR
786 * We're executing out of TLB1 entry in r14, and that's the only
787 * TLB entry that exists. To allocate some TLB entries for our
788 * own use, flip a bit high enough that we won't flip it again
793 lis r0, MAS0_TLBSEL(1)@h
794 rlwimi r0, r8, 16, MAS0_ESEL_MSK
795 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
796 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
797 lis r7, CONFIG_SYS_CCSRBAR@h
798 ori r7, r7, CONFIG_SYS_CCSRBAR@l
799 ori r2, r7, MAS2_I|MAS2_G
800 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
801 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
802 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
803 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
814 /* Map DCSR temporarily to physical address zero */
816 lis r3, DCSRBAR_LAWAR@h
817 ori r3, r3, DCSRBAR_LAWAR@l
819 stw r0, 0xc00(r7) /* LAWBARH0 */
820 stw r0, 0xc04(r7) /* LAWBARL0 */
822 stw r3, 0xc08(r7) /* LAWAR0 */
824 /* Read back from LAWAR to ensure the update is complete. */
825 lwz r3, 0xc08(r7) /* LAWAR0 */
828 /* Create a TLB entry for DCSR at zero */
831 lis r0, MAS0_TLBSEL(1)@h
832 rlwimi r0, r9, 16, MAS0_ESEL_MSK
833 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
834 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
835 li r6, 0 /* DCSR effective address */
836 ori r2, r6, MAS2_I|MAS2_G
837 li r3, MAS3_SW|MAS3_SR
849 /* enable the timebase */
850 #define CTBENR 0xe2084
852 addis r4, r7, CTBENR@ha
858 .macro erratum_set_ccsr offset value
859 addis r3, r7, \offset@ha
861 addi r3, r3, \offset@l
866 .macro erratum_set_dcsr offset value
867 addis r3, r6, \offset@ha
869 addi r3, r3, \offset@l
874 erratum_set_dcsr 0xb0e08 0xe0201800
875 erratum_set_dcsr 0xb0e18 0xe0201800
876 erratum_set_dcsr 0xb0e38 0xe0400000
877 erratum_set_dcsr 0xb0008 0x00900000
878 erratum_set_dcsr 0xb0e40 0xe00a0000
879 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
880 erratum_set_ccsr 0x10f00 0x415e5000
881 erratum_set_ccsr 0x11f00 0x415e5000
883 /* Make temp mapping uncacheable again, if it was initially */
888 rlwimi r4, r15, 0, MAS2_I
889 rlwimi r4, r15, 0, MAS2_G
896 /* Clear the cache */
897 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
898 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
908 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
909 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
919 /* Remove temporary mappings */
920 lis r0, MAS0_TLBSEL(1)@h
921 rlwimi r0, r9, 16, MAS0_ESEL_MSK
931 stw r3, 0xc08(r7) /* LAWAR0 */
935 lis r0, MAS0_TLBSEL(1)@h
936 rlwimi r0, r8, 16, MAS0_ESEL_MSK
947 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
949 /* Lock two cache lines into I-Cache */
951 mfspr r11, SPRN_L1CSR1
952 rlwinm r11, r11, 0, ~L1CSR1_ICUL
955 mtspr SPRN_L1CSR1, r11
966 mfspr r11, SPRN_L1CSR1
967 3: andi. r11, r11, L1CSR1_ICUL
974 mfspr r11, SPRN_L1CSR1
975 3: andi. r11, r11, L1CSR1_ICUL
980 /* Inside a locked cacheline, wait a while, write, then wait a while */
984 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
985 4: mfspr r5, SPRN_TBRL
992 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
993 4: mfspr r5, SPRN_TBRL
1000 * Fill out the rest of this cache line and the next with nops,
1001 * to ensure that nothing outside the locked area will be
1002 * fetched due to a branch.
1009 mfspr r11, SPRN_L1CSR1
1010 rlwinm r11, r11, 0, ~L1CSR1_ICUL
1013 mtspr SPRN_L1CSR1, r11
1022 create_init_ram_area:
1023 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
1024 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
1027 /* create a temp mapping in AS=1 to the 4M boot window */
1028 create_tlb1_entry 15, \
1029 1, BOOKE_PAGESZ_4M, \
1030 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
1031 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1034 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
1035 /* create a temp mapping in AS = 1 for Flash mapping
1036 * created by PBL for ISBC code
1038 create_tlb1_entry 15, \
1039 1, BOOKE_PAGESZ_1M, \
1040 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1041 CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1045 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
1046 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
1048 create_tlb1_entry 15, \
1049 1, BOOKE_PAGESZ_1M, \
1050 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1051 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1055 /* create a temp mapping in AS=1 to the stack */
1056 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
1057 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
1058 create_tlb1_entry 14, \
1059 1, BOOKE_PAGESZ_16K, \
1060 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1061 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
1062 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
1065 create_tlb1_entry 14, \
1066 1, BOOKE_PAGESZ_16K, \
1067 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1068 CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
1072 lis r6,MSR_IS|MSR_DS|MSR_DE@h
1073 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
1075 ori r7,r7,switch_as@l
1082 /* L1 DCache is used for initial RAM */
1084 /* Allocate Initial RAM in data cache.
1086 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1087 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1090 /* cache size * 1024 / (2 * L1 line size) */
1091 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
1097 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1100 /* Jump out the last 4K page and continue to 'normal' start */
1101 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
1102 /* We assume that we're already running at the address we're linked at */
1105 /* Calculate absolute address in FLASH and jump there */
1106 /*--------------------------------------------------------------*/
1107 lis r3,CONFIG_SYS_MONITOR_BASE@h
1108 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
1109 addi r3,r3,_start_cont - _start + _START_OFFSET
1117 .long 0x27051956 /* U-BOOT Magic Number */
1118 .globl version_string
1120 .ascii U_BOOT_VERSION_STRING, "\0"
1125 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
1126 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1127 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
1129 stw r0,0(r3) /* Terminate Back Chain */
1130 stw r0,+4(r3) /* NULL return address. */
1131 mr r1,r3 /* Transfer to SP(r1) */
1136 /* switch back to AS = 0 */
1137 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1138 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1146 /* NOTREACHED - board_init_f() does not return */
1149 . = EXC_OFF_SYS_RESET
1150 .globl _start_of_vectors
1153 /* Critical input. */
1154 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
1157 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
1159 /* Data Storage exception. */
1160 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
1162 /* Instruction Storage exception. */
1163 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
1165 /* External Interrupt exception. */
1166 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
1168 /* Alignment exception. */
1171 EXCEPTION_PROLOG(SRR0, SRR1)
1176 addi r3,r1,STACK_FRAME_OVERHEAD
1177 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
1179 /* Program check exception */
1182 EXCEPTION_PROLOG(SRR0, SRR1)
1183 addi r3,r1,STACK_FRAME_OVERHEAD
1184 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
1185 MSR_KERNEL, COPY_EE)
1187 /* No FPU on MPC85xx. This exception is not supposed to happen.
1189 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
1193 * r0 - SYSCALL number
1197 addis r11,r0,0 /* get functions table addr */
1198 ori r11,r11,0 /* Note: this code is patched in trap_init */
1199 addis r12,r0,0 /* get number of functions */
1205 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
1209 li r20,0xd00-4 /* Get stack pointer */
1211 subi r12,r12,12 /* Adjust stack pointer */
1212 li r0,0xc00+_end_back-SystemCall
1213 cmplw 0,r0,r12 /* Check stack overflow */
1224 li r12,0xc00+_back-SystemCall
1232 mfmsr r11 /* Disable interrupts */
1236 SYNC /* Some chip revs need this... */
1240 li r12,0xd00-4 /* restore regs */
1250 addi r12,r12,12 /* Adjust stack pointer */
1258 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
1259 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
1260 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
1262 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
1263 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
1265 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
1267 .globl _end_of_vectors
1271 . = . + (0x100 - ( . & 0xff )) /* align for debug */
1274 * This code finishes saving the registers to the exception frame
1275 * and jumps to the appropriate handler for the exception.
1276 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1278 .globl transfer_to_handler
1279 transfer_to_handler:
1290 andi. r24,r23,0x3f00 /* get vector offset */
1294 mtspr SPRG2,r22 /* r1 is now kernel sp */
1296 lwz r24,0(r23) /* virtual address of handler */
1297 lwz r23,4(r23) /* where to go when done */
1302 rfi /* jump to handler, enable MMU */
1305 mfmsr r28 /* Disable interrupts */
1309 SYNC /* Some chip revs need this... */
1324 lwz r2,_NIP(r1) /* Restore environment */
1335 mfmsr r28 /* Disable interrupts */
1339 SYNC /* Some chip revs need this... */
1354 lwz r2,_NIP(r1) /* Restore environment */
1365 mfmsr r28 /* Disable interrupts */
1369 SYNC /* Some chip revs need this... */
1384 lwz r2,_NIP(r1) /* Restore environment */
1386 mtspr SPRN_MCSRR0,r2
1387 mtspr SPRN_MCSRR1,r0
1398 .globl invalidate_icache
1401 ori r0,r0,L1CSR1_ICFI
1406 blr /* entire I cache */
1408 .globl invalidate_dcache
1411 ori r0,r0,L1CSR0_DCFI
1418 .globl icache_enable
1421 bl invalidate_icache
1431 .globl icache_disable
1435 ori r3,r3,L1CSR1_ICE
1441 .globl icache_status
1444 andi. r3,r3,L1CSR1_ICE
1447 .globl dcache_enable
1450 bl invalidate_dcache
1462 .globl dcache_disable
1466 ori r4,r4,L1CSR0_DCE
1472 .globl dcache_status
1475 andi. r3,r3,L1CSR0_DCE
1498 /*------------------------------------------------------------------------------- */
1500 /* Description: Input 8 bits */
1501 /*------------------------------------------------------------------------------- */
1507 /*------------------------------------------------------------------------------- */
1508 /* Function: out8 */
1509 /* Description: Output 8 bits */
1510 /*------------------------------------------------------------------------------- */
1517 /*------------------------------------------------------------------------------- */
1518 /* Function: out16 */
1519 /* Description: Output 16 bits */
1520 /*------------------------------------------------------------------------------- */
1527 /*------------------------------------------------------------------------------- */
1528 /* Function: out16r */
1529 /* Description: Byte reverse and output 16 bits */
1530 /*------------------------------------------------------------------------------- */
1537 /*------------------------------------------------------------------------------- */
1538 /* Function: out32 */
1539 /* Description: Output 32 bits */
1540 /*------------------------------------------------------------------------------- */
1547 /*------------------------------------------------------------------------------- */
1548 /* Function: out32r */
1549 /* Description: Byte reverse and output 32 bits */
1550 /*------------------------------------------------------------------------------- */
1557 /*------------------------------------------------------------------------------- */
1558 /* Function: in16 */
1559 /* Description: Input 16 bits */
1560 /*------------------------------------------------------------------------------- */
1566 /*------------------------------------------------------------------------------- */
1567 /* Function: in16r */
1568 /* Description: Input 16 bits and byte reverse */
1569 /*------------------------------------------------------------------------------- */
1575 /*------------------------------------------------------------------------------- */
1576 /* Function: in32 */
1577 /* Description: Input 32 bits */
1578 /*------------------------------------------------------------------------------- */
1584 /*------------------------------------------------------------------------------- */
1585 /* Function: in32r */
1586 /* Description: Input 32 bits and byte reverse */
1587 /*------------------------------------------------------------------------------- */
1592 #endif /* !MINIMAL_SPL */
1594 /*------------------------------------------------------------------------------*/
1597 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1605 #ifdef CONFIG_ENABLE_36BIT_PHYS
1609 #ifdef CONFIG_SYS_BOOK3E_HV
1619 * void relocate_code (addr_sp, gd, addr_moni)
1621 * This "function" does not return, instead it continues in RAM
1622 * after relocating the monitor code.
1626 * r5 = length in bytes
1627 * r6 = cachelinesize
1629 .globl relocate_code
1631 mr r1,r3 /* Set new stack pointer */
1632 mr r9,r4 /* Save copy of Init Data pointer */
1633 mr r10,r5 /* Save copy of Destination Address */
1636 mr r3,r5 /* Destination Address */
1637 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1638 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1639 lwz r5,GOT(__init_end)
1641 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1646 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1652 /* First our own GOT */
1654 /* the the one used by the C code */
1664 beq cr1,4f /* In place copy is not necessary */
1665 beq 7f /* Protect against 0 count */
1684 * Now flush the cache: note that we must start from a cache aligned
1685 * address. Otherwise we might miss one cache line.
1689 beq 7f /* Always flush prefetch queue in any case */
1697 sync /* Wait for all dcbst to complete on bus */
1703 7: sync /* Wait for all icbi to complete on bus */
1707 * We are done. Do not return, instead branch to second part of board
1708 * initialization, now running from RAM.
1711 addi r0,r10,in_ram - _start + _START_OFFSET
1714 * As IVPR is going to point RAM address,
1715 * Make sure IVOR15 has valid opcode to support debugger
1720 * Re-point the IVPR at RAM
1725 blr /* NEVER RETURNS! */
1730 * Relocation Function, r12 point to got2+0x8000
1732 * Adjust got2 pointers, no need to check for 0, this code
1733 * already puts a few entries in the table.
1735 li r0,__got2_entries@sectoff@l
1736 la r3,GOT(_GOT2_TABLE_)
1737 lwz r11,GOT(_GOT2_TABLE_)
1749 * Now adjust the fixups and the pointers to the fixups
1750 * in case we need to move ourselves again.
1752 li r0,__fixup_entries@sectoff@l
1753 lwz r3,GOT(_FIXUP_TABLE_)
1769 * Now clear BSS segment
1771 lwz r3,GOT(__bss_start)
1772 lwz r4,GOT(__bss_end)
1785 mr r3,r9 /* Init Data pointer */
1786 mr r4,r10 /* Destination Address */
1791 * Copy exception vector code to low memory
1794 * r7: source address, r8: end address, r9: target address
1798 mflr r4 /* save link register */
1800 lwz r7,GOT(_start_of_vectors)
1801 lwz r8,GOT(_end_of_vectors)
1803 li r9,0x100 /* reset vector always at 0x100 */
1806 bgelr /* return if r7>=r8 - just in case */
1816 * relocate `hdlr' and `int_return' entries
1818 li r7,.L_CriticalInput - _start + _START_OFFSET
1820 li r7,.L_MachineCheck - _start + _START_OFFSET
1822 li r7,.L_DataStorage - _start + _START_OFFSET
1824 li r7,.L_InstStorage - _start + _START_OFFSET
1826 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1828 li r7,.L_Alignment - _start + _START_OFFSET
1830 li r7,.L_ProgramCheck - _start + _START_OFFSET
1832 li r7,.L_FPUnavailable - _start + _START_OFFSET
1834 li r7,.L_Decrementer - _start + _START_OFFSET
1836 li r7,.L_IntervalTimer - _start + _START_OFFSET
1837 li r8,_end_of_vectors - _start + _START_OFFSET
1840 addi r7,r7,0x100 /* next exception vector */
1844 /* Update IVORs as per relocated vector table address */
1846 mtspr IVOR0,r7 /* 0: Critical input */
1848 mtspr IVOR1,r7 /* 1: Machine check */
1850 mtspr IVOR2,r7 /* 2: Data storage */
1852 mtspr IVOR3,r7 /* 3: Instruction storage */
1854 mtspr IVOR4,r7 /* 4: External interrupt */
1856 mtspr IVOR5,r7 /* 5: Alignment */
1858 mtspr IVOR6,r7 /* 6: Program check */
1860 mtspr IVOR7,r7 /* 7: floating point unavailable */
1862 mtspr IVOR8,r7 /* 8: System call */
1863 /* 9: Auxiliary processor unavailable(unsupported) */
1865 mtspr IVOR10,r7 /* 10: Decrementer */
1867 mtspr IVOR11,r7 /* 11: Interval timer */
1869 mtspr IVOR12,r7 /* 12: Watchdog timer */
1871 mtspr IVOR13,r7 /* 13: Data TLB error */
1873 mtspr IVOR14,r7 /* 14: Instruction TLB error */
1875 mtspr IVOR15,r7 /* 15: Debug */
1880 mtlr r4 /* restore link register */
1883 .globl unlock_ram_in_cache
1884 unlock_ram_in_cache:
1885 /* invalidate the INIT_RAM section */
1886 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1887 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1890 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1894 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1898 /* Invalidate the TLB entries for the cache */
1899 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1900 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1913 mfspr r3,SPRN_L1CFG0
1915 rlwinm r5,r3,9,3 /* Extract cache block size */
1916 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1917 * are currently defined.
1920 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1921 * log2(number of ways)
1923 slw r5,r4,r5 /* r5 = cache block size */
1925 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1926 mulli r7,r7,13 /* An 8-way cache will require 13
1931 /* save off HID0 and set DCFA */
1933 ori r9,r8,HID0_DCFA@l
1940 1: lwz r3,0(r4) /* Load... */
1948 1: dcbf 0,r4 /* ...and flush. */
1961 #include "fixed_ivor.S"
1963 #endif /* !MINIMAL_SPL */