2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
31 #include <asm-offsets.h>
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
45 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
48 * Set up GOT: Global Offset Table
50 * Use r12 to access the GOT
53 GOT_ENTRY(_GOT2_TABLE_)
54 GOT_ENTRY(_FIXUP_TABLE_)
56 #ifndef CONFIG_NAND_SPL
58 GOT_ENTRY(_start_of_vectors)
59 GOT_ENTRY(_end_of_vectors)
60 GOT_ENTRY(transfer_to_handler)
64 GOT_ENTRY(__bss_end__)
65 GOT_ENTRY(__bss_start)
69 * e500 Startup -- after reset only the last 4KB of the effective
70 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
71 * section is located at THIS LAST page and basically does three
72 * things: clear some registers, set up exception tables and
73 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
74 * continue the boot procedure.
76 * Once the boot rom is mapped by TLB entries we can proceed
77 * with normal startup.
85 /* Enable debug exception */
89 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
92 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
96 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
97 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
102 /* Not a supported revision affected by erratum */
106 1: li r27,1 /* Remember for later that we have the erratum */
107 /* Erratum says set bits 55:60 to 001001 */
118 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
119 /* ISBC uses L2 as stack.
120 * Disable L2 cache here so that u-boot can enable it later
121 * as part of it's normal flow
124 /* Check if L2 is enabled */
125 mfspr r3, SPRN_L2CSR0
127 ori r2, r2, L2CSR0_L2E@l
131 mfspr r3, SPRN_L2CSR0
133 lis r2,(L2CSR0_L2FL)@h
134 ori r2, r2, (L2CSR0_L2FL)@l
141 mfspr r3, SPRN_L2CSR0
145 mfspr r3, SPRN_L2CSR0
147 ori r2, r2, L2CSR0_L2E@l
157 /* clear registers/arrays not reset by hardware */
161 mtspr L1CSR0,r0 /* invalidate d-cache */
162 mtspr L1CSR1,r0 /* invalidate i-cache */
165 mtspr DBSR,r1 /* Clear all valid bits */
168 * Enable L1 Caches early
172 #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
173 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
178 /* Enable/invalidate the I-Cache */
179 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
180 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
187 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
188 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
193 andi. r1,r3,L1CSR1_ICE@l
196 /* Enable/invalidate the D-Cache */
197 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
198 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
205 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
206 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
211 andi. r1,r3,L1CSR0_DCE@l
214 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
216 * TLB entry for debuggging in AS1
217 * Create temporary TLB entry in AS0 to handle debug exception
218 * As on debug exception MSR is cleared i.e. Address space is changed
219 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
223 lis r6,FSL_BOOKE_MAS0(1,
224 CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h
225 ori r6,r6,FSL_BOOKE_MAS0(1,
226 CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l
228 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
230 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
231 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
232 * and this window is outside of 4K boot window.
234 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h
235 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l
237 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
239 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
242 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
243 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
244 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
245 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
246 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
247 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
249 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h
250 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l
252 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
253 (MAS3_SX|MAS3_SW|MAS3_SR))@h
254 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
255 (MAS3_SX|MAS3_SW|MAS3_SR))@l
258 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
259 * because "nexti" will resize TLB to 4K
261 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h
262 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l
264 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h
265 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,
267 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
268 (MAS3_SX|MAS3_SW|MAS3_SR))@h
269 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
270 (MAS3_SX|MAS3_SW|MAS3_SR))@l
281 * Ne need to setup interrupt vector for NAND SPL
282 * because NAND SPL never compiles it.
284 #if !defined(CONFIG_NAND_SPL)
285 /* Setup interrupt vectors */
286 lis r1,CONFIG_SYS_MONITOR_BASE@h
289 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
290 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
292 addi r4,r3,CriticalInput - _start + _START_OFFSET
293 mtspr IVOR0,r4 /* 0: Critical input */
294 addi r4,r3,MachineCheck - _start + _START_OFFSET
295 mtspr IVOR1,r4 /* 1: Machine check */
296 addi r4,r3,DataStorage - _start + _START_OFFSET
297 mtspr IVOR2,r4 /* 2: Data storage */
298 addi r4,r3,InstStorage - _start + _START_OFFSET
299 mtspr IVOR3,r4 /* 3: Instruction storage */
300 addi r4,r3,ExtInterrupt - _start + _START_OFFSET
301 mtspr IVOR4,r4 /* 4: External interrupt */
302 addi r4,r3,Alignment - _start + _START_OFFSET
303 mtspr IVOR5,r4 /* 5: Alignment */
304 addi r4,r3,ProgramCheck - _start + _START_OFFSET
305 mtspr IVOR6,r4 /* 6: Program check */
306 addi r4,r3,FPUnavailable - _start + _START_OFFSET
307 mtspr IVOR7,r4 /* 7: floating point unavailable */
308 addi r4,r3,SystemCall - _start + _START_OFFSET
309 mtspr IVOR8,r4 /* 8: System call */
310 /* 9: Auxiliary processor unavailable(unsupported) */
311 addi r4,r3,Decrementer - _start + _START_OFFSET
312 mtspr IVOR10,r4 /* 10: Decrementer */
313 addi r4,r3,IntervalTimer - _start + _START_OFFSET
314 mtspr IVOR11,r4 /* 11: Interval timer */
315 addi r4,r3,WatchdogTimer - _start + _START_OFFSET
316 mtspr IVOR12,r4 /* 12: Watchdog timer */
317 addi r4,r3,DataTLBError - _start + _START_OFFSET
318 mtspr IVOR13,r4 /* 13: Data TLB error */
319 addi r4,r3,InstructionTLBError - _start + _START_OFFSET
320 mtspr IVOR14,r4 /* 14: Instruction TLB error */
321 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
322 mtspr IVOR15,r4 /* 15: Debug */
325 /* Clear and set up some registers. */
328 mtspr DEC,r0 /* prevent dec exceptions */
329 mttbl r0 /* prevent fit & wdt exceptions */
331 mtspr TSR,r1 /* clear all timer exception status */
332 mtspr TCR,r0 /* disable all */
333 mtspr ESR,r0 /* clear exception syndrome register */
334 mtspr MCSR,r0 /* machine check syndrome register */
335 mtxer r0 /* clear integer exception register */
337 #ifdef CONFIG_SYS_BOOK3E_HV
338 mtspr MAS8,r0 /* make sure MAS8 is clear */
341 /* Enable Time Base and Select Time Base Clock */
342 lis r0,HID0_EMCP@h /* Enable machine check */
343 #if defined(CONFIG_ENABLE_36BIT_PHYS)
344 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
346 #ifndef CONFIG_E500MC
347 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
351 #ifndef CONFIG_E500MC
352 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
355 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
357 /* Set MBDD bit also */
358 ori r0, r0, HID1_MBDD@l
363 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
369 /* Enable Branch Prediction */
370 #if defined(CONFIG_BTB)
371 lis r0,BUCSR_ENABLE@h
372 ori r0,r0,BUCSR_ENABLE@l
376 #if defined(CONFIG_SYS_INIT_DBCR)
379 mtspr DBSR,r1 /* Clear all status bits */
380 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
381 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
385 #ifdef CONFIG_MPC8569
386 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
387 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
389 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
390 * use address space which is more than 12bits, and it must be done in
391 * the 4K boot page. So we set this bit here.
394 /* create a temp mapping TLB0[0] for LBCR */
395 lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h
396 ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
398 lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
399 ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
401 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
402 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
404 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
405 (MAS3_SX|MAS3_SW|MAS3_SR))@h
406 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
407 (MAS3_SX|MAS3_SW|MAS3_SR))@l
417 /* Set LBCR register */
418 lis r4,CONFIG_SYS_LBCR_ADDR@h
419 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
421 lis r5,CONFIG_SYS_LBC_LBCR@h
422 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
426 /* invalidate this temp TLB */
427 lis r4,CONFIG_SYS_LBC_ADDR@h
428 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
432 #endif /* CONFIG_MPC8569 */
435 * Search for the TLB that covers the code we're executing, and shrink it
436 * so that it covers only this 4K page. That will ensure that any other
437 * TLB we create won't interfere with it. We assume that the TLB exists,
438 * which is why we don't check the Valid bit of MAS1.
440 * This is necessary, for example, when booting from the on-chip ROM,
441 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
442 * If we don't shrink this TLB now, then we'll accidentally delete it
443 * in "purge_old_ccsr_tlb" below.
445 bl nexti /* Find our address */
446 nexti: mflr r1 /* R1 = our PC */
448 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
451 tlbsx 0, r1 /* This must succeed */
453 /* Set the size of the TLB to 4KB */
456 andc r3, r3, r2 /* Clear the TSIZE bits */
457 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
461 * Set the base address of the TLB to our PC. We assume that
462 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
465 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
467 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
472 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
475 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
476 rlwinm r2, r2, 0, ~MAS2_I
480 mtspr MAS2, r2 /* Set the EPN to our PC base address */
485 mtspr MAS3, r2 /* Set the RPN to our PC base address */
492 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
493 * location is not where we want it. This typically happens on a 36-bit
494 * system, where we want to move CCSR to near the top of 36-bit address space.
496 * To move CCSR, we create two temporary TLBs, one for the old location, and
497 * another for the new location. On CoreNet systems, we also need to create
498 * a special, temporary LAW.
500 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
501 * long-term TLBs, so we use TLB0 here.
503 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
505 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
506 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
510 lis r8, CONFIG_SYS_CCSRBAR@h
511 ori r8, r8, CONFIG_SYS_CCSRBAR@l
512 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
513 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
516 * In a multi-stage boot (e.g. NAND boot), a previous stage may have
517 * created a TLB for CCSR, which will interfere with our relocation
518 * code. Since we're going to create a new TLB for CCSR anyway,
519 * it should be safe to delete this old TLB here. We have to search
524 mtspr MAS6, r1 /* Search the current address space and PID */
529 andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */
530 beq 1f /* Skip if no TLB found */
532 rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */
541 * Create a TLB for the new location of CCSR. Register R8 is reserved
542 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
544 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
545 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
546 lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
547 ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
548 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
549 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
550 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
551 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
552 #ifdef CONFIG_ENABLE_36BIT_PHYS
553 lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
554 ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
566 * Create a TLB for the current location of CCSR. Register R9 is reserved
567 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
570 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
571 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
572 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
573 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
574 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h
575 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l
576 #ifdef CONFIG_ENABLE_36BIT_PHYS
577 li r7, 0 /* The default CCSR address is always a 32-bit number */
581 /* MAS1 is the same as above */
589 * We have a TLB for what we think is the current (old) CCSR. Let's
590 * verify that, otherwise we won't be able to move it.
591 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
592 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
595 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
596 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
597 #ifdef CONFIG_FSL_CORENET
598 lwz r1, 4(r9) /* CCSRBARL */
600 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
607 * If the value we read from CCSRBARL is not what we expect, then
608 * enter an infinite loop. This will at least allow a debugger to
609 * halt execution and examine TLBs, etc. There's no point in going
613 bne infinite_debug_loop
615 #ifdef CONFIG_FSL_CORENET
617 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
618 #define LAW_EN 0x80000000
619 #define LAW_SIZE_4K 0xb
620 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
621 #define CCSRAR_C 0x80000000 /* Commit */
625 * On CoreNet systems, we create the temporary LAW using a special LAW
626 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
628 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
629 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
630 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
631 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
632 lis r2, CCSRBAR_LAWAR@h
633 ori r2, r2, CCSRBAR_LAWAR@l
635 stw r0, 0xc00(r9) /* LAWBARH0 */
636 stw r1, 0xc04(r9) /* LAWBARL0 */
638 stw r2, 0xc08(r9) /* LAWAR0 */
641 * Read back from LAWAR to ensure the update is complete. e500mc
642 * cores also require an isync.
644 lwz r0, 0xc08(r9) /* LAWAR0 */
648 * Read the current CCSRBARH and CCSRBARL using load word instructions.
649 * Follow this with an isync instruction. This forces any outstanding
650 * accesses to configuration space to completion.
653 lwz r0, 0(r9) /* CCSRBARH */
654 lwz r0, 4(r9) /* CCSRBARL */
658 * Write the new values for CCSRBARH and CCSRBARL to their old
659 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
660 * has a new value written it loads a CCSRBARH shadow register. When
661 * the CCSRBARL is written, the CCSRBARH shadow register contents
662 * along with the CCSRBARL value are loaded into the CCSRBARH and
663 * CCSRBARL registers, respectively. Follow this with a sync
667 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
668 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
669 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
670 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
672 ori r2, r2, CCSRAR_C@l
674 stw r0, 0(r9) /* Write to CCSRBARH */
675 sync /* Make sure we write to CCSRBARH first */
676 stw r1, 4(r9) /* Write to CCSRBARL */
680 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
681 * Follow this with a sync instruction.
686 /* Delete the temporary LAW */
695 #else /* #ifdef CONFIG_FSL_CORENET */
699 * Read the current value of CCSRBAR using a load word instruction
700 * followed by an isync. This forces all accesses to configuration
707 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
708 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
709 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
711 /* Write the new value to CCSRBAR. */
712 lis r0, CCSRBAR_PHYS_RS12@h
713 ori r0, r0, CCSRBAR_PHYS_RS12@l
718 * The manual says to perform a load of an address that does not
719 * access configuration space or the on-chip SRAM using an existing TLB,
720 * but that doesn't appear to be necessary. We will do the isync,
726 * Read the contents of CCSRBAR from its new location, followed by
732 #endif /* #ifdef CONFIG_FSL_CORENET */
734 /* Delete the temporary TLBs */
736 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
737 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
739 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
740 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
748 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
749 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
750 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
751 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
757 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
759 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
760 #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
761 #define LAW_SIZE_1M 0x13
762 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
768 * Create a TLB entry for CCSR
770 * We're executing out of TLB1 entry in r14, and that's the only
771 * TLB entry that exists. To allocate some TLB entries for our
772 * own use, flip a bit high enough that we won't flip it again
777 lis r0, MAS0_TLBSEL(1)@h
778 rlwimi r0, r8, 16, MAS0_ESEL_MSK
779 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
780 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
781 lis r7, CONFIG_SYS_CCSRBAR@h
782 ori r7, r7, CONFIG_SYS_CCSRBAR@l
783 ori r2, r7, MAS2_I|MAS2_G
784 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
785 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
786 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
787 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
798 /* Map DCSR temporarily to physical address zero */
800 lis r3, DCSRBAR_LAWAR@h
801 ori r3, r3, DCSRBAR_LAWAR@l
803 stw r0, 0xc00(r7) /* LAWBARH0 */
804 stw r0, 0xc04(r7) /* LAWBARL0 */
806 stw r3, 0xc08(r7) /* LAWAR0 */
808 /* Read back from LAWAR to ensure the update is complete. */
809 lwz r3, 0xc08(r7) /* LAWAR0 */
812 /* Create a TLB entry for DCSR at zero */
815 lis r0, MAS0_TLBSEL(1)@h
816 rlwimi r0, r9, 16, MAS0_ESEL_MSK
817 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
818 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
819 li r6, 0 /* DCSR effective address */
820 ori r2, r6, MAS2_I|MAS2_G
821 li r3, MAS3_SW|MAS3_SR
833 /* enable the timebase */
834 #define CTBENR 0xe2084
836 addis r4, r7, CTBENR@ha
842 .macro erratum_set_ccsr offset value
843 addis r3, r7, \offset@ha
845 addi r3, r3, \offset@l
850 .macro erratum_set_dcsr offset value
851 addis r3, r6, \offset@ha
853 addi r3, r3, \offset@l
858 erratum_set_dcsr 0xb0e08 0xe0201800
859 erratum_set_dcsr 0xb0e18 0xe0201800
860 erratum_set_dcsr 0xb0e38 0xe0400000
861 erratum_set_dcsr 0xb0008 0x00900000
862 erratum_set_dcsr 0xb0e40 0xe00a0000
863 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
864 erratum_set_ccsr 0x10f00 0x415e5000
865 erratum_set_ccsr 0x11f00 0x415e5000
867 /* Make temp mapping uncacheable again, if it was initially */
872 rlwimi r4, r15, 0, MAS2_I
873 rlwimi r4, r15, 0, MAS2_G
880 /* Clear the cache */
881 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
882 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
892 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
893 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
903 /* Remove temporary mappings */
904 lis r0, MAS0_TLBSEL(1)@h
905 rlwimi r0, r9, 16, MAS0_ESEL_MSK
915 stw r3, 0xc08(r7) /* LAWAR0 */
919 lis r0, MAS0_TLBSEL(1)@h
920 rlwimi r0, r8, 16, MAS0_ESEL_MSK
931 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
933 /* Lock two cache lines into I-Cache */
935 mfspr r11, SPRN_L1CSR1
936 rlwinm r11, r11, 0, ~L1CSR1_ICUL
939 mtspr SPRN_L1CSR1, r11
950 mfspr r11, SPRN_L1CSR1
951 3: andi. r11, r11, L1CSR1_ICUL
958 mfspr r11, SPRN_L1CSR1
959 3: andi. r11, r11, L1CSR1_ICUL
964 /* Inside a locked cacheline, wait a while, write, then wait a while */
968 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
969 4: mfspr r5, SPRN_TBRL
976 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
977 4: mfspr r5, SPRN_TBRL
984 * Fill out the rest of this cache line and the next with nops,
985 * to ensure that nothing outside the locked area will be
986 * fetched due to a branch.
993 mfspr r11, SPRN_L1CSR1
994 rlwinm r11, r11, 0, ~L1CSR1_ICUL
997 mtspr SPRN_L1CSR1, r11
1006 create_init_ram_area:
1007 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
1008 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
1010 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
1011 /* create a temp mapping in AS=1 to the 4M boot window */
1012 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
1013 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
1015 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
1016 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
1018 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
1019 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
1020 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
1021 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
1022 /* create a temp mapping in AS = 1 for Flash mapping
1023 * created by PBL for ISBC code
1025 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
1026 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
1028 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
1029 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
1031 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
1032 (MAS3_SX|MAS3_SW|MAS3_SR))@h
1033 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
1034 (MAS3_SX|MAS3_SW|MAS3_SR))@l
1037 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
1038 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
1040 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
1041 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
1043 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
1044 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
1046 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
1047 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
1058 /* create a temp mapping in AS=1 to the stack */
1059 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
1060 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
1062 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
1063 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
1065 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
1066 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
1068 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
1069 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
1070 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
1071 (MAS3_SX|MAS3_SW|MAS3_SR))@h
1072 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
1073 (MAS3_SX|MAS3_SW|MAS3_SR))@l
1074 li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
1077 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
1078 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
1089 lis r6,MSR_IS|MSR_DS|MSR_DE@h
1090 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
1092 ori r7,r7,switch_as@l
1099 /* L1 DCache is used for initial RAM */
1101 /* Allocate Initial RAM in data cache.
1103 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1104 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1107 /* cache size * 1024 / (2 * L1 line size) */
1108 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
1114 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1117 /* Jump out the last 4K page and continue to 'normal' start */
1118 #ifdef CONFIG_SYS_RAMBOOT
1121 /* Calculate absolute address in FLASH and jump there */
1122 /*--------------------------------------------------------------*/
1123 lis r3,CONFIG_SYS_MONITOR_BASE@h
1124 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
1125 addi r3,r3,_start_cont - _start + _START_OFFSET
1133 .long 0x27051956 /* U-BOOT Magic Number */
1134 .globl version_string
1136 .ascii U_BOOT_VERSION_STRING, "\0"
1141 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
1142 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1143 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
1145 stw r0,0(r3) /* Terminate Back Chain */
1146 stw r0,+4(r3) /* NULL return address. */
1147 mr r1,r3 /* Transfer to SP(r1) */
1152 /* switch back to AS = 0 */
1153 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1154 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1162 /* NOTREACHED - board_init_f() does not return */
1164 #ifndef CONFIG_NAND_SPL
1165 . = EXC_OFF_SYS_RESET
1166 .globl _start_of_vectors
1169 /* Critical input. */
1170 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
1173 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
1175 /* Data Storage exception. */
1176 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
1178 /* Instruction Storage exception. */
1179 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
1181 /* External Interrupt exception. */
1182 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
1184 /* Alignment exception. */
1187 EXCEPTION_PROLOG(SRR0, SRR1)
1192 addi r3,r1,STACK_FRAME_OVERHEAD
1193 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
1195 /* Program check exception */
1198 EXCEPTION_PROLOG(SRR0, SRR1)
1199 addi r3,r1,STACK_FRAME_OVERHEAD
1200 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
1201 MSR_KERNEL, COPY_EE)
1203 /* No FPU on MPC85xx. This exception is not supposed to happen.
1205 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
1209 * r0 - SYSCALL number
1213 addis r11,r0,0 /* get functions table addr */
1214 ori r11,r11,0 /* Note: this code is patched in trap_init */
1215 addis r12,r0,0 /* get number of functions */
1221 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
1225 li r20,0xd00-4 /* Get stack pointer */
1227 subi r12,r12,12 /* Adjust stack pointer */
1228 li r0,0xc00+_end_back-SystemCall
1229 cmplw 0,r0,r12 /* Check stack overflow */
1240 li r12,0xc00+_back-SystemCall
1248 mfmsr r11 /* Disable interrupts */
1252 SYNC /* Some chip revs need this... */
1256 li r12,0xd00-4 /* restore regs */
1266 addi r12,r12,12 /* Adjust stack pointer */
1274 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
1275 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
1276 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
1278 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
1279 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
1281 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
1283 .globl _end_of_vectors
1287 . = . + (0x100 - ( . & 0xff )) /* align for debug */
1290 * This code finishes saving the registers to the exception frame
1291 * and jumps to the appropriate handler for the exception.
1292 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1294 .globl transfer_to_handler
1295 transfer_to_handler:
1306 andi. r24,r23,0x3f00 /* get vector offset */
1310 mtspr SPRG2,r22 /* r1 is now kernel sp */
1312 lwz r24,0(r23) /* virtual address of handler */
1313 lwz r23,4(r23) /* where to go when done */
1318 rfi /* jump to handler, enable MMU */
1321 mfmsr r28 /* Disable interrupts */
1325 SYNC /* Some chip revs need this... */
1340 lwz r2,_NIP(r1) /* Restore environment */
1351 mfmsr r28 /* Disable interrupts */
1355 SYNC /* Some chip revs need this... */
1370 lwz r2,_NIP(r1) /* Restore environment */
1381 mfmsr r28 /* Disable interrupts */
1385 SYNC /* Some chip revs need this... */
1400 lwz r2,_NIP(r1) /* Restore environment */
1402 mtspr SPRN_MCSRR0,r2
1403 mtspr SPRN_MCSRR1,r0
1414 .globl invalidate_icache
1417 ori r0,r0,L1CSR1_ICFI
1422 blr /* entire I cache */
1424 .globl invalidate_dcache
1427 ori r0,r0,L1CSR0_DCFI
1434 .globl icache_enable
1437 bl invalidate_icache
1447 .globl icache_disable
1451 ori r3,r3,L1CSR1_ICE
1457 .globl icache_status
1460 andi. r3,r3,L1CSR1_ICE
1463 .globl dcache_enable
1466 bl invalidate_dcache
1478 .globl dcache_disable
1482 ori r4,r4,L1CSR0_DCE
1488 .globl dcache_status
1491 andi. r3,r3,L1CSR0_DCE
1514 /*------------------------------------------------------------------------------- */
1516 /* Description: Input 8 bits */
1517 /*------------------------------------------------------------------------------- */
1523 /*------------------------------------------------------------------------------- */
1524 /* Function: out8 */
1525 /* Description: Output 8 bits */
1526 /*------------------------------------------------------------------------------- */
1533 /*------------------------------------------------------------------------------- */
1534 /* Function: out16 */
1535 /* Description: Output 16 bits */
1536 /*------------------------------------------------------------------------------- */
1543 /*------------------------------------------------------------------------------- */
1544 /* Function: out16r */
1545 /* Description: Byte reverse and output 16 bits */
1546 /*------------------------------------------------------------------------------- */
1553 /*------------------------------------------------------------------------------- */
1554 /* Function: out32 */
1555 /* Description: Output 32 bits */
1556 /*------------------------------------------------------------------------------- */
1563 /*------------------------------------------------------------------------------- */
1564 /* Function: out32r */
1565 /* Description: Byte reverse and output 32 bits */
1566 /*------------------------------------------------------------------------------- */
1573 /*------------------------------------------------------------------------------- */
1574 /* Function: in16 */
1575 /* Description: Input 16 bits */
1576 /*------------------------------------------------------------------------------- */
1582 /*------------------------------------------------------------------------------- */
1583 /* Function: in16r */
1584 /* Description: Input 16 bits and byte reverse */
1585 /*------------------------------------------------------------------------------- */
1591 /*------------------------------------------------------------------------------- */
1592 /* Function: in32 */
1593 /* Description: Input 32 bits */
1594 /*------------------------------------------------------------------------------- */
1600 /*------------------------------------------------------------------------------- */
1601 /* Function: in32r */
1602 /* Description: Input 32 bits and byte reverse */
1603 /*------------------------------------------------------------------------------- */
1608 #endif /* !CONFIG_NAND_SPL */
1610 /*------------------------------------------------------------------------------*/
1613 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1621 #ifdef CONFIG_ENABLE_36BIT_PHYS
1625 #ifdef CONFIG_SYS_BOOK3E_HV
1635 * void relocate_code (addr_sp, gd, addr_moni)
1637 * This "function" does not return, instead it continues in RAM
1638 * after relocating the monitor code.
1642 * r5 = length in bytes
1643 * r6 = cachelinesize
1645 .globl relocate_code
1647 mr r1,r3 /* Set new stack pointer */
1648 mr r9,r4 /* Save copy of Init Data pointer */
1649 mr r10,r5 /* Save copy of Destination Address */
1652 mr r3,r5 /* Destination Address */
1653 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1654 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1655 lwz r5,GOT(__init_end)
1657 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1662 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1668 /* First our own GOT */
1670 /* the the one used by the C code */
1680 beq cr1,4f /* In place copy is not necessary */
1681 beq 7f /* Protect against 0 count */
1700 * Now flush the cache: note that we must start from a cache aligned
1701 * address. Otherwise we might miss one cache line.
1705 beq 7f /* Always flush prefetch queue in any case */
1713 sync /* Wait for all dcbst to complete on bus */
1719 7: sync /* Wait for all icbi to complete on bus */
1723 * We are done. Do not return, instead branch to second part of board
1724 * initialization, now running from RAM.
1727 addi r0,r10,in_ram - _start + _START_OFFSET
1730 * As IVPR is going to point RAM address,
1731 * Make sure IVOR15 has valid opcode to support debugger
1736 * Re-point the IVPR at RAM
1741 blr /* NEVER RETURNS! */
1746 * Relocation Function, r12 point to got2+0x8000
1748 * Adjust got2 pointers, no need to check for 0, this code
1749 * already puts a few entries in the table.
1751 li r0,__got2_entries@sectoff@l
1752 la r3,GOT(_GOT2_TABLE_)
1753 lwz r11,GOT(_GOT2_TABLE_)
1765 * Now adjust the fixups and the pointers to the fixups
1766 * in case we need to move ourselves again.
1768 li r0,__fixup_entries@sectoff@l
1769 lwz r3,GOT(_FIXUP_TABLE_)
1785 * Now clear BSS segment
1787 lwz r3,GOT(__bss_start)
1788 lwz r4,GOT(__bss_end__)
1801 mr r3,r9 /* Init Data pointer */
1802 mr r4,r10 /* Destination Address */
1805 #ifndef CONFIG_NAND_SPL
1807 * Copy exception vector code to low memory
1810 * r7: source address, r8: end address, r9: target address
1814 mflr r4 /* save link register */
1816 lwz r7,GOT(_start_of_vectors)
1817 lwz r8,GOT(_end_of_vectors)
1819 li r9,0x100 /* reset vector always at 0x100 */
1822 bgelr /* return if r7>=r8 - just in case */
1832 * relocate `hdlr' and `int_return' entries
1834 li r7,.L_CriticalInput - _start + _START_OFFSET
1836 li r7,.L_MachineCheck - _start + _START_OFFSET
1838 li r7,.L_DataStorage - _start + _START_OFFSET
1840 li r7,.L_InstStorage - _start + _START_OFFSET
1842 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1844 li r7,.L_Alignment - _start + _START_OFFSET
1846 li r7,.L_ProgramCheck - _start + _START_OFFSET
1848 li r7,.L_FPUnavailable - _start + _START_OFFSET
1850 li r7,.L_Decrementer - _start + _START_OFFSET
1852 li r7,.L_IntervalTimer - _start + _START_OFFSET
1853 li r8,_end_of_vectors - _start + _START_OFFSET
1856 addi r7,r7,0x100 /* next exception vector */
1860 /* Update IVORs as per relocated vector table address */
1862 mtspr IVOR0,r7 /* 0: Critical input */
1864 mtspr IVOR1,r7 /* 1: Machine check */
1866 mtspr IVOR2,r7 /* 2: Data storage */
1868 mtspr IVOR3,r7 /* 3: Instruction storage */
1870 mtspr IVOR4,r7 /* 4: External interrupt */
1872 mtspr IVOR5,r7 /* 5: Alignment */
1874 mtspr IVOR6,r7 /* 6: Program check */
1876 mtspr IVOR7,r7 /* 7: floating point unavailable */
1878 mtspr IVOR8,r7 /* 8: System call */
1879 /* 9: Auxiliary processor unavailable(unsupported) */
1881 mtspr IVOR10,r7 /* 10: Decrementer */
1883 mtspr IVOR11,r7 /* 11: Interval timer */
1885 mtspr IVOR12,r7 /* 12: Watchdog timer */
1887 mtspr IVOR13,r7 /* 13: Data TLB error */
1889 mtspr IVOR14,r7 /* 14: Instruction TLB error */
1891 mtspr IVOR15,r7 /* 15: Debug */
1896 mtlr r4 /* restore link register */
1899 .globl unlock_ram_in_cache
1900 unlock_ram_in_cache:
1901 /* invalidate the INIT_RAM section */
1902 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1903 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1906 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1909 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1913 /* Invalidate the TLB entries for the cache */
1914 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1915 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1928 mfspr r3,SPRN_L1CFG0
1930 rlwinm r5,r3,9,3 /* Extract cache block size */
1931 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1932 * are currently defined.
1935 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1936 * log2(number of ways)
1938 slw r5,r4,r5 /* r5 = cache block size */
1940 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1941 mulli r7,r7,13 /* An 8-way cache will require 13
1946 /* save off HID0 and set DCFA */
1948 ori r9,r8,HID0_DCFA@l
1955 1: lwz r3,0(r4) /* Load... */
1963 1: dcbf 0,r4 /* ...and flush. */
1976 #include "fixed_ivor.S"
1978 #endif /* !CONFIG_NAND_SPL */