2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
31 #include <asm-offsets.h>
34 #include <timestamp.h>
37 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
39 #include <ppc_asm.tmpl>
42 #include <asm/cache.h>
45 #ifndef CONFIG_IDENT_STRING
46 #define CONFIG_IDENT_STRING ""
50 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
53 * Set up GOT: Global Offset Table
55 * Use r12 to access the GOT
58 GOT_ENTRY(_GOT2_TABLE_)
59 GOT_ENTRY(_FIXUP_TABLE_)
61 #ifndef CONFIG_NAND_SPL
63 GOT_ENTRY(_start_of_vectors)
64 GOT_ENTRY(_end_of_vectors)
65 GOT_ENTRY(transfer_to_handler)
69 GOT_ENTRY(__bss_end__)
70 GOT_ENTRY(__bss_start)
74 * e500 Startup -- after reset only the last 4KB of the effective
75 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
76 * section is located at THIS LAST page and basically does three
77 * things: clear some registers, set up exception tables and
78 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
79 * continue the boot procedure.
81 * Once the boot rom is mapped by TLB entries we can proceed
82 * with normal startup.
91 /* clear registers/arrays not reset by hardware */
95 mtspr L1CSR0,r0 /* invalidate d-cache */
96 mtspr L1CSR1,r0 /* invalidate i-cache */
99 mtspr DBSR,r1 /* Clear all valid bits */
102 * Enable L1 Caches early
106 #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
107 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
112 /* Enable/invalidate the I-Cache */
113 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
114 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
121 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
122 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
127 andi. r1,r3,L1CSR1_ICE@l
130 /* Enable/invalidate the D-Cache */
131 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
132 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
139 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
140 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
145 andi. r1,r3,L1CSR0_DCE@l
148 /* Setup interrupt vectors */
149 lis r1,CONFIG_SYS_MONITOR_BASE@h
153 mtspr IVOR0,r1 /* 0: Critical input */
155 mtspr IVOR1,r1 /* 1: Machine check */
157 mtspr IVOR2,r1 /* 2: Data storage */
159 mtspr IVOR3,r1 /* 3: Instruction storage */
161 mtspr IVOR4,r1 /* 4: External interrupt */
163 mtspr IVOR5,r1 /* 5: Alignment */
165 mtspr IVOR6,r1 /* 6: Program check */
167 mtspr IVOR7,r1 /* 7: floating point unavailable */
169 mtspr IVOR8,r1 /* 8: System call */
170 /* 9: Auxiliary processor unavailable(unsupported) */
172 mtspr IVOR10,r1 /* 10: Decrementer */
174 mtspr IVOR11,r1 /* 11: Interval timer */
176 mtspr IVOR12,r1 /* 12: Watchdog timer */
178 mtspr IVOR13,r1 /* 13: Data TLB error */
180 mtspr IVOR14,r1 /* 14: Instruction TLB error */
182 mtspr IVOR15,r1 /* 15: Debug */
184 /* Clear and set up some registers. */
187 mtspr DEC,r0 /* prevent dec exceptions */
188 mttbl r0 /* prevent fit & wdt exceptions */
190 mtspr TSR,r1 /* clear all timer exception status */
191 mtspr TCR,r0 /* disable all */
192 mtspr ESR,r0 /* clear exception syndrome register */
193 mtspr MCSR,r0 /* machine check syndrome register */
194 mtxer r0 /* clear integer exception register */
196 #ifdef CONFIG_SYS_BOOK3E_HV
197 mtspr MAS8,r0 /* make sure MAS8 is clear */
200 /* Enable Time Base and Select Time Base Clock */
201 lis r0,HID0_EMCP@h /* Enable machine check */
202 #if defined(CONFIG_ENABLE_36BIT_PHYS)
203 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
205 #ifndef CONFIG_E500MC
206 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
210 #ifndef CONFIG_E500MC
211 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
214 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
216 /* Set MBDD bit also */
217 ori r0, r0, HID1_MBDD@l
222 /* Enable Branch Prediction */
223 #if defined(CONFIG_BTB)
224 lis r0,BUCSR_ENABLE@h
225 ori r0,r0,BUCSR_ENABLE@l
229 #if defined(CONFIG_SYS_INIT_DBCR)
232 mtspr DBSR,r1 /* Clear all status bits */
233 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
234 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
238 #ifdef CONFIG_MPC8569
239 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
240 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
242 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
243 * use address space which is more than 12bits, and it must be done in
244 * the 4K boot page. So we set this bit here.
247 /* create a temp mapping TLB0[0] for LBCR */
248 lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h
249 ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
251 lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
252 ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
254 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
255 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
257 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
258 (MAS3_SX|MAS3_SW|MAS3_SR))@h
259 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
260 (MAS3_SX|MAS3_SW|MAS3_SR))@l
270 /* Set LBCR register */
271 lis r4,CONFIG_SYS_LBCR_ADDR@h
272 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
274 lis r5,CONFIG_SYS_LBC_LBCR@h
275 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
279 /* invalidate this temp TLB */
280 lis r4,CONFIG_SYS_LBC_ADDR@h
281 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
285 #endif /* CONFIG_MPC8569 */
287 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
288 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
290 #ifndef CONFIG_SYS_RAMBOOT
291 /* create a temp mapping in AS=1 to the 4M boot window */
292 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
293 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
295 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
296 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
298 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
299 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
300 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
303 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
304 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
306 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
307 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
309 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
310 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
312 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
313 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
324 /* create a temp mapping in AS=1 to the stack */
325 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
326 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
328 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
329 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
331 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
332 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
334 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
335 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
336 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
337 (MAS3_SX|MAS3_SW|MAS3_SR))@h
338 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
339 (MAS3_SX|MAS3_SW|MAS3_SR))@l
340 li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
343 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
344 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
355 lis r6,MSR_IS|MSR_DS@h
356 ori r6,r6,MSR_IS|MSR_DS@l
358 ori r7,r7,switch_as@l
365 /* L1 DCache is used for initial RAM */
367 /* Allocate Initial RAM in data cache.
369 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
370 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
373 /* cache size * 1024 / (2 * L1 line size) */
374 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
380 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
383 /* Jump out the last 4K page and continue to 'normal' start */
384 #ifdef CONFIG_SYS_RAMBOOT
387 /* Calculate absolute address in FLASH and jump there */
388 /*--------------------------------------------------------------*/
389 lis r3,CONFIG_SYS_MONITOR_BASE@h
390 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
391 addi r3,r3,_start_cont - _start + _START_OFFSET
399 .long 0x27051956 /* U-BOOT Magic Number */
400 .globl version_string
402 .ascii U_BOOT_VERSION
403 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
404 .ascii CONFIG_IDENT_STRING, "\0"
409 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
410 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
411 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
415 stwu r0,-4(r1) /* Terminate call chain */
417 stwu r1,-8(r1) /* Save back chain and move SP */
418 lis r0,RESET_VECTOR@h /* Address of reset vector */
419 ori r0,r0,RESET_VECTOR@l
420 stwu r1,-8(r1) /* Save back chain and move SP */
421 stw r0,+12(r1) /* Save return addr (underflow vect) */
424 #if defined(__pic__) && __pic__ == 1
425 /* Needed for upcoming -msingle-pic-base */
426 bl _GLOBAL_OFFSET_TABLE_@local-4
431 /* switch back to AS = 0 */
432 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
433 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
441 /* NOTREACHED - board_init_f() does not return */
443 #ifndef CONFIG_NAND_SPL
444 . = EXC_OFF_SYS_RESET
445 .globl _start_of_vectors
448 /* Critical input. */
449 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
452 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
454 /* Data Storage exception. */
455 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
457 /* Instruction Storage exception. */
458 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
460 /* External Interrupt exception. */
461 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
463 /* Alignment exception. */
466 EXCEPTION_PROLOG(SRR0, SRR1)
471 addi r3,r1,STACK_FRAME_OVERHEAD
472 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
474 /* Program check exception */
477 EXCEPTION_PROLOG(SRR0, SRR1)
478 addi r3,r1,STACK_FRAME_OVERHEAD
479 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
482 /* No FPU on MPC85xx. This exception is not supposed to happen.
484 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
488 * r0 - SYSCALL number
492 addis r11,r0,0 /* get functions table addr */
493 ori r11,r11,0 /* Note: this code is patched in trap_init */
494 addis r12,r0,0 /* get number of functions */
500 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
504 li r20,0xd00-4 /* Get stack pointer */
506 subi r12,r12,12 /* Adjust stack pointer */
507 li r0,0xc00+_end_back-SystemCall
508 cmplw 0,r0,r12 /* Check stack overflow */
519 li r12,0xc00+_back-SystemCall
527 mfmsr r11 /* Disable interrupts */
531 SYNC /* Some chip revs need this... */
535 li r12,0xd00-4 /* restore regs */
545 addi r12,r12,12 /* Adjust stack pointer */
553 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
554 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
555 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
557 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
558 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
560 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
562 .globl _end_of_vectors
566 . = . + (0x100 - ( . & 0xff )) /* align for debug */
569 * This code finishes saving the registers to the exception frame
570 * and jumps to the appropriate handler for the exception.
571 * Register r21 is pointer into trap frame, r1 has new stack pointer.
573 .globl transfer_to_handler
585 andi. r24,r23,0x3f00 /* get vector offset */
589 mtspr SPRG2,r22 /* r1 is now kernel sp */
591 lwz r24,0(r23) /* virtual address of handler */
592 lwz r23,4(r23) /* where to go when done */
597 rfi /* jump to handler, enable MMU */
600 mfmsr r28 /* Disable interrupts */
604 SYNC /* Some chip revs need this... */
619 lwz r2,_NIP(r1) /* Restore environment */
630 mfmsr r28 /* Disable interrupts */
634 SYNC /* Some chip revs need this... */
649 lwz r2,_NIP(r1) /* Restore environment */
660 mfmsr r28 /* Disable interrupts */
664 SYNC /* Some chip revs need this... */
679 lwz r2,_NIP(r1) /* Restore environment */
691 .globl invalidate_icache
694 ori r0,r0,L1CSR1_ICFI
699 blr /* entire I cache */
701 .globl invalidate_dcache
704 ori r0,r0,L1CSR0_DCFI
724 .globl icache_disable
737 andi. r3,r3,L1CSR1_ICE
755 .globl dcache_disable
768 andi. r3,r3,L1CSR0_DCE
791 /*------------------------------------------------------------------------------- */
793 /* Description: Input 8 bits */
794 /*------------------------------------------------------------------------------- */
800 /*------------------------------------------------------------------------------- */
802 /* Description: Output 8 bits */
803 /*------------------------------------------------------------------------------- */
810 /*------------------------------------------------------------------------------- */
811 /* Function: out16 */
812 /* Description: Output 16 bits */
813 /*------------------------------------------------------------------------------- */
820 /*------------------------------------------------------------------------------- */
821 /* Function: out16r */
822 /* Description: Byte reverse and output 16 bits */
823 /*------------------------------------------------------------------------------- */
830 /*------------------------------------------------------------------------------- */
831 /* Function: out32 */
832 /* Description: Output 32 bits */
833 /*------------------------------------------------------------------------------- */
840 /*------------------------------------------------------------------------------- */
841 /* Function: out32r */
842 /* Description: Byte reverse and output 32 bits */
843 /*------------------------------------------------------------------------------- */
850 /*------------------------------------------------------------------------------- */
852 /* Description: Input 16 bits */
853 /*------------------------------------------------------------------------------- */
859 /*------------------------------------------------------------------------------- */
860 /* Function: in16r */
861 /* Description: Input 16 bits and byte reverse */
862 /*------------------------------------------------------------------------------- */
868 /*------------------------------------------------------------------------------- */
870 /* Description: Input 32 bits */
871 /*------------------------------------------------------------------------------- */
877 /*------------------------------------------------------------------------------- */
878 /* Function: in32r */
879 /* Description: Input 32 bits and byte reverse */
880 /*------------------------------------------------------------------------------- */
885 #endif /* !CONFIG_NAND_SPL */
887 /*------------------------------------------------------------------------------*/
890 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
898 #ifdef CONFIG_ENABLE_36BIT_PHYS
902 #ifdef CONFIG_SYS_BOOK3E_HV
912 * void relocate_code (addr_sp, gd, addr_moni)
914 * This "function" does not return, instead it continues in RAM
915 * after relocating the monitor code.
919 * r5 = length in bytes
924 mr r1,r3 /* Set new stack pointer */
925 mr r9,r4 /* Save copy of Init Data pointer */
926 mr r10,r5 /* Save copy of Destination Address */
929 #if defined(__pic__) && __pic__ == 1
930 /* Needed for upcoming -msingle-pic-base */
931 bl _GLOBAL_OFFSET_TABLE_@local-4
934 mr r3,r5 /* Destination Address */
935 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
936 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
937 lwz r5,GOT(__init_end)
939 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
944 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
950 /* First our own GOT */
952 /* the the one used by the C code */
962 beq cr1,4f /* In place copy is not necessary */
963 beq 7f /* Protect against 0 count */
982 * Now flush the cache: note that we must start from a cache aligned
983 * address. Otherwise we might miss one cache line.
987 beq 7f /* Always flush prefetch queue in any case */
995 sync /* Wait for all dcbst to complete on bus */
1001 7: sync /* Wait for all icbi to complete on bus */
1005 * Re-point the IVPR at RAM
1010 * We are done. Do not return, instead branch to second part of board
1011 * initialization, now running from RAM.
1014 addi r0,r10,in_ram - _start + _START_OFFSET
1016 blr /* NEVER RETURNS! */
1021 * Relocation Function, r12 point to got2+0x8000
1023 * Adjust got2 pointers, no need to check for 0, this code
1024 * already puts a few entries in the table.
1026 li r0,__got2_entries@sectoff@l
1027 la r3,GOT(_GOT2_TABLE_)
1028 lwz r11,GOT(_GOT2_TABLE_)
1040 * Now adjust the fixups and the pointers to the fixups
1041 * in case we need to move ourselves again.
1043 li r0,__fixup_entries@sectoff@l
1044 lwz r3,GOT(_FIXUP_TABLE_)
1060 * Now clear BSS segment
1062 lwz r3,GOT(__bss_start)
1063 lwz r4,GOT(__bss_end__)
1076 mr r3,r9 /* Init Data pointer */
1077 mr r4,r10 /* Destination Address */
1080 #ifndef CONFIG_NAND_SPL
1082 * Copy exception vector code to low memory
1085 * r7: source address, r8: end address, r9: target address
1089 mflr r4 /* save link register */
1091 lwz r7,GOT(_start_of_vectors)
1092 lwz r8,GOT(_end_of_vectors)
1094 li r9,0x100 /* reset vector always at 0x100 */
1097 bgelr /* return if r7>=r8 - just in case */
1107 * relocate `hdlr' and `int_return' entries
1109 li r7,.L_CriticalInput - _start + _START_OFFSET
1111 li r7,.L_MachineCheck - _start + _START_OFFSET
1113 li r7,.L_DataStorage - _start + _START_OFFSET
1115 li r7,.L_InstStorage - _start + _START_OFFSET
1117 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1119 li r7,.L_Alignment - _start + _START_OFFSET
1121 li r7,.L_ProgramCheck - _start + _START_OFFSET
1123 li r7,.L_FPUnavailable - _start + _START_OFFSET
1125 li r7,.L_Decrementer - _start + _START_OFFSET
1127 li r7,.L_IntervalTimer - _start + _START_OFFSET
1128 li r8,_end_of_vectors - _start + _START_OFFSET
1131 addi r7,r7,0x100 /* next exception vector */
1138 mtlr r4 /* restore link register */
1141 .globl unlock_ram_in_cache
1142 unlock_ram_in_cache:
1143 /* invalidate the INIT_RAM section */
1144 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1145 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1148 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1151 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1155 /* Invalidate the TLB entries for the cache */
1156 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1157 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1170 mfspr r3,SPRN_L1CFG0
1172 rlwinm r5,r3,9,3 /* Extract cache block size */
1173 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1174 * are currently defined.
1177 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1178 * log2(number of ways)
1180 slw r5,r4,r5 /* r5 = cache block size */
1182 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1183 mulli r7,r7,13 /* An 8-way cache will require 13
1188 /* save off HID0 and set DCFA */
1190 ori r9,r8,HID0_DCFA@l
1197 1: lwz r3,0(r4) /* Load... */
1205 1: dcbf 0,r4 /* ...and flush. */
1218 #include "fixed_ivor.S"
1220 #endif /* !CONFIG_NAND_SPL */