2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
31 #include <asm-offsets.h>
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
45 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
48 * Set up GOT: Global Offset Table
50 * Use r12 to access the GOT
53 GOT_ENTRY(_GOT2_TABLE_)
54 GOT_ENTRY(_FIXUP_TABLE_)
56 #ifndef CONFIG_NAND_SPL
58 GOT_ENTRY(_start_of_vectors)
59 GOT_ENTRY(_end_of_vectors)
60 GOT_ENTRY(transfer_to_handler)
64 GOT_ENTRY(__bss_end__)
65 GOT_ENTRY(__bss_start)
69 * e500 Startup -- after reset only the last 4KB of the effective
70 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
71 * section is located at THIS LAST page and basically does three
72 * things: clear some registers, set up exception tables and
73 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
74 * continue the boot procedure.
76 * Once the boot rom is mapped by TLB entries we can proceed
77 * with normal startup.
85 /* Enable debug exception */
89 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
90 /* ISBC uses L2 as stack.
91 * Disable L2 cache here so that u-boot can enable it later
92 * as part of it's normal flow
95 /* Check if L2 is enabled */
98 ori r2, r2, L2CSR0_L2E@l
102 mfspr r3, SPRN_L2CSR0
104 lis r2,(L2CSR0_L2FL)@h
105 ori r2, r2, (L2CSR0_L2FL)@l
112 mfspr r3, SPRN_L2CSR0
116 mfspr r3, SPRN_L2CSR0
118 ori r2, r2, L2CSR0_L2E@l
128 /* clear registers/arrays not reset by hardware */
132 mtspr L1CSR0,r0 /* invalidate d-cache */
133 mtspr L1CSR1,r0 /* invalidate i-cache */
136 mtspr DBSR,r1 /* Clear all valid bits */
139 * Enable L1 Caches early
143 #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
144 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
149 /* Enable/invalidate the I-Cache */
150 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
151 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
158 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
159 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
164 andi. r1,r3,L1CSR1_ICE@l
167 /* Enable/invalidate the D-Cache */
168 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
169 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
176 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
177 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
182 andi. r1,r3,L1CSR0_DCE@l
185 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
187 * TLB entry for debuggging in AS1
188 * Create temporary TLB entry in AS0 to handle debug exception
189 * As on debug exception MSR is cleared i.e. Address space is changed
190 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
194 lis r6,FSL_BOOKE_MAS0(1,
195 CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h
196 ori r6,r6,FSL_BOOKE_MAS0(1,
197 CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l
199 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
201 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
202 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
203 * and this window is outside of 4K boot window.
205 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h
206 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l
208 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
210 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
213 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
214 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
215 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
216 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
217 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
218 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
220 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h
221 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l
223 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
224 (MAS3_SX|MAS3_SW|MAS3_SR))@h
225 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
226 (MAS3_SX|MAS3_SW|MAS3_SR))@l
229 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
230 * because "nexti" will resize TLB to 4K
232 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h
233 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l
235 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h
236 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,
238 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
239 (MAS3_SX|MAS3_SW|MAS3_SR))@h
240 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
241 (MAS3_SX|MAS3_SW|MAS3_SR))@l
252 * Ne need to setup interrupt vector for NAND SPL
253 * because NAND SPL never compiles it.
255 #if !defined(CONFIG_NAND_SPL)
256 /* Setup interrupt vectors */
257 lis r1,CONFIG_SYS_MONITOR_BASE@h
260 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
261 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
263 addi r4,r3,CriticalInput - _start + _START_OFFSET
264 mtspr IVOR0,r4 /* 0: Critical input */
265 addi r4,r3,MachineCheck - _start + _START_OFFSET
266 mtspr IVOR1,r4 /* 1: Machine check */
267 addi r4,r3,DataStorage - _start + _START_OFFSET
268 mtspr IVOR2,r4 /* 2: Data storage */
269 addi r4,r3,InstStorage - _start + _START_OFFSET
270 mtspr IVOR3,r4 /* 3: Instruction storage */
271 addi r4,r3,ExtInterrupt - _start + _START_OFFSET
272 mtspr IVOR4,r4 /* 4: External interrupt */
273 addi r4,r3,Alignment - _start + _START_OFFSET
274 mtspr IVOR5,r4 /* 5: Alignment */
275 addi r4,r3,ProgramCheck - _start + _START_OFFSET
276 mtspr IVOR6,r4 /* 6: Program check */
277 addi r4,r3,FPUnavailable - _start + _START_OFFSET
278 mtspr IVOR7,r4 /* 7: floating point unavailable */
279 addi r4,r3,SystemCall - _start + _START_OFFSET
280 mtspr IVOR8,r4 /* 8: System call */
281 /* 9: Auxiliary processor unavailable(unsupported) */
282 addi r4,r3,Decrementer - _start + _START_OFFSET
283 mtspr IVOR10,r4 /* 10: Decrementer */
284 addi r4,r3,IntervalTimer - _start + _START_OFFSET
285 mtspr IVOR11,r4 /* 11: Interval timer */
286 addi r4,r3,WatchdogTimer - _start + _START_OFFSET
287 mtspr IVOR12,r4 /* 12: Watchdog timer */
288 addi r4,r3,DataTLBError - _start + _START_OFFSET
289 mtspr IVOR13,r4 /* 13: Data TLB error */
290 addi r4,r3,InstructionTLBError - _start + _START_OFFSET
291 mtspr IVOR14,r4 /* 14: Instruction TLB error */
292 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
293 mtspr IVOR15,r4 /* 15: Debug */
296 /* Clear and set up some registers. */
299 mtspr DEC,r0 /* prevent dec exceptions */
300 mttbl r0 /* prevent fit & wdt exceptions */
302 mtspr TSR,r1 /* clear all timer exception status */
303 mtspr TCR,r0 /* disable all */
304 mtspr ESR,r0 /* clear exception syndrome register */
305 mtspr MCSR,r0 /* machine check syndrome register */
306 mtxer r0 /* clear integer exception register */
308 #ifdef CONFIG_SYS_BOOK3E_HV
309 mtspr MAS8,r0 /* make sure MAS8 is clear */
312 /* Enable Time Base and Select Time Base Clock */
313 lis r0,HID0_EMCP@h /* Enable machine check */
314 #if defined(CONFIG_ENABLE_36BIT_PHYS)
315 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
317 #ifndef CONFIG_E500MC
318 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
322 #ifndef CONFIG_E500MC
323 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
326 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
328 /* Set MBDD bit also */
329 ori r0, r0, HID1_MBDD@l
334 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
340 /* Enable Branch Prediction */
341 #if defined(CONFIG_BTB)
342 lis r0,BUCSR_ENABLE@h
343 ori r0,r0,BUCSR_ENABLE@l
347 #if defined(CONFIG_SYS_INIT_DBCR)
350 mtspr DBSR,r1 /* Clear all status bits */
351 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
352 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
356 #ifdef CONFIG_MPC8569
357 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
358 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
360 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
361 * use address space which is more than 12bits, and it must be done in
362 * the 4K boot page. So we set this bit here.
365 /* create a temp mapping TLB0[0] for LBCR */
366 lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h
367 ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
369 lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
370 ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
372 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
373 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
375 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
376 (MAS3_SX|MAS3_SW|MAS3_SR))@h
377 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
378 (MAS3_SX|MAS3_SW|MAS3_SR))@l
388 /* Set LBCR register */
389 lis r4,CONFIG_SYS_LBCR_ADDR@h
390 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
392 lis r5,CONFIG_SYS_LBC_LBCR@h
393 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
397 /* invalidate this temp TLB */
398 lis r4,CONFIG_SYS_LBC_ADDR@h
399 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
403 #endif /* CONFIG_MPC8569 */
406 * Search for the TLB that covers the code we're executing, and shrink it
407 * so that it covers only this 4K page. That will ensure that any other
408 * TLB we create won't interfere with it. We assume that the TLB exists,
409 * which is why we don't check the Valid bit of MAS1.
411 * This is necessary, for example, when booting from the on-chip ROM,
412 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
413 * If we don't shrink this TLB now, then we'll accidentally delete it
414 * in "purge_old_ccsr_tlb" below.
416 bl nexti /* Find our address */
417 nexti: mflr r1 /* R1 = our PC */
419 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
422 tlbsx 0, r1 /* This must succeed */
424 /* Set the size of the TLB to 4KB */
427 andc r3, r3, r2 /* Clear the TSIZE bits */
428 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
432 * Set the base address of the TLB to our PC. We assume that
433 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
436 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
438 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
443 mtspr MAS2, r2 /* Set the EPN to our PC base address */
448 mtspr MAS3, r2 /* Set the RPN to our PC base address */
455 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
456 * location is not where we want it. This typically happens on a 36-bit
457 * system, where we want to move CCSR to near the top of 36-bit address space.
459 * To move CCSR, we create two temporary TLBs, one for the old location, and
460 * another for the new location. On CoreNet systems, we also need to create
461 * a special, temporary LAW.
463 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
464 * long-term TLBs, so we use TLB0 here.
466 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
468 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
469 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
473 lis r8, CONFIG_SYS_CCSRBAR@h
474 ori r8, r8, CONFIG_SYS_CCSRBAR@l
475 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
476 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
479 * In a multi-stage boot (e.g. NAND boot), a previous stage may have
480 * created a TLB for CCSR, which will interfere with our relocation
481 * code. Since we're going to create a new TLB for CCSR anyway,
482 * it should be safe to delete this old TLB here. We have to search
487 mtspr MAS6, r1 /* Search the current address space and PID */
492 andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */
493 beq 1f /* Skip if no TLB found */
495 rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */
504 * Create a TLB for the new location of CCSR. Register R8 is reserved
505 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
507 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
508 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
509 lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
510 ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
511 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
512 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
513 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
514 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
515 #ifdef CONFIG_ENABLE_36BIT_PHYS
516 lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
517 ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
529 * Create a TLB for the current location of CCSR. Register R9 is reserved
530 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
533 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
534 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
535 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
536 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
537 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h
538 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l
539 #ifdef CONFIG_ENABLE_36BIT_PHYS
540 li r7, 0 /* The default CCSR address is always a 32-bit number */
544 /* MAS1 is the same as above */
552 * We have a TLB for what we think is the current (old) CCSR. Let's
553 * verify that, otherwise we won't be able to move it.
554 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
555 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
558 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
559 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
560 #ifdef CONFIG_FSL_CORENET
561 lwz r1, 4(r9) /* CCSRBARL */
563 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
570 * If the value we read from CCSRBARL is not what we expect, then
571 * enter an infinite loop. This will at least allow a debugger to
572 * halt execution and examine TLBs, etc. There's no point in going
576 bne infinite_debug_loop
578 #ifdef CONFIG_FSL_CORENET
580 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
581 #define LAW_EN 0x80000000
582 #define LAW_SIZE_4K 0xb
583 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
584 #define CCSRAR_C 0x80000000 /* Commit */
588 * On CoreNet systems, we create the temporary LAW using a special LAW
589 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
591 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
592 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
593 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
594 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
595 lis r2, CCSRBAR_LAWAR@h
596 ori r2, r2, CCSRBAR_LAWAR@l
598 stw r0, 0xc00(r9) /* LAWBARH0 */
599 stw r1, 0xc04(r9) /* LAWBARL0 */
601 stw r2, 0xc08(r9) /* LAWAR0 */
604 * Read back from LAWAR to ensure the update is complete. e500mc
605 * cores also require an isync.
607 lwz r0, 0xc08(r9) /* LAWAR0 */
611 * Read the current CCSRBARH and CCSRBARL using load word instructions.
612 * Follow this with an isync instruction. This forces any outstanding
613 * accesses to configuration space to completion.
616 lwz r0, 0(r9) /* CCSRBARH */
617 lwz r0, 4(r9) /* CCSRBARL */
621 * Write the new values for CCSRBARH and CCSRBARL to their old
622 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
623 * has a new value written it loads a CCSRBARH shadow register. When
624 * the CCSRBARL is written, the CCSRBARH shadow register contents
625 * along with the CCSRBARL value are loaded into the CCSRBARH and
626 * CCSRBARL registers, respectively. Follow this with a sync
630 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
631 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
632 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
633 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
635 ori r2, r2, CCSRAR_C@l
637 stw r0, 0(r9) /* Write to CCSRBARH */
638 sync /* Make sure we write to CCSRBARH first */
639 stw r1, 4(r9) /* Write to CCSRBARL */
643 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
644 * Follow this with a sync instruction.
649 /* Delete the temporary LAW */
658 #else /* #ifdef CONFIG_FSL_CORENET */
662 * Read the current value of CCSRBAR using a load word instruction
663 * followed by an isync. This forces all accesses to configuration
670 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
671 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
672 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
674 /* Write the new value to CCSRBAR. */
675 lis r0, CCSRBAR_PHYS_RS12@h
676 ori r0, r0, CCSRBAR_PHYS_RS12@l
681 * The manual says to perform a load of an address that does not
682 * access configuration space or the on-chip SRAM using an existing TLB,
683 * but that doesn't appear to be necessary. We will do the isync,
689 * Read the contents of CCSRBAR from its new location, followed by
695 #endif /* #ifdef CONFIG_FSL_CORENET */
697 /* Delete the temporary TLBs */
699 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
700 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
702 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
703 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
711 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
712 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
713 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
714 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
720 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
722 create_init_ram_area:
723 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
724 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
726 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
727 /* create a temp mapping in AS=1 to the 4M boot window */
728 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
729 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
731 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
732 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
734 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
735 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
736 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
737 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
738 /* create a temp mapping in AS = 1 for Flash mapping
739 * created by PBL for ISBC code
741 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
742 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
744 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
745 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
747 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
748 (MAS3_SX|MAS3_SW|MAS3_SR))@h
749 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
750 (MAS3_SX|MAS3_SW|MAS3_SR))@l
753 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
754 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
756 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
757 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
759 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
760 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
762 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
763 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
774 /* create a temp mapping in AS=1 to the stack */
775 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
776 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
778 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
779 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
781 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
782 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
784 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
785 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
786 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
787 (MAS3_SX|MAS3_SW|MAS3_SR))@h
788 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
789 (MAS3_SX|MAS3_SW|MAS3_SR))@l
790 li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
793 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
794 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
805 lis r6,MSR_IS|MSR_DS|MSR_DE@h
806 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
808 ori r7,r7,switch_as@l
815 /* L1 DCache is used for initial RAM */
817 /* Allocate Initial RAM in data cache.
819 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
820 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
823 /* cache size * 1024 / (2 * L1 line size) */
824 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
830 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
833 /* Jump out the last 4K page and continue to 'normal' start */
834 #ifdef CONFIG_SYS_RAMBOOT
837 /* Calculate absolute address in FLASH and jump there */
838 /*--------------------------------------------------------------*/
839 lis r3,CONFIG_SYS_MONITOR_BASE@h
840 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
841 addi r3,r3,_start_cont - _start + _START_OFFSET
849 .long 0x27051956 /* U-BOOT Magic Number */
850 .globl version_string
852 .ascii U_BOOT_VERSION_STRING, "\0"
857 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
858 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
859 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
861 stw r0,0(r3) /* Terminate Back Chain */
862 stw r0,+4(r3) /* NULL return address. */
863 mr r1,r3 /* Transfer to SP(r1) */
868 /* switch back to AS = 0 */
869 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
870 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
878 /* NOTREACHED - board_init_f() does not return */
880 #ifndef CONFIG_NAND_SPL
881 . = EXC_OFF_SYS_RESET
882 .globl _start_of_vectors
885 /* Critical input. */
886 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
889 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
891 /* Data Storage exception. */
892 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
894 /* Instruction Storage exception. */
895 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
897 /* External Interrupt exception. */
898 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
900 /* Alignment exception. */
903 EXCEPTION_PROLOG(SRR0, SRR1)
908 addi r3,r1,STACK_FRAME_OVERHEAD
909 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
911 /* Program check exception */
914 EXCEPTION_PROLOG(SRR0, SRR1)
915 addi r3,r1,STACK_FRAME_OVERHEAD
916 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
919 /* No FPU on MPC85xx. This exception is not supposed to happen.
921 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
925 * r0 - SYSCALL number
929 addis r11,r0,0 /* get functions table addr */
930 ori r11,r11,0 /* Note: this code is patched in trap_init */
931 addis r12,r0,0 /* get number of functions */
937 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
941 li r20,0xd00-4 /* Get stack pointer */
943 subi r12,r12,12 /* Adjust stack pointer */
944 li r0,0xc00+_end_back-SystemCall
945 cmplw 0,r0,r12 /* Check stack overflow */
956 li r12,0xc00+_back-SystemCall
964 mfmsr r11 /* Disable interrupts */
968 SYNC /* Some chip revs need this... */
972 li r12,0xd00-4 /* restore regs */
982 addi r12,r12,12 /* Adjust stack pointer */
990 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
991 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
992 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
994 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
995 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
997 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
999 .globl _end_of_vectors
1003 . = . + (0x100 - ( . & 0xff )) /* align for debug */
1006 * This code finishes saving the registers to the exception frame
1007 * and jumps to the appropriate handler for the exception.
1008 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1010 .globl transfer_to_handler
1011 transfer_to_handler:
1022 andi. r24,r23,0x3f00 /* get vector offset */
1026 mtspr SPRG2,r22 /* r1 is now kernel sp */
1028 lwz r24,0(r23) /* virtual address of handler */
1029 lwz r23,4(r23) /* where to go when done */
1034 rfi /* jump to handler, enable MMU */
1037 mfmsr r28 /* Disable interrupts */
1041 SYNC /* Some chip revs need this... */
1056 lwz r2,_NIP(r1) /* Restore environment */
1067 mfmsr r28 /* Disable interrupts */
1071 SYNC /* Some chip revs need this... */
1086 lwz r2,_NIP(r1) /* Restore environment */
1097 mfmsr r28 /* Disable interrupts */
1101 SYNC /* Some chip revs need this... */
1116 lwz r2,_NIP(r1) /* Restore environment */
1118 mtspr SPRN_MCSRR0,r2
1119 mtspr SPRN_MCSRR1,r0
1130 .globl invalidate_icache
1133 ori r0,r0,L1CSR1_ICFI
1138 blr /* entire I cache */
1140 .globl invalidate_dcache
1143 ori r0,r0,L1CSR0_DCFI
1150 .globl icache_enable
1153 bl invalidate_icache
1163 .globl icache_disable
1167 ori r3,r3,L1CSR1_ICE
1173 .globl icache_status
1176 andi. r3,r3,L1CSR1_ICE
1179 .globl dcache_enable
1182 bl invalidate_dcache
1194 .globl dcache_disable
1198 ori r4,r4,L1CSR0_DCE
1204 .globl dcache_status
1207 andi. r3,r3,L1CSR0_DCE
1230 /*------------------------------------------------------------------------------- */
1232 /* Description: Input 8 bits */
1233 /*------------------------------------------------------------------------------- */
1239 /*------------------------------------------------------------------------------- */
1240 /* Function: out8 */
1241 /* Description: Output 8 bits */
1242 /*------------------------------------------------------------------------------- */
1249 /*------------------------------------------------------------------------------- */
1250 /* Function: out16 */
1251 /* Description: Output 16 bits */
1252 /*------------------------------------------------------------------------------- */
1259 /*------------------------------------------------------------------------------- */
1260 /* Function: out16r */
1261 /* Description: Byte reverse and output 16 bits */
1262 /*------------------------------------------------------------------------------- */
1269 /*------------------------------------------------------------------------------- */
1270 /* Function: out32 */
1271 /* Description: Output 32 bits */
1272 /*------------------------------------------------------------------------------- */
1279 /*------------------------------------------------------------------------------- */
1280 /* Function: out32r */
1281 /* Description: Byte reverse and output 32 bits */
1282 /*------------------------------------------------------------------------------- */
1289 /*------------------------------------------------------------------------------- */
1290 /* Function: in16 */
1291 /* Description: Input 16 bits */
1292 /*------------------------------------------------------------------------------- */
1298 /*------------------------------------------------------------------------------- */
1299 /* Function: in16r */
1300 /* Description: Input 16 bits and byte reverse */
1301 /*------------------------------------------------------------------------------- */
1307 /*------------------------------------------------------------------------------- */
1308 /* Function: in32 */
1309 /* Description: Input 32 bits */
1310 /*------------------------------------------------------------------------------- */
1316 /*------------------------------------------------------------------------------- */
1317 /* Function: in32r */
1318 /* Description: Input 32 bits and byte reverse */
1319 /*------------------------------------------------------------------------------- */
1324 #endif /* !CONFIG_NAND_SPL */
1326 /*------------------------------------------------------------------------------*/
1329 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1337 #ifdef CONFIG_ENABLE_36BIT_PHYS
1341 #ifdef CONFIG_SYS_BOOK3E_HV
1351 * void relocate_code (addr_sp, gd, addr_moni)
1353 * This "function" does not return, instead it continues in RAM
1354 * after relocating the monitor code.
1358 * r5 = length in bytes
1359 * r6 = cachelinesize
1361 .globl relocate_code
1363 mr r1,r3 /* Set new stack pointer */
1364 mr r9,r4 /* Save copy of Init Data pointer */
1365 mr r10,r5 /* Save copy of Destination Address */
1368 mr r3,r5 /* Destination Address */
1369 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1370 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1371 lwz r5,GOT(__init_end)
1373 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1378 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1384 /* First our own GOT */
1386 /* the the one used by the C code */
1396 beq cr1,4f /* In place copy is not necessary */
1397 beq 7f /* Protect against 0 count */
1416 * Now flush the cache: note that we must start from a cache aligned
1417 * address. Otherwise we might miss one cache line.
1421 beq 7f /* Always flush prefetch queue in any case */
1429 sync /* Wait for all dcbst to complete on bus */
1435 7: sync /* Wait for all icbi to complete on bus */
1439 * We are done. Do not return, instead branch to second part of board
1440 * initialization, now running from RAM.
1443 addi r0,r10,in_ram - _start + _START_OFFSET
1446 * As IVPR is going to point RAM address,
1447 * Make sure IVOR15 has valid opcode to support debugger
1452 * Re-point the IVPR at RAM
1457 blr /* NEVER RETURNS! */
1462 * Relocation Function, r12 point to got2+0x8000
1464 * Adjust got2 pointers, no need to check for 0, this code
1465 * already puts a few entries in the table.
1467 li r0,__got2_entries@sectoff@l
1468 la r3,GOT(_GOT2_TABLE_)
1469 lwz r11,GOT(_GOT2_TABLE_)
1481 * Now adjust the fixups and the pointers to the fixups
1482 * in case we need to move ourselves again.
1484 li r0,__fixup_entries@sectoff@l
1485 lwz r3,GOT(_FIXUP_TABLE_)
1501 * Now clear BSS segment
1503 lwz r3,GOT(__bss_start)
1504 lwz r4,GOT(__bss_end__)
1517 mr r3,r9 /* Init Data pointer */
1518 mr r4,r10 /* Destination Address */
1521 #ifndef CONFIG_NAND_SPL
1523 * Copy exception vector code to low memory
1526 * r7: source address, r8: end address, r9: target address
1530 mflr r4 /* save link register */
1532 lwz r7,GOT(_start_of_vectors)
1533 lwz r8,GOT(_end_of_vectors)
1535 li r9,0x100 /* reset vector always at 0x100 */
1538 bgelr /* return if r7>=r8 - just in case */
1548 * relocate `hdlr' and `int_return' entries
1550 li r7,.L_CriticalInput - _start + _START_OFFSET
1552 li r7,.L_MachineCheck - _start + _START_OFFSET
1554 li r7,.L_DataStorage - _start + _START_OFFSET
1556 li r7,.L_InstStorage - _start + _START_OFFSET
1558 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1560 li r7,.L_Alignment - _start + _START_OFFSET
1562 li r7,.L_ProgramCheck - _start + _START_OFFSET
1564 li r7,.L_FPUnavailable - _start + _START_OFFSET
1566 li r7,.L_Decrementer - _start + _START_OFFSET
1568 li r7,.L_IntervalTimer - _start + _START_OFFSET
1569 li r8,_end_of_vectors - _start + _START_OFFSET
1572 addi r7,r7,0x100 /* next exception vector */
1576 /* Update IVORs as per relocated vector table address */
1578 mtspr IVOR0,r7 /* 0: Critical input */
1580 mtspr IVOR1,r7 /* 1: Machine check */
1582 mtspr IVOR2,r7 /* 2: Data storage */
1584 mtspr IVOR3,r7 /* 3: Instruction storage */
1586 mtspr IVOR4,r7 /* 4: External interrupt */
1588 mtspr IVOR5,r7 /* 5: Alignment */
1590 mtspr IVOR6,r7 /* 6: Program check */
1592 mtspr IVOR7,r7 /* 7: floating point unavailable */
1594 mtspr IVOR8,r7 /* 8: System call */
1595 /* 9: Auxiliary processor unavailable(unsupported) */
1597 mtspr IVOR10,r7 /* 10: Decrementer */
1599 mtspr IVOR11,r7 /* 11: Interval timer */
1601 mtspr IVOR12,r7 /* 12: Watchdog timer */
1603 mtspr IVOR13,r7 /* 13: Data TLB error */
1605 mtspr IVOR14,r7 /* 14: Instruction TLB error */
1607 mtspr IVOR15,r7 /* 15: Debug */
1612 mtlr r4 /* restore link register */
1615 .globl unlock_ram_in_cache
1616 unlock_ram_in_cache:
1617 /* invalidate the INIT_RAM section */
1618 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1619 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1622 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1625 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1629 /* Invalidate the TLB entries for the cache */
1630 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1631 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1644 mfspr r3,SPRN_L1CFG0
1646 rlwinm r5,r3,9,3 /* Extract cache block size */
1647 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1648 * are currently defined.
1651 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1652 * log2(number of ways)
1654 slw r5,r4,r5 /* r5 = cache block size */
1656 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1657 mulli r7,r7,13 /* An 8-way cache will require 13
1662 /* save off HID0 and set DCFA */
1664 ori r9,r8,HID0_DCFA@l
1671 1: lwz r3,0(r4) /* Load... */
1679 1: dcbf 0,r4 /* ...and flush. */
1692 #include "fixed_ivor.S"
1694 #endif /* !CONFIG_NAND_SPL */