2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
10 * The processor starts at 0xfffffffc and the code is first executed in the
11 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
15 #include <asm-offsets.h>
20 #include <ppc_asm.tmpl>
23 #include <asm/cache.h>
27 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
29 #define LAW_EN 0x80000000
31 #if defined(CONFIG_NAND_SPL) || \
32 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
36 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
37 !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
42 * Set up GOT: Global Offset Table
44 * Use r12 to access the GOT
47 GOT_ENTRY(_GOT2_TABLE_)
48 GOT_ENTRY(_FIXUP_TABLE_)
52 GOT_ENTRY(_start_of_vectors)
53 GOT_ENTRY(_end_of_vectors)
54 GOT_ENTRY(transfer_to_handler)
59 GOT_ENTRY(__bss_start)
63 * e500 Startup -- after reset only the last 4KB of the effective
64 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
65 * section is located at THIS LAST page and basically does three
66 * things: clear some registers, set up exception tables and
67 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
68 * continue the boot procedure.
70 * Once the boot rom is mapped by TLB entries we can proceed
71 * with normal startup.
79 /* Enable debug exception */
84 * If we got an ePAPR device tree pointer passed in as r3, we need that
85 * later in cpu_init_early_f(). Save it to a safe register before we
86 * clobber it so that we can fetch it from there later.
90 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
93 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
97 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
98 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
103 /* Not a supported revision affected by erratum */
107 1: li r27,1 /* Remember for later that we have the erratum */
108 /* Erratum says set bits 55:60 to 001001 */
118 #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
121 mfspr r3, SPRN_HDBCR0
123 mtspr SPRN_HDBCR0, r3
127 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
128 !defined(CONFIG_E6500)
129 /* ISBC uses L2 as stack.
130 * Disable L2 cache here so that u-boot can enable it later
131 * as part of it's normal flow
134 /* Check if L2 is enabled */
135 mfspr r3, SPRN_L2CSR0
137 ori r2, r2, L2CSR0_L2E@l
141 mfspr r3, SPRN_L2CSR0
143 lis r2,(L2CSR0_L2FL)@h
144 ori r2, r2, (L2CSR0_L2FL)@l
151 mfspr r3, SPRN_L2CSR0
155 mfspr r3, SPRN_L2CSR0
157 ori r2, r2, L2CSR0_L2E@l
167 /* clear registers/arrays not reset by hardware */
171 mtspr L1CSR0,r0 /* invalidate d-cache */
172 mtspr L1CSR1,r0 /* invalidate i-cache */
175 mtspr DBSR,r1 /* Clear all valid bits */
178 .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
179 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
180 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
182 lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
183 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
185 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
186 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
188 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
189 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
191 lis \scratch, \phy_high@h
192 ori \scratch, \scratch, \phy_high@l
200 .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
201 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
202 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
204 lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
205 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
207 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
208 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
210 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
211 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
213 lis \scratch, \phy_high@h
214 ori \scratch, \scratch, \phy_high@l
222 .macro delete_tlb1_entry esel scratch
223 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
224 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
234 .macro delete_tlb0_entry esel epn wimg scratch
235 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
236 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
240 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
241 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
249 /* Interrupt vectors do not fit in minimal SPL. */
250 #if !defined(MINIMAL_SPL)
251 /* Setup interrupt vectors */
252 lis r1,CONFIG_SYS_MONITOR_BASE@h
255 li r4,CriticalInput@l
256 mtspr IVOR0,r4 /* 0: Critical input */
258 mtspr IVOR1,r4 /* 1: Machine check */
260 mtspr IVOR2,r4 /* 2: Data storage */
262 mtspr IVOR3,r4 /* 3: Instruction storage */
264 mtspr IVOR4,r4 /* 4: External interrupt */
266 mtspr IVOR5,r4 /* 5: Alignment */
268 mtspr IVOR6,r4 /* 6: Program check */
269 li r4,FPUnavailable@l
270 mtspr IVOR7,r4 /* 7: floating point unavailable */
272 mtspr IVOR8,r4 /* 8: System call */
273 /* 9: Auxiliary processor unavailable(unsupported) */
275 mtspr IVOR10,r4 /* 10: Decrementer */
276 li r4,IntervalTimer@l
277 mtspr IVOR11,r4 /* 11: Interval timer */
278 li r4,WatchdogTimer@l
279 mtspr IVOR12,r4 /* 12: Watchdog timer */
281 mtspr IVOR13,r4 /* 13: Data TLB error */
282 li r4,InstructionTLBError@l
283 mtspr IVOR14,r4 /* 14: Instruction TLB error */
284 li r4,DebugBreakpoint@l
285 mtspr IVOR15,r4 /* 15: Debug */
288 /* Clear and set up some registers. */
291 mtspr DEC,r0 /* prevent dec exceptions */
292 mttbl r0 /* prevent fit & wdt exceptions */
294 mtspr TSR,r1 /* clear all timer exception status */
295 mtspr TCR,r0 /* disable all */
296 mtspr ESR,r0 /* clear exception syndrome register */
297 mtspr MCSR,r0 /* machine check syndrome register */
298 mtxer r0 /* clear integer exception register */
300 #ifdef CONFIG_SYS_BOOK3E_HV
301 mtspr MAS8,r0 /* make sure MAS8 is clear */
304 /* Enable Time Base and Select Time Base Clock */
305 lis r0,HID0_EMCP@h /* Enable machine check */
306 #if defined(CONFIG_ENABLE_36BIT_PHYS)
307 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
309 #ifndef CONFIG_E500MC
310 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
314 #if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500)
315 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
318 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
320 /* Set MBDD bit also */
321 ori r0, r0, HID1_MBDD@l
326 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
332 /* Enable Branch Prediction */
333 #if defined(CONFIG_BTB)
334 lis r0,BUCSR_ENABLE@h
335 ori r0,r0,BUCSR_ENABLE@l
339 #if defined(CONFIG_SYS_INIT_DBCR)
342 mtspr DBSR,r1 /* Clear all status bits */
343 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
344 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
348 #ifdef CONFIG_MPC8569
349 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
350 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
352 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
353 * use address space which is more than 12bits, and it must be done in
354 * the 4K boot page. So we set this bit here.
357 /* create a temp mapping TLB0[0] for LBCR */
358 create_tlb0_entry 0, \
359 0, BOOKE_PAGESZ_4K, \
360 CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
361 CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
364 /* Set LBCR register */
365 lis r4,CONFIG_SYS_LBCR_ADDR@h
366 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
368 lis r5,CONFIG_SYS_LBC_LBCR@h
369 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
373 /* invalidate this temp TLB */
374 lis r4,CONFIG_SYS_LBC_ADDR@h
375 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
379 #endif /* CONFIG_MPC8569 */
382 * Search for the TLB that covers the code we're executing, and shrink it
383 * so that it covers only this 4K page. That will ensure that any other
384 * TLB we create won't interfere with it. We assume that the TLB exists,
385 * which is why we don't check the Valid bit of MAS1. We also assume
388 * This is necessary, for example, when booting from the on-chip ROM,
389 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
391 bl nexti /* Find our address */
392 nexti: mflr r1 /* R1 = our PC */
394 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
397 tlbsx 0, r1 /* This must succeed */
399 mfspr r14, MAS0 /* Save ESEL for later */
400 rlwinm r14, r14, 16, 0xfff
402 /* Set the size of the TLB to 4KB */
405 andc r3, r3, r2 /* Clear the TSIZE bits */
406 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
407 oris r3, r3, MAS1_IPROT@h
411 * Set the base address of the TLB to our PC. We assume that
412 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
415 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
417 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
422 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
425 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
426 rlwinm r2, r2, 0, ~MAS2_I
430 mtspr MAS2, r2 /* Set the EPN to our PC base address */
435 mtspr MAS3, r2 /* Set the RPN to our PC base address */
442 * Clear out any other TLB entries that may exist, to avoid conflicts.
443 * Our TLB entry is in r14.
445 li r0, TLBIVAX_ALL | TLBIVAX_TLB0
449 mfspr r4, SPRN_TLB1CFG
450 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
455 rlwinm r5, r3, 16, MAS0_ESEL_MSK
457 beq 2f /* skip the entry we're executing from */
459 oris r5, r5, MAS0_TLBSEL(1)@h
470 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
471 !defined(CONFIG_SECURE_BOOT)
473 * TLB entry for debuggging in AS1
474 * Create temporary TLB entry in AS0 to handle debug exception
475 * As on debug exception MSR is cleared i.e. Address space is changed
476 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
482 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
483 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
484 * and this window is outside of 4K boot window.
486 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
487 0, BOOKE_PAGESZ_4M, \
488 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
489 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
494 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
495 * because "nexti" will resize TLB to 4K
497 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
498 0, BOOKE_PAGESZ_256K, \
499 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
500 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
506 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
507 * location is not where we want it. This typically happens on a 36-bit
508 * system, where we want to move CCSR to near the top of 36-bit address space.
510 * To move CCSR, we create two temporary TLBs, one for the old location, and
511 * another for the new location. On CoreNet systems, we also need to create
512 * a special, temporary LAW.
514 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
515 * long-term TLBs, so we use TLB0 here.
517 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
519 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
520 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
525 * Create a TLB for the new location of CCSR. Register R8 is reserved
526 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
528 lis r8, CONFIG_SYS_CCSRBAR@h
529 ori r8, r8, CONFIG_SYS_CCSRBAR@l
530 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
531 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
532 create_tlb0_entry 0, \
533 0, BOOKE_PAGESZ_4K, \
534 CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
535 CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
536 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
538 * Create a TLB for the current location of CCSR. Register R9 is reserved
539 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
542 create_tlb0_entry 1, \
543 0, BOOKE_PAGESZ_4K, \
544 CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
545 CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
546 0, r3 /* The default CCSR address is always a 32-bit number */
550 * We have a TLB for what we think is the current (old) CCSR. Let's
551 * verify that, otherwise we won't be able to move it.
552 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
553 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
556 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
557 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
558 #ifdef CONFIG_FSL_CORENET
559 lwz r1, 4(r9) /* CCSRBARL */
561 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
568 * If the value we read from CCSRBARL is not what we expect, then
569 * enter an infinite loop. This will at least allow a debugger to
570 * halt execution and examine TLBs, etc. There's no point in going
574 bne infinite_debug_loop
576 #ifdef CONFIG_FSL_CORENET
578 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
579 #define LAW_SIZE_4K 0xb
580 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
581 #define CCSRAR_C 0x80000000 /* Commit */
585 * On CoreNet systems, we create the temporary LAW using a special LAW
586 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
588 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
589 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
590 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
591 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
592 lis r2, CCSRBAR_LAWAR@h
593 ori r2, r2, CCSRBAR_LAWAR@l
595 stw r0, 0xc00(r9) /* LAWBARH0 */
596 stw r1, 0xc04(r9) /* LAWBARL0 */
598 stw r2, 0xc08(r9) /* LAWAR0 */
601 * Read back from LAWAR to ensure the update is complete. e500mc
602 * cores also require an isync.
604 lwz r0, 0xc08(r9) /* LAWAR0 */
608 * Read the current CCSRBARH and CCSRBARL using load word instructions.
609 * Follow this with an isync instruction. This forces any outstanding
610 * accesses to configuration space to completion.
613 lwz r0, 0(r9) /* CCSRBARH */
614 lwz r0, 4(r9) /* CCSRBARL */
618 * Write the new values for CCSRBARH and CCSRBARL to their old
619 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
620 * has a new value written it loads a CCSRBARH shadow register. When
621 * the CCSRBARL is written, the CCSRBARH shadow register contents
622 * along with the CCSRBARL value are loaded into the CCSRBARH and
623 * CCSRBARL registers, respectively. Follow this with a sync
627 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
628 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
629 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
630 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
632 ori r2, r2, CCSRAR_C@l
634 stw r0, 0(r9) /* Write to CCSRBARH */
635 sync /* Make sure we write to CCSRBARH first */
636 stw r1, 4(r9) /* Write to CCSRBARL */
640 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
641 * Follow this with a sync instruction.
646 /* Delete the temporary LAW */
655 #else /* #ifdef CONFIG_FSL_CORENET */
659 * Read the current value of CCSRBAR using a load word instruction
660 * followed by an isync. This forces all accesses to configuration
667 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
668 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
669 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
671 /* Write the new value to CCSRBAR. */
672 lis r0, CCSRBAR_PHYS_RS12@h
673 ori r0, r0, CCSRBAR_PHYS_RS12@l
678 * The manual says to perform a load of an address that does not
679 * access configuration space or the on-chip SRAM using an existing TLB,
680 * but that doesn't appear to be necessary. We will do the isync,
686 * Read the contents of CCSRBAR from its new location, followed by
692 #endif /* #ifdef CONFIG_FSL_CORENET */
694 /* Delete the temporary TLBs */
696 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
697 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
699 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
701 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
704 * Create a TLB for the MMR location of CCSR
705 * to access L2CSR0 register
707 create_tlb0_entry 0, \
708 0, BOOKE_PAGESZ_4K, \
709 CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
710 CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
711 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
713 enable_l2_cluster_l2:
714 /* enable L2 cache */
715 lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
716 ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
717 li r4, 33 /* stash id */
719 lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
720 ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
722 stw r4, 0(r3) /* invalidate L2 */
729 lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
730 ori r4, r4, (L2CSR0_L2REP_MODE)@l
732 stw r4, 0(r3) /* enable L2 */
734 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
738 * Enable the L1. On e6500, this has to be done
739 * after the L2 is up.
742 #ifdef CONFIG_SYS_CACHE_STASHING
743 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
748 /* Enable/invalidate the I-Cache */
749 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
750 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
757 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
758 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
763 andi. r1,r3,L1CSR1_ICE@l
766 /* Enable/invalidate the D-Cache */
767 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
768 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
775 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
776 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
781 andi. r1,r3,L1CSR0_DCE@l
783 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
784 #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
785 #define LAW_SIZE_1M 0x13
786 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
792 * Create a TLB entry for CCSR
794 * We're executing out of TLB1 entry in r14, and that's the only
795 * TLB entry that exists. To allocate some TLB entries for our
796 * own use, flip a bit high enough that we won't flip it again
801 lis r0, MAS0_TLBSEL(1)@h
802 rlwimi r0, r8, 16, MAS0_ESEL_MSK
803 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
804 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
805 lis r7, CONFIG_SYS_CCSRBAR@h
806 ori r7, r7, CONFIG_SYS_CCSRBAR@l
807 ori r2, r7, MAS2_I|MAS2_G
808 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
809 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
810 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
811 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
822 /* Map DCSR temporarily to physical address zero */
824 lis r3, DCSRBAR_LAWAR@h
825 ori r3, r3, DCSRBAR_LAWAR@l
827 stw r0, 0xc00(r7) /* LAWBARH0 */
828 stw r0, 0xc04(r7) /* LAWBARL0 */
830 stw r3, 0xc08(r7) /* LAWAR0 */
832 /* Read back from LAWAR to ensure the update is complete. */
833 lwz r3, 0xc08(r7) /* LAWAR0 */
836 /* Create a TLB entry for DCSR at zero */
839 lis r0, MAS0_TLBSEL(1)@h
840 rlwimi r0, r9, 16, MAS0_ESEL_MSK
841 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
842 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
843 li r6, 0 /* DCSR effective address */
844 ori r2, r6, MAS2_I|MAS2_G
845 li r3, MAS3_SW|MAS3_SR
857 /* enable the timebase */
858 #define CTBENR 0xe2084
860 addis r4, r7, CTBENR@ha
866 .macro erratum_set_ccsr offset value
867 addis r3, r7, \offset@ha
869 addi r3, r3, \offset@l
874 .macro erratum_set_dcsr offset value
875 addis r3, r6, \offset@ha
877 addi r3, r3, \offset@l
882 erratum_set_dcsr 0xb0e08 0xe0201800
883 erratum_set_dcsr 0xb0e18 0xe0201800
884 erratum_set_dcsr 0xb0e38 0xe0400000
885 erratum_set_dcsr 0xb0008 0x00900000
886 erratum_set_dcsr 0xb0e40 0xe00a0000
887 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
888 #ifdef CONFIG_RAMBOOT_PBL
889 erratum_set_ccsr 0x10f00 0x495e5000
891 erratum_set_ccsr 0x10f00 0x415e5000
893 erratum_set_ccsr 0x11f00 0x415e5000
895 /* Make temp mapping uncacheable again, if it was initially */
900 rlwimi r4, r15, 0, MAS2_I
901 rlwimi r4, r15, 0, MAS2_G
908 /* Clear the cache */
909 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
910 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
920 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
921 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
931 /* Remove temporary mappings */
932 lis r0, MAS0_TLBSEL(1)@h
933 rlwimi r0, r9, 16, MAS0_ESEL_MSK
943 stw r3, 0xc08(r7) /* LAWAR0 */
947 lis r0, MAS0_TLBSEL(1)@h
948 rlwimi r0, r8, 16, MAS0_ESEL_MSK
959 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
961 /* Lock two cache lines into I-Cache */
963 mfspr r11, SPRN_L1CSR1
964 rlwinm r11, r11, 0, ~L1CSR1_ICUL
967 mtspr SPRN_L1CSR1, r11
978 mfspr r11, SPRN_L1CSR1
979 3: andi. r11, r11, L1CSR1_ICUL
986 mfspr r11, SPRN_L1CSR1
987 3: andi. r11, r11, L1CSR1_ICUL
992 /* Inside a locked cacheline, wait a while, write, then wait a while */
996 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
997 4: mfspr r5, SPRN_TBRL
1004 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
1005 4: mfspr r5, SPRN_TBRL
1012 * Fill out the rest of this cache line and the next with nops,
1013 * to ensure that nothing outside the locked area will be
1014 * fetched due to a branch.
1021 mfspr r11, SPRN_L1CSR1
1022 rlwinm r11, r11, 0, ~L1CSR1_ICUL
1025 mtspr SPRN_L1CSR1, r11
1034 create_init_ram_area:
1035 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
1036 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
1039 /* create a temp mapping in AS=1 to the 4M boot window */
1040 create_tlb1_entry 15, \
1041 1, BOOKE_PAGESZ_4M, \
1042 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
1043 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1046 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
1047 /* create a temp mapping in AS = 1 for Flash mapping
1048 * created by PBL for ISBC code
1050 create_tlb1_entry 15, \
1051 1, BOOKE_PAGESZ_1M, \
1052 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1053 CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1057 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
1058 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
1060 create_tlb1_entry 15, \
1061 1, BOOKE_PAGESZ_1M, \
1062 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1063 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1067 /* create a temp mapping in AS=1 to the stack */
1068 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
1069 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
1070 create_tlb1_entry 14, \
1071 1, BOOKE_PAGESZ_16K, \
1072 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1073 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
1074 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
1077 create_tlb1_entry 14, \
1078 1, BOOKE_PAGESZ_16K, \
1079 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1080 CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
1084 lis r6,MSR_IS|MSR_DS|MSR_DE@h
1085 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
1087 ori r7,r7,switch_as@l
1094 /* L1 DCache is used for initial RAM */
1096 /* Allocate Initial RAM in data cache.
1098 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1099 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1102 /* cache size * 1024 / (2 * L1 line size) */
1103 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
1109 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1112 /* Jump out the last 4K page and continue to 'normal' start */
1113 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
1114 /* We assume that we're already running at the address we're linked at */
1117 /* Calculate absolute address in FLASH and jump there */
1118 /*--------------------------------------------------------------*/
1119 lis r3,CONFIG_SYS_MONITOR_BASE@h
1120 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
1121 addi r3,r3,_start_cont - _start
1129 .long 0x27051956 /* U-BOOT Magic Number */
1130 .globl version_string
1132 .ascii U_BOOT_VERSION_STRING, "\0"
1137 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
1138 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1139 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
1141 stw r0,0(r3) /* Terminate Back Chain */
1142 stw r0,+4(r3) /* NULL return address. */
1143 mr r1,r3 /* Transfer to SP(r1) */
1147 /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */
1152 /* switch back to AS = 0 */
1153 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1154 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1158 bl cpu_init_f /* return boot_flag for calling board_init_f */
1162 /* NOTREACHED - board_init_f() does not return */
1165 .globl _start_of_vectors
1168 /* Critical input. */
1169 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
1172 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
1174 /* Data Storage exception. */
1175 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
1177 /* Instruction Storage exception. */
1178 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
1180 /* External Interrupt exception. */
1181 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
1183 /* Alignment exception. */
1185 EXCEPTION_PROLOG(SRR0, SRR1)
1190 addi r3,r1,STACK_FRAME_OVERHEAD
1191 EXC_XFER_TEMPLATE(0x600, Alignment, AlignmentException,
1192 MSR_KERNEL, COPY_EE)
1194 /* Program check exception */
1196 EXCEPTION_PROLOG(SRR0, SRR1)
1197 addi r3,r1,STACK_FRAME_OVERHEAD
1198 EXC_XFER_TEMPLATE(0x700, ProgramCheck, ProgramCheckException,
1199 MSR_KERNEL, COPY_EE)
1201 /* No FPU on MPC85xx. This exception is not supposed to happen.
1203 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
1204 STD_EXCEPTION(0x0900, SystemCall, UnknownException)
1205 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
1206 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
1207 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
1209 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
1210 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
1212 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
1214 .globl _end_of_vectors
1218 . = . + (0x100 - ( . & 0xff )) /* align for debug */
1221 * This code finishes saving the registers to the exception frame
1222 * and jumps to the appropriate handler for the exception.
1223 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1224 * r23 is the address of the handler.
1226 .globl transfer_to_handler
1227 transfer_to_handler:
1235 mtspr SPRG2,r22 /* r1 is now kernel sp */
1237 mtctr r23 /* virtual address of handler */
1242 mfmsr r28 /* Disable interrupts */
1246 SYNC /* Some chip revs need this... */
1261 lwz r2,_NIP(r1) /* Restore environment */
1275 .globl invalidate_icache
1278 ori r0,r0,L1CSR1_ICFI
1283 blr /* entire I cache */
1285 .globl invalidate_dcache
1288 ori r0,r0,L1CSR0_DCFI
1295 .globl icache_enable
1298 bl invalidate_icache
1308 .globl icache_disable
1312 ori r3,r3,L1CSR1_ICE
1318 .globl icache_status
1321 andi. r3,r3,L1CSR1_ICE
1324 .globl dcache_enable
1327 bl invalidate_dcache
1339 .globl dcache_disable
1343 ori r4,r4,L1CSR0_DCE
1349 .globl dcache_status
1352 andi. r3,r3,L1CSR0_DCE
1365 /*------------------------------------------------------------------------------- */
1367 /* Description: Input 8 bits */
1368 /*------------------------------------------------------------------------------- */
1374 /*------------------------------------------------------------------------------- */
1375 /* Function: out8 */
1376 /* Description: Output 8 bits */
1377 /*------------------------------------------------------------------------------- */
1384 /*------------------------------------------------------------------------------- */
1385 /* Function: out16 */
1386 /* Description: Output 16 bits */
1387 /*------------------------------------------------------------------------------- */
1394 /*------------------------------------------------------------------------------- */
1395 /* Function: out16r */
1396 /* Description: Byte reverse and output 16 bits */
1397 /*------------------------------------------------------------------------------- */
1404 /*------------------------------------------------------------------------------- */
1405 /* Function: out32 */
1406 /* Description: Output 32 bits */
1407 /*------------------------------------------------------------------------------- */
1414 /*------------------------------------------------------------------------------- */
1415 /* Function: out32r */
1416 /* Description: Byte reverse and output 32 bits */
1417 /*------------------------------------------------------------------------------- */
1424 /*------------------------------------------------------------------------------- */
1425 /* Function: in16 */
1426 /* Description: Input 16 bits */
1427 /*------------------------------------------------------------------------------- */
1433 /*------------------------------------------------------------------------------- */
1434 /* Function: in16r */
1435 /* Description: Input 16 bits and byte reverse */
1436 /*------------------------------------------------------------------------------- */
1442 /*------------------------------------------------------------------------------- */
1443 /* Function: in32 */
1444 /* Description: Input 32 bits */
1445 /*------------------------------------------------------------------------------- */
1451 /*------------------------------------------------------------------------------- */
1452 /* Function: in32r */
1453 /* Description: Input 32 bits and byte reverse */
1454 /*------------------------------------------------------------------------------- */
1459 #endif /* !MINIMAL_SPL */
1461 /*------------------------------------------------------------------------------*/
1464 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1472 #ifdef CONFIG_ENABLE_36BIT_PHYS
1476 #ifdef CONFIG_SYS_BOOK3E_HV
1486 * void relocate_code (addr_sp, gd, addr_moni)
1488 * This "function" does not return, instead it continues in RAM
1489 * after relocating the monitor code.
1493 * r5 = length in bytes
1494 * r6 = cachelinesize
1496 .globl relocate_code
1498 mr r1,r3 /* Set new stack pointer */
1499 mr r9,r4 /* Save copy of Init Data pointer */
1500 mr r10,r5 /* Save copy of Destination Address */
1503 #ifndef CONFIG_SPL_SKIP_RELOCATE
1504 mr r3,r5 /* Destination Address */
1505 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1506 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1507 lwz r5,GOT(__init_end)
1509 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1514 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1520 /* First our own GOT */
1522 /* the the one used by the C code */
1532 beq cr1,4f /* In place copy is not necessary */
1533 beq 7f /* Protect against 0 count */
1552 * Now flush the cache: note that we must start from a cache aligned
1553 * address. Otherwise we might miss one cache line.
1557 beq 7f /* Always flush prefetch queue in any case */
1565 sync /* Wait for all dcbst to complete on bus */
1571 7: sync /* Wait for all icbi to complete on bus */
1575 * We are done. Do not return, instead branch to second part of board
1576 * initialization, now running from RAM.
1579 addi r0,r10,in_ram - _start
1582 * As IVPR is going to point RAM address,
1583 * Make sure IVOR15 has valid opcode to support debugger
1588 * Re-point the IVPR at RAM
1593 blr /* NEVER RETURNS! */
1599 * Relocation Function, r12 point to got2+0x8000
1601 * Adjust got2 pointers, no need to check for 0, this code
1602 * already puts a few entries in the table.
1604 li r0,__got2_entries@sectoff@l
1605 la r3,GOT(_GOT2_TABLE_)
1606 lwz r11,GOT(_GOT2_TABLE_)
1618 * Now adjust the fixups and the pointers to the fixups
1619 * in case we need to move ourselves again.
1621 li r0,__fixup_entries@sectoff@l
1622 lwz r3,GOT(_FIXUP_TABLE_)
1638 * Now clear BSS segment
1640 lwz r3,GOT(__bss_start)
1641 lwz r4,GOT(__bss_end)
1654 mr r3,r9 /* Init Data pointer */
1655 mr r4,r10 /* Destination Address */
1660 * Copy exception vector code to low memory
1663 * r7: source address, r8: end address, r9: target address
1667 /* Update IVORs as per relocation */
1670 li r4,CriticalInput@l
1671 mtspr IVOR0,r4 /* 0: Critical input */
1672 li r4,MachineCheck@l
1673 mtspr IVOR1,r4 /* 1: Machine check */
1675 mtspr IVOR2,r4 /* 2: Data storage */
1677 mtspr IVOR3,r4 /* 3: Instruction storage */
1678 li r4,ExtInterrupt@l
1679 mtspr IVOR4,r4 /* 4: External interrupt */
1681 mtspr IVOR5,r4 /* 5: Alignment */
1682 li r4,ProgramCheck@l
1683 mtspr IVOR6,r4 /* 6: Program check */
1684 li r4,FPUnavailable@l
1685 mtspr IVOR7,r4 /* 7: floating point unavailable */
1687 mtspr IVOR8,r4 /* 8: System call */
1688 /* 9: Auxiliary processor unavailable(unsupported) */
1690 mtspr IVOR10,r4 /* 10: Decrementer */
1691 li r4,IntervalTimer@l
1692 mtspr IVOR11,r4 /* 11: Interval timer */
1693 li r4,WatchdogTimer@l
1694 mtspr IVOR12,r4 /* 12: Watchdog timer */
1695 li r4,DataTLBError@l
1696 mtspr IVOR13,r4 /* 13: Data TLB error */
1697 li r4,InstructionTLBError@l
1698 mtspr IVOR14,r4 /* 14: Instruction TLB error */
1699 li r4,DebugBreakpoint@l
1700 mtspr IVOR15,r4 /* 15: Debug */
1704 .globl unlock_ram_in_cache
1705 unlock_ram_in_cache:
1706 /* invalidate the INIT_RAM section */
1707 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1708 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1711 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1715 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1719 /* Invalidate the TLB entries for the cache */
1720 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1721 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1734 mfspr r3,SPRN_L1CFG0
1736 rlwinm r5,r3,9,3 /* Extract cache block size */
1737 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1738 * are currently defined.
1741 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1742 * log2(number of ways)
1744 slw r5,r4,r5 /* r5 = cache block size */
1746 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1747 mulli r7,r7,13 /* An 8-way cache will require 13
1752 /* save off HID0 and set DCFA */
1754 ori r9,r8,HID0_DCFA@l
1761 1: lwz r3,0(r4) /* Load... */
1769 1: dcbf 0,r4 /* ...and flush. */
1778 #endif /* !MINIMAL_SPL */