2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
10 * The processor starts at 0xfffffffc and the code is first executed in the
11 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
15 #include <asm-offsets.h>
20 #include <ppc_asm.tmpl>
23 #include <asm/cache.h>
27 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
29 #if defined(CONFIG_NAND_SPL) || \
30 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
34 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
35 !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
40 * Set up GOT: Global Offset Table
42 * Use r12 to access the GOT
45 GOT_ENTRY(_GOT2_TABLE_)
46 GOT_ENTRY(_FIXUP_TABLE_)
50 GOT_ENTRY(_start_of_vectors)
51 GOT_ENTRY(_end_of_vectors)
52 GOT_ENTRY(transfer_to_handler)
57 GOT_ENTRY(__bss_start)
61 * e500 Startup -- after reset only the last 4KB of the effective
62 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
63 * section is located at THIS LAST page and basically does three
64 * things: clear some registers, set up exception tables and
65 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
66 * continue the boot procedure.
68 * Once the boot rom is mapped by TLB entries we can proceed
69 * with normal startup.
77 /* Enable debug exception */
82 * If we got an ePAPR device tree pointer passed in as r3, we need that
83 * later in cpu_init_early_f(). Save it to a safe register before we
84 * clobber it so that we can fetch it from there later.
88 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
91 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
95 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
96 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
101 /* Not a supported revision affected by erratum */
105 1: li r27,1 /* Remember for later that we have the erratum */
106 /* Erratum says set bits 55:60 to 001001 */
116 #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
119 mfspr r3, SPRN_HDBCR0
121 mtspr SPRN_HDBCR0, r3
125 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
126 !defined(CONFIG_E6500)
127 /* ISBC uses L2 as stack.
128 * Disable L2 cache here so that u-boot can enable it later
129 * as part of it's normal flow
132 /* Check if L2 is enabled */
133 mfspr r3, SPRN_L2CSR0
135 ori r2, r2, L2CSR0_L2E@l
139 mfspr r3, SPRN_L2CSR0
141 lis r2,(L2CSR0_L2FL)@h
142 ori r2, r2, (L2CSR0_L2FL)@l
149 mfspr r3, SPRN_L2CSR0
153 mfspr r3, SPRN_L2CSR0
155 ori r2, r2, L2CSR0_L2E@l
165 /* clear registers/arrays not reset by hardware */
169 mtspr L1CSR0,r0 /* invalidate d-cache */
170 mtspr L1CSR1,r0 /* invalidate i-cache */
173 mtspr DBSR,r1 /* Clear all valid bits */
176 .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
177 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
178 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
180 lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
181 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
183 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
184 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
186 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
187 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
189 lis \scratch, \phy_high@h
190 ori \scratch, \scratch, \phy_high@l
198 .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
199 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
200 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
202 lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
203 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
205 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
206 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
208 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
209 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
211 lis \scratch, \phy_high@h
212 ori \scratch, \scratch, \phy_high@l
220 .macro delete_tlb1_entry esel scratch
221 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
222 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
232 .macro delete_tlb0_entry esel epn wimg scratch
233 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
234 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
238 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
239 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
247 /* Interrupt vectors do not fit in minimal SPL. */
248 #if !defined(MINIMAL_SPL)
249 /* Setup interrupt vectors */
250 lis r1,CONFIG_SYS_MONITOR_BASE@h
253 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
254 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
256 addi r4,r3,CriticalInput - _start + _START_OFFSET
257 mtspr IVOR0,r4 /* 0: Critical input */
258 addi r4,r3,MachineCheck - _start + _START_OFFSET
259 mtspr IVOR1,r4 /* 1: Machine check */
260 addi r4,r3,DataStorage - _start + _START_OFFSET
261 mtspr IVOR2,r4 /* 2: Data storage */
262 addi r4,r3,InstStorage - _start + _START_OFFSET
263 mtspr IVOR3,r4 /* 3: Instruction storage */
264 addi r4,r3,ExtInterrupt - _start + _START_OFFSET
265 mtspr IVOR4,r4 /* 4: External interrupt */
266 addi r4,r3,Alignment - _start + _START_OFFSET
267 mtspr IVOR5,r4 /* 5: Alignment */
268 addi r4,r3,ProgramCheck - _start + _START_OFFSET
269 mtspr IVOR6,r4 /* 6: Program check */
270 addi r4,r3,FPUnavailable - _start + _START_OFFSET
271 mtspr IVOR7,r4 /* 7: floating point unavailable */
272 addi r4,r3,SystemCall - _start + _START_OFFSET
273 mtspr IVOR8,r4 /* 8: System call */
274 /* 9: Auxiliary processor unavailable(unsupported) */
275 addi r4,r3,Decrementer - _start + _START_OFFSET
276 mtspr IVOR10,r4 /* 10: Decrementer */
277 addi r4,r3,IntervalTimer - _start + _START_OFFSET
278 mtspr IVOR11,r4 /* 11: Interval timer */
279 addi r4,r3,WatchdogTimer - _start + _START_OFFSET
280 mtspr IVOR12,r4 /* 12: Watchdog timer */
281 addi r4,r3,DataTLBError - _start + _START_OFFSET
282 mtspr IVOR13,r4 /* 13: Data TLB error */
283 addi r4,r3,InstructionTLBError - _start + _START_OFFSET
284 mtspr IVOR14,r4 /* 14: Instruction TLB error */
285 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
286 mtspr IVOR15,r4 /* 15: Debug */
289 /* Clear and set up some registers. */
292 mtspr DEC,r0 /* prevent dec exceptions */
293 mttbl r0 /* prevent fit & wdt exceptions */
295 mtspr TSR,r1 /* clear all timer exception status */
296 mtspr TCR,r0 /* disable all */
297 mtspr ESR,r0 /* clear exception syndrome register */
298 mtspr MCSR,r0 /* machine check syndrome register */
299 mtxer r0 /* clear integer exception register */
301 #ifdef CONFIG_SYS_BOOK3E_HV
302 mtspr MAS8,r0 /* make sure MAS8 is clear */
305 /* Enable Time Base and Select Time Base Clock */
306 lis r0,HID0_EMCP@h /* Enable machine check */
307 #if defined(CONFIG_ENABLE_36BIT_PHYS)
308 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
310 #ifndef CONFIG_E500MC
311 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
315 #ifndef CONFIG_E500MC
316 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
319 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
321 /* Set MBDD bit also */
322 ori r0, r0, HID1_MBDD@l
327 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
333 /* Enable Branch Prediction */
334 #if defined(CONFIG_BTB)
335 lis r0,BUCSR_ENABLE@h
336 ori r0,r0,BUCSR_ENABLE@l
340 #if defined(CONFIG_SYS_INIT_DBCR)
343 mtspr DBSR,r1 /* Clear all status bits */
344 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
345 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
349 #ifdef CONFIG_MPC8569
350 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
351 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
353 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
354 * use address space which is more than 12bits, and it must be done in
355 * the 4K boot page. So we set this bit here.
358 /* create a temp mapping TLB0[0] for LBCR */
359 create_tlb0_entry 0, \
360 0, BOOKE_PAGESZ_4K, \
361 CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
362 CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
365 /* Set LBCR register */
366 lis r4,CONFIG_SYS_LBCR_ADDR@h
367 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
369 lis r5,CONFIG_SYS_LBC_LBCR@h
370 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
374 /* invalidate this temp TLB */
375 lis r4,CONFIG_SYS_LBC_ADDR@h
376 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
380 #endif /* CONFIG_MPC8569 */
383 * Search for the TLB that covers the code we're executing, and shrink it
384 * so that it covers only this 4K page. That will ensure that any other
385 * TLB we create won't interfere with it. We assume that the TLB exists,
386 * which is why we don't check the Valid bit of MAS1. We also assume
389 * This is necessary, for example, when booting from the on-chip ROM,
390 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
392 bl nexti /* Find our address */
393 nexti: mflr r1 /* R1 = our PC */
395 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
398 tlbsx 0, r1 /* This must succeed */
400 mfspr r14, MAS0 /* Save ESEL for later */
401 rlwinm r14, r14, 16, 0xfff
403 /* Set the size of the TLB to 4KB */
406 andc r3, r3, r2 /* Clear the TSIZE bits */
407 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
408 oris r3, r3, MAS1_IPROT@h
412 * Set the base address of the TLB to our PC. We assume that
413 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
416 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
418 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
423 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
426 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
427 rlwinm r2, r2, 0, ~MAS2_I
431 mtspr MAS2, r2 /* Set the EPN to our PC base address */
436 mtspr MAS3, r2 /* Set the RPN to our PC base address */
443 * Clear out any other TLB entries that may exist, to avoid conflicts.
444 * Our TLB entry is in r14.
446 li r0, TLBIVAX_ALL | TLBIVAX_TLB0
450 mfspr r4, SPRN_TLB1CFG
451 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
456 rlwinm r5, r3, 16, MAS0_ESEL_MSK
458 beq 2f /* skip the entry we're executing from */
460 oris r5, r5, MAS0_TLBSEL(1)@h
471 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
472 !defined(CONFIG_SECURE_BOOT)
474 * TLB entry for debuggging in AS1
475 * Create temporary TLB entry in AS0 to handle debug exception
476 * As on debug exception MSR is cleared i.e. Address space is changed
477 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
483 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
484 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
485 * and this window is outside of 4K boot window.
487 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
488 0, BOOKE_PAGESZ_4M, \
489 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
490 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
495 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
496 * because "nexti" will resize TLB to 4K
498 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
499 0, BOOKE_PAGESZ_256K, \
500 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
501 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
507 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
508 * location is not where we want it. This typically happens on a 36-bit
509 * system, where we want to move CCSR to near the top of 36-bit address space.
511 * To move CCSR, we create two temporary TLBs, one for the old location, and
512 * another for the new location. On CoreNet systems, we also need to create
513 * a special, temporary LAW.
515 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
516 * long-term TLBs, so we use TLB0 here.
518 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
520 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
521 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
526 * Create a TLB for the new location of CCSR. Register R8 is reserved
527 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
529 lis r8, CONFIG_SYS_CCSRBAR@h
530 ori r8, r8, CONFIG_SYS_CCSRBAR@l
531 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
532 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
533 create_tlb0_entry 0, \
534 0, BOOKE_PAGESZ_4K, \
535 CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
536 CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
537 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
539 * Create a TLB for the current location of CCSR. Register R9 is reserved
540 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
543 create_tlb0_entry 1, \
544 0, BOOKE_PAGESZ_4K, \
545 CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
546 CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
547 0, r3 /* The default CCSR address is always a 32-bit number */
551 * We have a TLB for what we think is the current (old) CCSR. Let's
552 * verify that, otherwise we won't be able to move it.
553 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
554 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
557 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
558 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
559 #ifdef CONFIG_FSL_CORENET
560 lwz r1, 4(r9) /* CCSRBARL */
562 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
569 * If the value we read from CCSRBARL is not what we expect, then
570 * enter an infinite loop. This will at least allow a debugger to
571 * halt execution and examine TLBs, etc. There's no point in going
575 bne infinite_debug_loop
577 #ifdef CONFIG_FSL_CORENET
579 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
580 #define LAW_EN 0x80000000
581 #define LAW_SIZE_4K 0xb
582 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
583 #define CCSRAR_C 0x80000000 /* Commit */
587 * On CoreNet systems, we create the temporary LAW using a special LAW
588 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
590 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
591 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
592 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
593 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
594 lis r2, CCSRBAR_LAWAR@h
595 ori r2, r2, CCSRBAR_LAWAR@l
597 stw r0, 0xc00(r9) /* LAWBARH0 */
598 stw r1, 0xc04(r9) /* LAWBARL0 */
600 stw r2, 0xc08(r9) /* LAWAR0 */
603 * Read back from LAWAR to ensure the update is complete. e500mc
604 * cores also require an isync.
606 lwz r0, 0xc08(r9) /* LAWAR0 */
610 * Read the current CCSRBARH and CCSRBARL using load word instructions.
611 * Follow this with an isync instruction. This forces any outstanding
612 * accesses to configuration space to completion.
615 lwz r0, 0(r9) /* CCSRBARH */
616 lwz r0, 4(r9) /* CCSRBARL */
620 * Write the new values for CCSRBARH and CCSRBARL to their old
621 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
622 * has a new value written it loads a CCSRBARH shadow register. When
623 * the CCSRBARL is written, the CCSRBARH shadow register contents
624 * along with the CCSRBARL value are loaded into the CCSRBARH and
625 * CCSRBARL registers, respectively. Follow this with a sync
629 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
630 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
631 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
632 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
634 ori r2, r2, CCSRAR_C@l
636 stw r0, 0(r9) /* Write to CCSRBARH */
637 sync /* Make sure we write to CCSRBARH first */
638 stw r1, 4(r9) /* Write to CCSRBARL */
642 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
643 * Follow this with a sync instruction.
648 /* Delete the temporary LAW */
657 #else /* #ifdef CONFIG_FSL_CORENET */
661 * Read the current value of CCSRBAR using a load word instruction
662 * followed by an isync. This forces all accesses to configuration
669 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
670 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
671 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
673 /* Write the new value to CCSRBAR. */
674 lis r0, CCSRBAR_PHYS_RS12@h
675 ori r0, r0, CCSRBAR_PHYS_RS12@l
680 * The manual says to perform a load of an address that does not
681 * access configuration space or the on-chip SRAM using an existing TLB,
682 * but that doesn't appear to be necessary. We will do the isync,
688 * Read the contents of CCSRBAR from its new location, followed by
694 #endif /* #ifdef CONFIG_FSL_CORENET */
696 /* Delete the temporary TLBs */
698 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
699 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
701 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
703 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
706 * Create a TLB for the MMR location of CCSR
707 * to access L2CSR0 register
709 create_tlb0_entry 0, \
710 0, BOOKE_PAGESZ_4K, \
711 CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
712 CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
713 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
715 enable_l2_cluster_l2:
716 /* enable L2 cache */
717 lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
718 ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
719 li r4, 33 /* stash id */
721 lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
722 ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
724 stw r4, 0(r3) /* invalidate L2 */
731 lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
732 ori r4, r4, (L2CSR0_L2REP_MODE)@l
734 stw r4, 0(r3) /* enable L2 */
736 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
740 * Enable the L1. On e6500, this has to be done
741 * after the L2 is up.
744 #ifdef CONFIG_SYS_CACHE_STASHING
745 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
750 /* Enable/invalidate the I-Cache */
751 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
752 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
759 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
760 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
765 andi. r1,r3,L1CSR1_ICE@l
768 /* Enable/invalidate the D-Cache */
769 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
770 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
777 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
778 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
783 andi. r1,r3,L1CSR0_DCE@l
785 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
786 #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
787 #define LAW_SIZE_1M 0x13
788 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
794 * Create a TLB entry for CCSR
796 * We're executing out of TLB1 entry in r14, and that's the only
797 * TLB entry that exists. To allocate some TLB entries for our
798 * own use, flip a bit high enough that we won't flip it again
803 lis r0, MAS0_TLBSEL(1)@h
804 rlwimi r0, r8, 16, MAS0_ESEL_MSK
805 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
806 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
807 lis r7, CONFIG_SYS_CCSRBAR@h
808 ori r7, r7, CONFIG_SYS_CCSRBAR@l
809 ori r2, r7, MAS2_I|MAS2_G
810 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
811 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
812 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
813 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
824 /* Map DCSR temporarily to physical address zero */
826 lis r3, DCSRBAR_LAWAR@h
827 ori r3, r3, DCSRBAR_LAWAR@l
829 stw r0, 0xc00(r7) /* LAWBARH0 */
830 stw r0, 0xc04(r7) /* LAWBARL0 */
832 stw r3, 0xc08(r7) /* LAWAR0 */
834 /* Read back from LAWAR to ensure the update is complete. */
835 lwz r3, 0xc08(r7) /* LAWAR0 */
838 /* Create a TLB entry for DCSR at zero */
841 lis r0, MAS0_TLBSEL(1)@h
842 rlwimi r0, r9, 16, MAS0_ESEL_MSK
843 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
844 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
845 li r6, 0 /* DCSR effective address */
846 ori r2, r6, MAS2_I|MAS2_G
847 li r3, MAS3_SW|MAS3_SR
859 /* enable the timebase */
860 #define CTBENR 0xe2084
862 addis r4, r7, CTBENR@ha
868 .macro erratum_set_ccsr offset value
869 addis r3, r7, \offset@ha
871 addi r3, r3, \offset@l
876 .macro erratum_set_dcsr offset value
877 addis r3, r6, \offset@ha
879 addi r3, r3, \offset@l
884 erratum_set_dcsr 0xb0e08 0xe0201800
885 erratum_set_dcsr 0xb0e18 0xe0201800
886 erratum_set_dcsr 0xb0e38 0xe0400000
887 erratum_set_dcsr 0xb0008 0x00900000
888 erratum_set_dcsr 0xb0e40 0xe00a0000
889 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
890 #ifdef CONFIG_RAMBOOT_PBL
891 erratum_set_ccsr 0x10f00 0x495e5000
893 erratum_set_ccsr 0x10f00 0x415e5000
895 erratum_set_ccsr 0x11f00 0x415e5000
897 /* Make temp mapping uncacheable again, if it was initially */
902 rlwimi r4, r15, 0, MAS2_I
903 rlwimi r4, r15, 0, MAS2_G
910 /* Clear the cache */
911 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
912 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
922 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
923 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
933 /* Remove temporary mappings */
934 lis r0, MAS0_TLBSEL(1)@h
935 rlwimi r0, r9, 16, MAS0_ESEL_MSK
945 stw r3, 0xc08(r7) /* LAWAR0 */
949 lis r0, MAS0_TLBSEL(1)@h
950 rlwimi r0, r8, 16, MAS0_ESEL_MSK
961 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
963 /* Lock two cache lines into I-Cache */
965 mfspr r11, SPRN_L1CSR1
966 rlwinm r11, r11, 0, ~L1CSR1_ICUL
969 mtspr SPRN_L1CSR1, r11
980 mfspr r11, SPRN_L1CSR1
981 3: andi. r11, r11, L1CSR1_ICUL
988 mfspr r11, SPRN_L1CSR1
989 3: andi. r11, r11, L1CSR1_ICUL
994 /* Inside a locked cacheline, wait a while, write, then wait a while */
998 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
999 4: mfspr r5, SPRN_TBRL
1006 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
1007 4: mfspr r5, SPRN_TBRL
1014 * Fill out the rest of this cache line and the next with nops,
1015 * to ensure that nothing outside the locked area will be
1016 * fetched due to a branch.
1023 mfspr r11, SPRN_L1CSR1
1024 rlwinm r11, r11, 0, ~L1CSR1_ICUL
1027 mtspr SPRN_L1CSR1, r11
1036 create_init_ram_area:
1037 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
1038 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
1041 /* create a temp mapping in AS=1 to the 4M boot window */
1042 create_tlb1_entry 15, \
1043 1, BOOKE_PAGESZ_4M, \
1044 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
1045 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1048 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
1049 /* create a temp mapping in AS = 1 for Flash mapping
1050 * created by PBL for ISBC code
1052 create_tlb1_entry 15, \
1053 1, BOOKE_PAGESZ_1M, \
1054 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1055 CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1059 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
1060 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
1062 create_tlb1_entry 15, \
1063 1, BOOKE_PAGESZ_1M, \
1064 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1065 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1069 /* create a temp mapping in AS=1 to the stack */
1070 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
1071 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
1072 create_tlb1_entry 14, \
1073 1, BOOKE_PAGESZ_16K, \
1074 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1075 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
1076 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
1079 create_tlb1_entry 14, \
1080 1, BOOKE_PAGESZ_16K, \
1081 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1082 CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
1086 lis r6,MSR_IS|MSR_DS|MSR_DE@h
1087 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
1089 ori r7,r7,switch_as@l
1096 /* L1 DCache is used for initial RAM */
1098 /* Allocate Initial RAM in data cache.
1100 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1101 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1104 /* cache size * 1024 / (2 * L1 line size) */
1105 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
1111 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1114 /* Jump out the last 4K page and continue to 'normal' start */
1115 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
1116 /* We assume that we're already running at the address we're linked at */
1119 /* Calculate absolute address in FLASH and jump there */
1120 /*--------------------------------------------------------------*/
1121 lis r3,CONFIG_SYS_MONITOR_BASE@h
1122 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
1123 addi r3,r3,_start_cont - _start + _START_OFFSET
1131 .long 0x27051956 /* U-BOOT Magic Number */
1132 .globl version_string
1134 .ascii U_BOOT_VERSION_STRING, "\0"
1139 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
1140 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1141 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
1143 stw r0,0(r3) /* Terminate Back Chain */
1144 stw r0,+4(r3) /* NULL return address. */
1145 mr r1,r3 /* Transfer to SP(r1) */
1149 /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */
1154 /* switch back to AS = 0 */
1155 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1156 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1164 /* NOTREACHED - board_init_f() does not return */
1167 . = EXC_OFF_SYS_RESET
1168 .globl _start_of_vectors
1171 /* Critical input. */
1172 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
1175 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
1177 /* Data Storage exception. */
1178 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
1180 /* Instruction Storage exception. */
1181 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
1183 /* External Interrupt exception. */
1184 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
1186 /* Alignment exception. */
1189 EXCEPTION_PROLOG(SRR0, SRR1)
1194 addi r3,r1,STACK_FRAME_OVERHEAD
1195 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
1197 /* Program check exception */
1200 EXCEPTION_PROLOG(SRR0, SRR1)
1201 addi r3,r1,STACK_FRAME_OVERHEAD
1202 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
1203 MSR_KERNEL, COPY_EE)
1205 /* No FPU on MPC85xx. This exception is not supposed to happen.
1207 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
1211 * r0 - SYSCALL number
1215 addis r11,r0,0 /* get functions table addr */
1216 ori r11,r11,0 /* Note: this code is patched in trap_init */
1217 addis r12,r0,0 /* get number of functions */
1223 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
1227 li r20,0xd00-4 /* Get stack pointer */
1229 subi r12,r12,12 /* Adjust stack pointer */
1230 li r0,0xc00+_end_back-SystemCall
1231 cmplw 0,r0,r12 /* Check stack overflow */
1242 li r12,0xc00+_back-SystemCall
1250 mfmsr r11 /* Disable interrupts */
1254 SYNC /* Some chip revs need this... */
1258 li r12,0xd00-4 /* restore regs */
1268 addi r12,r12,12 /* Adjust stack pointer */
1276 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
1277 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
1278 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
1280 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
1281 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
1283 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
1285 .globl _end_of_vectors
1289 . = . + (0x100 - ( . & 0xff )) /* align for debug */
1292 * This code finishes saving the registers to the exception frame
1293 * and jumps to the appropriate handler for the exception.
1294 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1296 .globl transfer_to_handler
1297 transfer_to_handler:
1308 andi. r24,r23,0x3f00 /* get vector offset */
1312 mtspr SPRG2,r22 /* r1 is now kernel sp */
1314 lwz r24,0(r23) /* virtual address of handler */
1315 lwz r23,4(r23) /* where to go when done */
1320 rfi /* jump to handler, enable MMU */
1323 mfmsr r28 /* Disable interrupts */
1327 SYNC /* Some chip revs need this... */
1342 lwz r2,_NIP(r1) /* Restore environment */
1353 mfmsr r28 /* Disable interrupts */
1357 SYNC /* Some chip revs need this... */
1372 lwz r2,_NIP(r1) /* Restore environment */
1383 mfmsr r28 /* Disable interrupts */
1387 SYNC /* Some chip revs need this... */
1402 lwz r2,_NIP(r1) /* Restore environment */
1404 mtspr SPRN_MCSRR0,r2
1405 mtspr SPRN_MCSRR1,r0
1416 .globl invalidate_icache
1419 ori r0,r0,L1CSR1_ICFI
1424 blr /* entire I cache */
1426 .globl invalidate_dcache
1429 ori r0,r0,L1CSR0_DCFI
1436 .globl icache_enable
1439 bl invalidate_icache
1449 .globl icache_disable
1453 ori r3,r3,L1CSR1_ICE
1459 .globl icache_status
1462 andi. r3,r3,L1CSR1_ICE
1465 .globl dcache_enable
1468 bl invalidate_dcache
1480 .globl dcache_disable
1484 ori r4,r4,L1CSR0_DCE
1490 .globl dcache_status
1493 andi. r3,r3,L1CSR0_DCE
1516 /*------------------------------------------------------------------------------- */
1518 /* Description: Input 8 bits */
1519 /*------------------------------------------------------------------------------- */
1525 /*------------------------------------------------------------------------------- */
1526 /* Function: out8 */
1527 /* Description: Output 8 bits */
1528 /*------------------------------------------------------------------------------- */
1535 /*------------------------------------------------------------------------------- */
1536 /* Function: out16 */
1537 /* Description: Output 16 bits */
1538 /*------------------------------------------------------------------------------- */
1545 /*------------------------------------------------------------------------------- */
1546 /* Function: out16r */
1547 /* Description: Byte reverse and output 16 bits */
1548 /*------------------------------------------------------------------------------- */
1555 /*------------------------------------------------------------------------------- */
1556 /* Function: out32 */
1557 /* Description: Output 32 bits */
1558 /*------------------------------------------------------------------------------- */
1565 /*------------------------------------------------------------------------------- */
1566 /* Function: out32r */
1567 /* Description: Byte reverse and output 32 bits */
1568 /*------------------------------------------------------------------------------- */
1575 /*------------------------------------------------------------------------------- */
1576 /* Function: in16 */
1577 /* Description: Input 16 bits */
1578 /*------------------------------------------------------------------------------- */
1584 /*------------------------------------------------------------------------------- */
1585 /* Function: in16r */
1586 /* Description: Input 16 bits and byte reverse */
1587 /*------------------------------------------------------------------------------- */
1593 /*------------------------------------------------------------------------------- */
1594 /* Function: in32 */
1595 /* Description: Input 32 bits */
1596 /*------------------------------------------------------------------------------- */
1602 /*------------------------------------------------------------------------------- */
1603 /* Function: in32r */
1604 /* Description: Input 32 bits and byte reverse */
1605 /*------------------------------------------------------------------------------- */
1610 #endif /* !MINIMAL_SPL */
1612 /*------------------------------------------------------------------------------*/
1615 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1623 #ifdef CONFIG_ENABLE_36BIT_PHYS
1627 #ifdef CONFIG_SYS_BOOK3E_HV
1637 * void relocate_code (addr_sp, gd, addr_moni)
1639 * This "function" does not return, instead it continues in RAM
1640 * after relocating the monitor code.
1644 * r5 = length in bytes
1645 * r6 = cachelinesize
1647 .globl relocate_code
1649 mr r1,r3 /* Set new stack pointer */
1650 mr r9,r4 /* Save copy of Init Data pointer */
1651 mr r10,r5 /* Save copy of Destination Address */
1654 mr r3,r5 /* Destination Address */
1655 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1656 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1657 lwz r5,GOT(__init_end)
1659 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1664 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1670 /* First our own GOT */
1672 /* the the one used by the C code */
1682 beq cr1,4f /* In place copy is not necessary */
1683 beq 7f /* Protect against 0 count */
1702 * Now flush the cache: note that we must start from a cache aligned
1703 * address. Otherwise we might miss one cache line.
1707 beq 7f /* Always flush prefetch queue in any case */
1715 sync /* Wait for all dcbst to complete on bus */
1721 7: sync /* Wait for all icbi to complete on bus */
1725 * We are done. Do not return, instead branch to second part of board
1726 * initialization, now running from RAM.
1729 addi r0,r10,in_ram - _start + _START_OFFSET
1732 * As IVPR is going to point RAM address,
1733 * Make sure IVOR15 has valid opcode to support debugger
1738 * Re-point the IVPR at RAM
1743 blr /* NEVER RETURNS! */
1748 * Relocation Function, r12 point to got2+0x8000
1750 * Adjust got2 pointers, no need to check for 0, this code
1751 * already puts a few entries in the table.
1753 li r0,__got2_entries@sectoff@l
1754 la r3,GOT(_GOT2_TABLE_)
1755 lwz r11,GOT(_GOT2_TABLE_)
1767 * Now adjust the fixups and the pointers to the fixups
1768 * in case we need to move ourselves again.
1770 li r0,__fixup_entries@sectoff@l
1771 lwz r3,GOT(_FIXUP_TABLE_)
1787 * Now clear BSS segment
1789 lwz r3,GOT(__bss_start)
1790 lwz r4,GOT(__bss_end)
1803 mr r3,r9 /* Init Data pointer */
1804 mr r4,r10 /* Destination Address */
1809 * Copy exception vector code to low memory
1812 * r7: source address, r8: end address, r9: target address
1816 mflr r4 /* save link register */
1818 lwz r7,GOT(_start_of_vectors)
1819 lwz r8,GOT(_end_of_vectors)
1821 li r9,0x100 /* reset vector always at 0x100 */
1824 bgelr /* return if r7>=r8 - just in case */
1834 * relocate `hdlr' and `int_return' entries
1836 li r7,.L_CriticalInput - _start + _START_OFFSET
1838 li r7,.L_MachineCheck - _start + _START_OFFSET
1840 li r7,.L_DataStorage - _start + _START_OFFSET
1842 li r7,.L_InstStorage - _start + _START_OFFSET
1844 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1846 li r7,.L_Alignment - _start + _START_OFFSET
1848 li r7,.L_ProgramCheck - _start + _START_OFFSET
1850 li r7,.L_FPUnavailable - _start + _START_OFFSET
1852 li r7,.L_Decrementer - _start + _START_OFFSET
1854 li r7,.L_IntervalTimer - _start + _START_OFFSET
1855 li r8,_end_of_vectors - _start + _START_OFFSET
1858 addi r7,r7,0x100 /* next exception vector */
1862 /* Update IVORs as per relocated vector table address */
1864 mtspr IVOR0,r7 /* 0: Critical input */
1866 mtspr IVOR1,r7 /* 1: Machine check */
1868 mtspr IVOR2,r7 /* 2: Data storage */
1870 mtspr IVOR3,r7 /* 3: Instruction storage */
1872 mtspr IVOR4,r7 /* 4: External interrupt */
1874 mtspr IVOR5,r7 /* 5: Alignment */
1876 mtspr IVOR6,r7 /* 6: Program check */
1878 mtspr IVOR7,r7 /* 7: floating point unavailable */
1880 mtspr IVOR8,r7 /* 8: System call */
1881 /* 9: Auxiliary processor unavailable(unsupported) */
1883 mtspr IVOR10,r7 /* 10: Decrementer */
1885 mtspr IVOR11,r7 /* 11: Interval timer */
1887 mtspr IVOR12,r7 /* 12: Watchdog timer */
1889 mtspr IVOR13,r7 /* 13: Data TLB error */
1891 mtspr IVOR14,r7 /* 14: Instruction TLB error */
1893 mtspr IVOR15,r7 /* 15: Debug */
1898 mtlr r4 /* restore link register */
1901 .globl unlock_ram_in_cache
1902 unlock_ram_in_cache:
1903 /* invalidate the INIT_RAM section */
1904 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1905 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1908 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1912 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1916 /* Invalidate the TLB entries for the cache */
1917 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1918 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1931 mfspr r3,SPRN_L1CFG0
1933 rlwinm r5,r3,9,3 /* Extract cache block size */
1934 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1935 * are currently defined.
1938 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1939 * log2(number of ways)
1941 slw r5,r4,r5 /* r5 = cache block size */
1943 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1944 mulli r7,r7,13 /* An 8-way cache will require 13
1949 /* save off HID0 and set DCFA */
1951 ori r9,r8,HID0_DCFA@l
1958 1: lwz r3,0(r4) /* Load... */
1966 1: dcbf 0,r4 /* ...and flush. */
1975 #endif /* !MINIMAL_SPL */