2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/fsl_serdes.h>
9 #include <asm/processor.h>
11 #include "fsl_corenet2_serdes.h"
13 struct serdes_config {
15 u8 lanes[SRDS_MAX_LANES];
18 #ifdef CONFIG_PPC_T4240
19 static const struct serdes_config serdes1_cfg_tbl[] = {
21 {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
22 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
23 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
24 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
25 {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
26 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
27 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
28 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
29 {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
30 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
31 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
32 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
33 {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
34 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
35 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
36 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
37 {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
38 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
39 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
40 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
41 {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
42 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
43 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
44 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
45 {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
46 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
47 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
48 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
49 {37, {NONE, NONE, QSGMII_FM1_B, NONE,
50 NONE, NONE, QSGMII_FM1_A, NONE} },
51 {38, {NONE, NONE, QSGMII_FM1_B, NONE,
52 NONE, NONE, QSGMII_FM1_A, NONE}},
53 {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
54 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
55 NONE, NONE, QSGMII_FM1_A, NONE} },
56 {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
57 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
58 NONE, NONE, QSGMII_FM1_A, NONE}},
59 {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
60 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
61 NONE, NONE, QSGMII_FM1_A, NONE} },
62 {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
63 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
64 NONE, NONE, QSGMII_FM1_A, NONE}},
65 {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
66 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
67 NONE, NONE, QSGMII_FM1_A, NONE} },
68 {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
69 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
70 NONE, NONE, QSGMII_FM1_A, NONE}},
73 static const struct serdes_config serdes2_cfg_tbl[] = {
75 {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
76 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
77 XAUI_FM2_MAC10, XAUI_FM2_MAC10,
78 XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
79 {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
80 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
81 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
82 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
83 {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
84 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
85 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
86 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
87 {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
88 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
89 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
90 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
91 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
92 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
93 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
94 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
95 {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
96 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
97 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
98 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
99 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
100 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
101 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
102 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
103 {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
104 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
105 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
106 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
107 {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
108 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
109 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
110 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
111 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
112 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
113 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
114 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
115 {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
116 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
117 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
118 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
119 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
120 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
121 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
122 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
123 {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
124 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
125 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
126 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
127 {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
128 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
129 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
130 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
131 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
132 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
133 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
134 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
135 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
136 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
137 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
138 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
139 {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
140 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
141 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
142 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
143 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
144 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
145 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
146 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
147 {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
148 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
149 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
150 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
151 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
152 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
153 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
154 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
155 {37, {NONE, NONE, QSGMII_FM2_B, NONE,
156 NONE, NONE, QSGMII_FM2_A, NONE} },
157 {38, {NONE, NONE, QSGMII_FM2_B, NONE,
158 NONE, NONE, QSGMII_FM2_A, NONE} },
159 {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
160 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
161 NONE, NONE, QSGMII_FM2_A, NONE} },
162 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
163 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
164 NONE, NONE, QSGMII_FM2_A, NONE} },
165 {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
166 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
167 NONE, NONE, QSGMII_FM2_A, NONE} },
168 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
169 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
170 NONE, NONE, QSGMII_FM2_A, NONE} },
171 {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
172 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
173 NONE, NONE, QSGMII_FM2_A, NONE} },
174 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
175 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
176 NONE, NONE, QSGMII_FM2_A, NONE} },
177 {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
178 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
179 NONE, NONE, QSGMII_FM2_A, NONE} },
180 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
181 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
182 NONE, NONE, QSGMII_FM2_A, NONE} },
183 {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
184 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
185 NONE, NONE, QSGMII_FM2_A, NONE} },
186 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
187 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
188 NONE, NONE, QSGMII_FM2_A, NONE} },
189 {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
190 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
191 NONE, NONE, QSGMII_FM2_A, NONE} },
192 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
193 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
194 NONE, NONE, QSGMII_FM2_A, NONE} },
195 {55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
196 XFI_FM2_MAC10, XFI_FM2_MAC9,
197 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
198 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
199 {56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
200 XFI_FM2_MAC10, XFI_FM2_MAC9,
201 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
202 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
203 {57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
204 XFI_FM2_MAC10, XFI_FM2_MAC9,
205 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
206 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
209 static const struct serdes_config serdes3_cfg_tbl[] = {
211 {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
212 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
213 {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
214 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
215 {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
216 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
217 {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
218 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
219 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
220 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
221 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
222 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
223 {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
224 PCIE2, PCIE2, PCIE2, PCIE2} },
225 {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
226 PCIE2, PCIE2, PCIE2, PCIE2}},
227 {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
228 PCIE2, PCIE2, PCIE2, PCIE2} },
229 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
230 PCIE2, PCIE2, PCIE2, PCIE2}},
231 {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
232 SRIO1, SRIO1, SRIO1, SRIO1} },
233 {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
234 SRIO1, SRIO1, SRIO1, SRIO1}},
235 {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
236 SRIO1, SRIO1, SRIO1, SRIO1}},
237 {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
238 SRIO1, SRIO1, SRIO1, SRIO1} },
239 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
240 SRIO1, SRIO1, SRIO1, SRIO1}},
241 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
242 SRIO1, SRIO1, SRIO1, SRIO1}},
245 static const struct serdes_config serdes4_cfg_tbl[] = {
247 {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
248 {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
249 {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
250 {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
251 {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
252 {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
253 {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
254 {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
255 {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
256 {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
257 {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
258 {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
259 {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
260 {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
261 {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
262 {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
263 {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
266 #elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
267 static const struct serdes_config serdes1_cfg_tbl[] = {
269 {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
270 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
271 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
272 XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
273 {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
274 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
275 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
276 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
277 {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
278 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
279 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
280 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
281 {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
282 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
283 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
284 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
285 {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
286 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
287 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
288 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
289 {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
290 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
291 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
292 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
293 {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
294 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
295 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
296 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
297 {37, {NONE, NONE, QSGMII_FM1_B, NONE,
298 NONE, NONE, QSGMII_FM1_A, NONE} },
299 {38, {NONE, NONE, QSGMII_FM1_B, NONE,
300 NONE, NONE, QSGMII_FM1_A, NONE} },
303 static const struct serdes_config serdes2_cfg_tbl[] = {
305 {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
306 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
307 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
308 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
309 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
310 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
311 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
312 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
313 {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
314 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
315 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
316 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
317 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
318 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
319 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
320 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
321 {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
322 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
323 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
324 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
325 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
326 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
327 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
328 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
329 {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
330 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
331 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
332 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
333 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
334 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
335 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
336 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
337 {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
338 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
339 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
340 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
341 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
342 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
343 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
344 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
345 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
346 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
347 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
349 {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
350 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
351 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
352 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
353 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
354 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
355 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
356 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
357 {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
358 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
359 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
360 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
361 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
362 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
363 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
364 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
365 {37, {NONE, NONE, QSGMII_FM2_B, NONE,
366 NONE, QSGMII_FM1_A, NONE, NONE} },
367 {38, {NONE, NONE, QSGMII_FM2_B, NONE,
368 NONE, QSGMII_FM1_A, NONE, NONE} },
369 {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
370 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
371 NONE, QSGMII_FM1_A, NONE, NONE} },
372 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
373 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
374 NONE, QSGMII_FM1_A, NONE, NONE} },
375 {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
376 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
377 NONE, QSGMII_FM1_A, NONE, NONE} },
378 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
379 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
380 NONE, QSGMII_FM1_A, NONE, NONE} },
381 {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
382 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
383 NONE, QSGMII_FM1_A, NONE, NONE} },
384 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
385 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
386 NONE, QSGMII_FM1_A, NONE, NONE} },
387 {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
388 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
389 NONE, NONE, NONE, NONE} },
390 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
391 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
392 NONE, NONE, NONE, NONE} },
393 {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
394 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
395 NONE, NONE, NONE, NONE} },
396 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
397 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
398 NONE, NONE, NONE, NONE} },
399 {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
400 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
401 NONE, NONE, NONE, NONE} },
402 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
403 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
404 NONE, NONE, NONE, NONE} },
405 {55, {NONE, XFI_FM1_MAC10,
407 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
408 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
409 {56, {NONE, XFI_FM1_MAC10,
411 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
412 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
413 {57, {NONE, XFI_FM1_MAC10,
415 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
419 static const struct serdes_config serdes3_cfg_tbl[] = {
421 {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
422 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
423 {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
424 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
425 {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
426 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
427 {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
428 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
429 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
430 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
431 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
432 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
433 {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
434 PCIE2, PCIE2, PCIE2, PCIE2} },
435 {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
436 PCIE2, PCIE2, PCIE2, PCIE2} },
437 {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
438 PCIE2, PCIE2, PCIE2, PCIE2} },
439 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
440 PCIE2, PCIE2, PCIE2, PCIE2} },
441 {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
442 SRIO1, SRIO1, SRIO1, SRIO1} },
443 {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
444 SRIO1, SRIO1, SRIO1, SRIO1} },
445 {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
446 SRIO1, SRIO1, SRIO1, SRIO1} },
447 {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
448 SRIO1, SRIO1, SRIO1, SRIO1} },
449 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
450 SRIO1, SRIO1, SRIO1, SRIO1} },
451 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
452 NONE, NONE, NONE, NONE} },
455 static const struct serdes_config serdes4_cfg_tbl[] = {
457 {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
458 {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
459 {5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
460 {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
461 {7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
462 {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
463 {9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
464 {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
465 {11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
466 {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
467 {13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
468 {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
469 {15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
470 {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
471 {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
476 #error "Need to define SerDes protocol"
478 static const struct serdes_config *serdes_cfg_tbl[] = {
485 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
487 const struct serdes_config *ptr;
489 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
492 ptr = serdes_cfg_tbl[serdes];
493 while (ptr->protocol) {
494 if (ptr->protocol == cfg)
495 return ptr->lanes[lane];
501 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
504 const struct serdes_config *ptr;
506 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
509 ptr = serdes_cfg_tbl[serdes];
510 while (ptr->protocol) {
511 if (ptr->protocol == prtcl)
519 for (i = 0; i < SRDS_MAX_LANES; i++) {
520 if (ptr->lanes[i] != NONE)