2 * Copyright 2004,2009-2010 Freescale Semiconductor, Inc.
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * cpu_init.c - low level cpu init
33 #include <asm/fsl_law.h>
34 #include <asm/fsl_serdes.h>
37 void setup_bats(void);
39 DECLARE_GLOBAL_DATA_PTR;
42 * Breathe some life into the CPU...
44 * Set up the memory map
45 * initialize a bunch of registers
50 /* Pointer is writable since we allocated a register for it */
51 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
53 /* Clear initial global data */
54 memset ((void *) gd, 0, sizeof (gd_t));
62 init_early_memctl_regs();
64 #if defined(CONFIG_FSL_DMA)
68 /* enable the timebase bit in HID0 */
69 set_hid0(get_hid0() | 0x4000000);
71 /* enable EMCP, SYNCBE | ABE bits in HID1 */
72 set_hid1(get_hid1() | 0x80000C00);
76 * initialize higher level parts of CPU like timers
80 /* needs to be in ram since code uses global static vars */
83 #if defined(CONFIG_MP)
89 /* Set up BAT registers */
92 #if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L)
93 write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L);
95 #if defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
96 write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L);
98 write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L);
99 write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L);
100 write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L);
101 write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L);
102 write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L);
103 write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L);
104 write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L);
105 write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L);
106 write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L);
107 write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L);
108 write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
109 write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
110 write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L);
111 write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L);
116 #ifdef CONFIG_ADDR_MAP
117 /* Initialize address mapping array */
118 void init_addr_map(void)
121 ppc_bat_t bat = DBAT0;
123 unsigned long upper, lower;
125 for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) {
126 if (read_bat(bat, &upper, &lower) != -1) {
127 if (!BATU_VALID(upper))
130 size = BATU_SIZE(upper);
131 addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
134 #ifdef CONFIG_HIGH_BATS
135 /* High bats are not contiguous with low BAT numbers */