2 * Copyright 2004, 2007, 2008 Freescale Semiconductor.
3 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <ppc_asm.tmpl>
13 #include <asm/cache.h>
16 /* If this is a multi-cpu system then we need to handle the
17 * 2nd cpu. The assumption is that the 2nd cpu is being
18 * held in boot holdoff mode until the 1st cpu unlocks it
19 * from Linux. We'll do some basic cpu init and then pass
20 * it to the Linux Reset Vector.
21 * Sri: Much of this initialization is not required. Linux
22 * rewrites the bats, and the sprs and also enables the L1 cache.
24 * Core 0 must copy this to a 1M aligned region and set BPTR
28 .globl __secondary_start_page
29 __secondary_start_page:
30 .space 0x100 /* space over to reset vector loc */
58 /* enable extended addressing */
60 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
61 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
67 /* init the L2 cache */
68 addis r3, r0, L2_INIT@h
75 /* invalidate the L2 cache */
77 rlwinm. r3, r3, 0, 0, 0
81 rlwinm r3, r3, 0, 1, 31
90 oris r3, r3, L2CR_L2I@h
95 andis. r3, r3, L2CR_L2I@h
100 /* enable and invalidate the data cache */
102 li r5, HID0_DCFI|HID0_DLOCK
104 mtspr HID0, r3 /* no invalidate, unlock */
106 ori r5, r3, HID0_DCFI
107 mtspr HID0, r5 /* enable + invalidate */
108 mtspr HID0, r3 /* enable */
113 ori r3, r3, L2_ENABLE@l
119 /* enable and invalidate the instruction cache*/
121 li r5, HID0_ICFI|HID0_ILOCK
124 ori r5, r3, HID0_ICFI
137 /* MCP|SYNCBE|ABE in HID1 */
145 lis r3, CONFIG_LINUX_RESET_VEC@h
146 ori r3, r3, CONFIG_LINUX_RESET_VEC@l
150 /* Never Returns, Running in Linux Now */