2 * Copyright 2004, 2007 Freescale Semiconductor.
3 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
27 * The processor starts at 0xfff00100 and the code is executed
28 * from flash. The code is organized to be at an other address
29 * in memory, but as long we don't jump around before relocating.
30 * board_init lies at a quite high address and when the cpu has
31 * jumped there, everything is ok.
35 #include <timestamp.h>
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
43 #include <asm/u-boot.h>
45 #ifndef CONFIG_IDENT_STRING
46 #define CONFIG_IDENT_STRING ""
50 * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
54 * Set up GOT: Global Offset Table
56 * Use r12 to access the GOT
59 GOT_ENTRY(_GOT2_TABLE_)
60 GOT_ENTRY(_FIXUP_TABLE_)
63 GOT_ENTRY(_start_of_vectors)
64 GOT_ENTRY(_end_of_vectors)
65 GOT_ENTRY(transfer_to_handler)
69 GOT_ENTRY(__bss_start)
73 * r3 - 1st arg to board_init(): IMMP pointer
74 * r4 - 2nd arg to board_init(): boot flag
77 .long 0x27051956 /* U-Boot Magic Number */
81 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
82 .ascii CONFIG_IDENT_STRING, "\0"
89 /* the boot code is located below the exception table */
91 .globl _start_of_vectors
95 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
97 /* Data Storage exception. */
98 STD_EXCEPTION(0x300, DataStorage, UnknownException)
100 /* Instruction Storage exception. */
101 STD_EXCEPTION(0x400, InstStorage, UnknownException)
103 /* External Interrupt exception. */
104 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
106 /* Alignment exception. */
109 EXCEPTION_PROLOG(SRR0, SRR1)
114 addi r3,r1,STACK_FRAME_OVERHEAD
115 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
117 /* Program check exception */
120 EXCEPTION_PROLOG(SRR0, SRR1)
121 addi r3,r1,STACK_FRAME_OVERHEAD
122 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
125 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
127 /* I guess we could implement decrementer, and may have
128 * to someday for timekeeping.
130 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
131 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
132 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
133 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
134 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
135 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
136 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
137 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
138 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
139 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
140 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
141 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
142 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
143 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
144 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
145 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
146 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
147 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
148 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
149 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
150 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
151 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
152 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
154 .globl _end_of_vectors
161 * NOTE: Only Cpu 0 will ever come here. Other cores go to an
162 * address specified by the BPTR
165 #ifdef CONFIG_SYS_RAMBOOT
166 /* disable everything */
173 /* Invalidate BATs */
176 /* Invalidate all of TLB before MMU turn on */
181 /* init the L2 cache */
183 ori r3, r3, L2_INIT@l
185 /* invalidate the L2 cache */
186 bl l2cache_invalidate
191 * Calculate absolute address in FLASH and jump there
192 *------------------------------------------------------*/
193 lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
194 ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
195 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
200 /* let the C-code set up the rest */
202 /* Be careful to keep code relocatable ! */
203 /*------------------------------------------------------*/
204 /* perform low-level init */
206 /* enable extended addressing */
213 * Cache must be enabled here for stack-in-cache trick.
214 * This means we need to enable the BATS.
215 * Cache should be turned on after BATs, since by default
216 * everything is write-through.
219 /* enable address translation */
221 ori r5, r5, (MSR_IR | MSR_DR)
222 lis r3,addr_trans_enabled@h
223 ori r3, r3, addr_trans_enabled@l
229 /* enable and invalidate the data cache */
230 /* bl l1dcache_enable */
238 #ifdef CONFIG_SYS_INIT_RAM_LOCK
243 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
247 /* set up the stack pointer in our newly created
249 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
250 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
252 li r0, 0 /* Make room for stack frame header and */
253 stwu r0, -4(r1) /* clear final stack frame so that */
254 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
256 GET_GOT /* initialize GOT access */
258 /* run low-level CPU init code (from Flash) */
264 /* Load PX_AUX register address in r4 */
267 /* Load contents of PX_AUX in r3 bits 24 to 31*/
270 /* Mask and obtain the bit in r3 */
271 rlwinm. r3, r3, 0, 24, 24
272 /* If not zero, jump and continue with u-boot */
275 /* Load back contents of PX_AUX in r3 bits 24 to 31 */
277 /* Set the MSB of the register value */
279 /* Write value in r3 back to PX_AUX */
282 /* Get the address to jump to in r3*/
283 lis r3, CONFIG_SYS_DIAG_ADDR@h
284 ori r3, r3, CONFIG_SYS_DIAG_ADDR@l
286 /* Load the LR with the branch address */
289 /* Branch to diagnostic */
295 /* bl l2cache_enable */
297 /* run 1st part of board init code (from Flash) */
301 /* NOTREACHED - board_init_f() does not return */
303 .globl invalidate_bats
307 /* invalidate BATs */
334 * Set up bats needed early on - this is usually the BAT for the
335 * stack-in-cache, the Flash, and CCSR space
340 lis r4, CONFIG_SYS_IBAT3L@h
341 ori r4, r4, CONFIG_SYS_IBAT3L@l
342 lis r3, CONFIG_SYS_IBAT3U@h
343 ori r3, r3, CONFIG_SYS_IBAT3U@l
349 lis r4, CONFIG_SYS_DBAT3L@h
350 ori r4, r4, CONFIG_SYS_DBAT3L@l
351 lis r3, CONFIG_SYS_DBAT3U@h
352 ori r3, r3, CONFIG_SYS_DBAT3U@l
358 lis r4, CONFIG_SYS_IBAT5L@h
359 ori r4, r4, CONFIG_SYS_IBAT5L@l
360 lis r3, CONFIG_SYS_IBAT5U@h
361 ori r3, r3, CONFIG_SYS_IBAT5U@l
367 lis r4, CONFIG_SYS_DBAT5L@h
368 ori r4, r4, CONFIG_SYS_DBAT5L@l
369 lis r3, CONFIG_SYS_DBAT5U@h
370 ori r3, r3, CONFIG_SYS_DBAT5U@l
376 lis r4, CONFIG_SYS_IBAT6L_EARLY@h
377 ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
378 lis r3, CONFIG_SYS_IBAT6U_EARLY@h
379 ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
385 lis r4, CONFIG_SYS_DBAT6L_EARLY@h
386 ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
387 lis r3, CONFIG_SYS_DBAT6U_EARLY@h
388 ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
393 #if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
395 lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
396 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
397 lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
398 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
404 lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
405 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
406 lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
407 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
427 .globl disable_addr_trans
429 /* disable address translation */
432 andi. r0, r3, (MSR_IR | MSR_DR)
440 * This code finishes saving the registers to the exception frame
441 * and jumps to the appropriate handler for the exception.
442 * Register r21 is pointer into trap frame, r1 has new stack pointer.
444 .globl transfer_to_handler
455 andi. r24,r23,0x3f00 /* get vector offset */
459 mtspr SPRG2,r22 /* r1 is now kernel sp */
460 lwz r24,0(r23) /* virtual address of handler */
461 lwz r23,4(r23) /* where to go when done */
466 rfi /* jump to handler, enable MMU */
469 mfmsr r28 /* Disable interrupts */
473 SYNC /* Some chip revs need this... */
488 lwz r2,_NIP(r1) /* Restore environment */
515 * Description: Input 8 bits
524 * Description: Output 8 bits
533 * Description: Output 16 bits
542 * Description: Byte reverse and output 16 bits
551 * Description: Output 32 bits
560 * Description: Byte reverse and output 32 bits
569 * Description: Input 16 bits
578 * Description: Input 16 bits and byte reverse
587 * Description: Input 32 bits
596 * Description: Input 32 bits and byte reverse
604 * void relocate_code (addr_sp, gd, addr_moni)
606 * This "function" does not return, instead it continues in RAM
607 * after relocating the monitor code.
611 * r5 = length in bytes
617 mr r1, r3 /* Set new stack pointer */
618 mr r9, r4 /* Save copy of Global Data pointer */
619 mr r10, r5 /* Save copy of Destination Address */
622 mr r3, r5 /* Destination Address */
623 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
624 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
625 lwz r5, GOT(__init_end)
627 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
632 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
638 /* First our own GOT */
640 /* then the one used by the C code */
649 beq cr1,4f /* In place copy is not necessary */
650 beq 7f /* Protect against 0 count */
668 * Now flush the cache: note that we must start from a cache aligned
669 * address. Otherwise we might miss one cache line.
673 beq 7f /* Always flush prefetch queue in any case */
681 sync /* Wait for all dcbst to complete on bus */
687 7: sync /* Wait for all icbi to complete on bus */
691 * We are done. Do not return, instead branch to second part of board
692 * initialization, now running from RAM.
694 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
700 * Relocation Function, r12 point to got2+0x8000
702 * Adjust got2 pointers, no need to check for 0, this code
703 * already puts a few entries in the table.
705 li r0,__got2_entries@sectoff@l
706 la r3,GOT(_GOT2_TABLE_)
707 lwz r11,GOT(_GOT2_TABLE_)
719 * Now adjust the fixups and the pointers to the fixups
720 * in case we need to move ourselves again.
722 li r0,__fixup_entries@sectoff@l
723 lwz r3,GOT(_FIXUP_TABLE_)
737 * Now clear BSS segment
739 lwz r3,GOT(__bss_start)
752 mr r3, r9 /* Init Date pointer */
753 mr r4, r10 /* Destination Address */
756 /* not reached - end relocate_code */
757 /*-----------------------------------------------------------------------*/
760 * Copy exception vector code to low memory
763 * r7: source address, r8: end address, r9: target address
767 mflr r4 /* save link register */
770 lwz r8, GOT(_end_of_vectors)
772 li r9, 0x100 /* reset vector always at 0x100 */
775 bgelr /* return if r7>=r8 - just in case */
785 * relocate `hdlr' and `int_return' entries
787 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
788 li r8, Alignment - _start + EXC_OFF_SYS_RESET
791 addi r7, r7, 0x100 /* next exception vector */
795 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
798 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
801 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
802 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
805 addi r7, r7, 0x100 /* next exception vector */
809 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
810 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
813 addi r7, r7, 0x100 /* next exception vector */
817 /* enable execptions from RAM vectors */
821 ori r7,r7,MSR_ME /* Enable Machine Check */
824 mtlr r4 /* restore link register */
827 .globl enable_ext_addr
830 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
831 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
837 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
840 /* Special sequence needed to update CCSRBAR itself */
841 lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
842 ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
844 lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
845 ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
847 li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
849 stw r5, 0(r4) /* Store physical value of CCSR */
852 lis r5, CONFIG_SYS_TEXT_BASE@h
853 ori r5,r5,CONFIG_SYS_TEXT_BASE@l
857 /* Use VA of CCSR to do read */
858 lis r3, CONFIG_SYS_CCSRBAR@h
859 lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
865 #ifdef CONFIG_SYS_INIT_RAM_LOCK
867 /* Allocate Initial RAM in data cache.
869 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
870 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
871 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
872 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
879 /* Lock the data cache */
888 /* Lock the first way of the data cache */
891 #if defined(CONFIG_ALTIVEC)
901 .globl unlock_ram_in_cache
903 /* invalidate the INIT_RAM section */
904 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
905 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
906 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
907 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
912 sync /* Wait for all icbi to complete on bus */
915 /* Unlock the data cache and invalidate it */
927 /* Unlock the first way of the data cache */
931 #ifdef CONFIG_ALTIVEC