2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
13 * written or collected and sometimes rewritten by
14 * Magnus Damm <damm@bitsmart.com>
16 * minor modifications by
17 * Wolfgang Denk <wd@denx.de>
26 #include <asm/cache.h>
27 #include <linux/compiler.h>
30 #if defined(CONFIG_OF_LIBFDT)
32 #include <fdt_support.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 static char *cpu_warning = "\n " \
38 "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
40 static int check_CPU(long clock, uint pvr, uint immr)
44 immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
51 /* the highest 16 bits should be 0x0050 for a 860 */
53 if ((pvr >> 16) != 0x0050)
57 in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
62 * Some boards use sockets so different CPUs can be used.
63 * We have to check chip version in run time.
66 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
67 case 0x08010004: /* Rev. A.0 */
70 case 0x08000003: /* Rev. 0.3 */
74 "PC866x"; /* Unknown chip from MPC866 family */
77 pre = 'M'; mid = suf = ""; m = 1;
79 id_str = "PC885"; /* 870/875/880/885 */
88 id_str = "PC86x"; /* Unknown 86x chip */
90 printf("%c%s%sZPnn%s", pre, id_str, mid, suf);
92 printf("unknown M%s (0x%08x)", id_str, k);
94 printf(" at %s MHz: ", strmhz(buf, clock));
96 print_size(checkicache(), " I-Cache ");
97 print_size(checkdcache(), " D-Cache");
99 /* do we have a FEC (860T/P or 852/859/866/885)? */
101 out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
102 if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
103 printf(" FEC present");
113 /* ------------------------------------------------------------------------- */
117 ulong clock = gd->cpu_clk;
118 uint immr = get_immr(0); /* Return full IMMR contents */
119 uint pvr = get_pvr();
123 return check_CPU(clock, pvr, immr);
126 /* ------------------------------------------------------------------------- */
129 int checkicache(void)
131 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
132 memctl8xx_t __iomem *memctl = &immap->im_memctl;
133 u32 cacheon = rd_ic_cst() & IDC_ENABLED;
134 /* probe in flash memoryarea */
135 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
139 wr_ic_cst(IDC_UNALL);
140 wr_ic_cst(IDC_INVALL);
141 wr_ic_cst(IDC_DISABLE);
142 __asm__ volatile ("isync");
144 while (!((m = rd_ic_cst()) & IDC_CERR2)) {
146 wr_ic_cst(IDC_LDLCK);
147 __asm__ volatile ("isync");
150 k += 0x10; /* the number of bytes in a cacheline */
153 wr_ic_cst(IDC_UNALL);
154 wr_ic_cst(IDC_INVALL);
157 wr_ic_cst(IDC_ENABLE);
159 wr_ic_cst(IDC_DISABLE);
161 __asm__ volatile ("isync");
166 /* ------------------------------------------------------------------------- */
168 /* call with cache disabled */
170 int checkdcache(void)
172 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
173 memctl8xx_t __iomem *memctl = &immap->im_memctl;
174 u32 cacheon = rd_dc_cst() & IDC_ENABLED;
175 /* probe in flash memoryarea */
176 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
180 wr_dc_cst(IDC_UNALL);
181 wr_dc_cst(IDC_INVALL);
182 wr_dc_cst(IDC_DISABLE);
184 while (!((m = rd_dc_cst()) & IDC_CERR2)) {
186 wr_dc_cst(IDC_LDLCK);
188 k += 0x10; /* the number of bytes in a cacheline */
191 wr_dc_cst(IDC_UNALL);
192 wr_dc_cst(IDC_INVALL);
195 wr_dc_cst(IDC_ENABLE);
197 wr_dc_cst(IDC_DISABLE);
202 /* ------------------------------------------------------------------------- */
204 void upmconfig(uint upm, uint *table, uint size)
208 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
209 memctl8xx_t __iomem *memctl = &immap->im_memctl;
211 for (i = 0; i < size; i++) {
212 out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */
213 out_be32(&memctl->memc_mcr, addr | upm); /* (16-16) */
218 /* ------------------------------------------------------------------------- */
220 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
224 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
226 /* Checkstop Reset enable */
227 setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR);
229 /* Interrupts and MMU off */
230 __asm__ volatile ("mtspr 81, 0");
231 __asm__ volatile ("mfmsr %0" : "=r" (msr));
234 __asm__ volatile ("mtmsr %0" : : "r" (msr));
237 * Trying to execute the next instruction at a non-existing address
238 * should cause a machine check, resulting in reset
240 #ifdef CONFIG_SYS_RESET_ADDRESS
241 addr = CONFIG_SYS_RESET_ADDRESS;
244 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
245 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
246 * Better pick an address known to be invalid on your system and assign
247 * it to CONFIG_SYS_RESET_ADDRESS.
248 * "(ulong)-1" used to be a good choice for many systems...
250 addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
252 ((void (*)(void)) addr)();
256 /* ------------------------------------------------------------------------- */
259 * Get timebase clock frequency (like cpu_clk in Hz)
261 * See sections 14.2 and 14.6 of the User's Manual
263 unsigned long get_tbclk(void)
265 uint immr = get_immr(0); /* Return full IMMR contents */
266 immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
267 ulong oscclk, factor, pll;
269 if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
270 return gd->cpu_clk / 16;
272 pll = in_be32(&immap->im_clkrst.car_plprcr);
274 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
277 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
278 * factor is calculated as follows:
283 * factor = -----------------
287 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
288 (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
290 oscclk = gd->cpu_clk / factor;
292 if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
299 /* ------------------------------------------------------------------------- */
301 #if defined(CONFIG_WATCHDOG)
302 void watchdog_reset(void)
304 int re_enable = disable_interrupts();
306 reset_8xx_watchdog((immap_t __iomem *)CONFIG_SYS_IMMR);
310 #endif /* CONFIG_WATCHDOG */
312 #if defined(CONFIG_WATCHDOG)
314 void reset_8xx_watchdog(immap_t __iomem *immr)
317 * All other boards use the MPC8xx Internal Watchdog
319 out_be16(&immr->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */
320 out_be16(&immr->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */
322 #endif /* CONFIG_WATCHDOG */
325 * Initializes on-chip ethernet controllers.
326 * to override, implement board_eth_init()
328 int cpu_eth_init(bd_t *bis)
330 #if defined(CONFIG_MPC8XX_FEC)