2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
13 * written or collected and sometimes rewritten by
14 * Magnus Damm <damm@bitsmart.com>
16 * minor modifications by
17 * Wolfgang Denk <wd@denx.de>
26 #include <asm/cache.h>
27 #include <linux/compiler.h>
30 #if defined(CONFIG_OF_LIBFDT)
32 #include <fdt_support.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 static char *cpu_warning = "\n " \
38 "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
40 #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
41 !defined(CONFIG_MPC862))
43 static int check_CPU (long clock, uint pvr, uint immr)
46 # if defined(CONFIG_MPC855)
48 # elif defined(CONFIG_MPC860P)
53 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
60 /* the highest 16 bits should be 0x0050 for a 860 */
62 if ((pvr >> 16) != 0x0050)
66 immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
71 * Some boards use sockets so different CPUs can be used.
72 * We have to check chip version in run time.
75 case 0x00020001: pre = 'P'; break;
76 case 0x00030001: break;
77 case 0x00120003: suf = "A"; break;
78 case 0x00130003: suf = "A3"; break;
80 case 0x00200004: suf = "B"; break;
82 case 0x00300004: suf = "C"; break;
83 case 0x00310004: suf = "C1"; m = 1; break;
85 case 0x00200064: mid = "SR"; suf = "B"; break;
86 case 0x00300065: mid = "SR"; suf = "C"; break;
87 case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
88 case 0x05010000: suf = "D3"; m = 1; break;
89 case 0x05020000: suf = "D4"; m = 1; break;
90 /* this value is not documented anywhere */
91 case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
92 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
93 case 0x08010004: /* Rev. A.0 */
96 case 0x08000003: /* Rev. 0.3 */
100 # if defined(CONFIG_MPC859T)
103 "PC866x"; /* Unknown chip from MPC866 family */
106 case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
108 id_str = "PC885"; /* 870/875/880/885 */
111 default: suf = NULL; break;
115 id_str = "PC86x"; /* Unknown 86x chip */
117 printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
119 printf ("unknown M%s (0x%08x)", id_str, k);
122 #if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX)
123 printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
125 CONFIG_SYS_8xx_CPUCLK_MIN / 1000000,
126 ((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
127 CONFIG_SYS_8xx_CPUCLK_MAX / 1000000,
128 ((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
131 printf (" at %s MHz: ", strmhz (buf, clock));
133 print_size(checkicache(), " I-Cache ");
134 print_size(checkdcache(), " D-Cache");
136 /* do we have a FEC (860T/P or 852/859/866/885)? */
138 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
139 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
140 printf (" FEC present");
150 if(clock != measure_gclk()) {
151 printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
158 #elif defined(CONFIG_MPC862)
160 static int check_CPU (long clock, uint pvr, uint immr)
162 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
166 __maybe_unused char *mid = "xx";
169 /* the highest 16 bits should be 0x0050 for a 8xx */
171 if ((pvr >> 16) != 0x0050)
175 immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
180 /* this value is not documented anywhere */
181 case 0x06000000: mid = "P"; suf = "0"; break;
182 case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
183 case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
184 default: suf = NULL; break;
187 #ifndef CONFIG_MPC857
189 printf ("%cPC862%sZPnn%s", pre, mid, suf);
191 printf ("unknown MPC862 (0x%08x)", k);
194 printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
196 printf ("unknown MPC857 (0x%08x)", k);
199 printf(" at %s MHz: ", strmhz(buf, clock));
201 print_size(checkicache(), " I-Cache ");
202 print_size(checkdcache(), " D-Cache");
204 /* lets check and see if we're running on a 862T (or P?) */
206 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
207 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
208 printf (" FEC present");
220 #elif defined(CONFIG_MPC823)
222 static int check_CPU (long clock, uint pvr, uint immr)
224 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
229 /* the highest 16 bits should be 0x0050 for a 8xx */
231 if ((pvr >> 16) != 0x0050)
235 in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
240 case 0x20000000: suf = "0"; break;
241 case 0x20010000: suf = "0.1"; break;
242 case 0x20020000: suf = "Z2/3"; break;
243 case 0x20020001: suf = "Z3"; break;
244 case 0x21000000: suf = "A"; break;
245 case 0x21010000: suf = "B"; m = 1; break;
246 case 0x21010001: suf = "B2"; m = 1; break;
248 case 0x24010000: suf = NULL;
249 puts ("PPC823EZTnnB2");
254 printf ("unknown MPC823 (0x%08x)", k);
258 printf ("PPC823ZTnn%s", suf);
260 printf(" at %s MHz: ", strmhz(buf, clock));
262 print_size(checkicache(), " I-Cache ");
263 print_size(checkdcache(), " D-Cache");
265 /* lets check and see if we're running on a 860T (or P?) */
267 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
268 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
269 puts (" FEC present");
281 #elif defined(CONFIG_MPC850)
283 static int check_CPU (long clock, uint pvr, uint immr)
285 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
289 /* the highest 16 bits should be 0x0050 for a 8xx */
291 if ((pvr >> 16) != 0x0050)
295 immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
300 printf ("XPC850xxZT");
303 printf ("XPC850xxZTA");
306 printf ("XPC850xxZTB");
310 printf ("XPC850xxZTC");
314 printf ("unknown MPC850 (0x%08x)", k);
316 printf(" at %s MHz: ", strmhz(buf, clock));
318 print_size(checkicache(), " I-Cache ");
319 print_size(checkdcache(), " D-Cache");
321 /* lets check and see if we're running on a 850T (or P?) */
323 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
324 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
325 printf (" FEC present");
339 /* ------------------------------------------------------------------------- */
343 ulong clock = gd->cpu_clk;
344 uint immr = get_immr (0); /* Return full IMMR contents */
345 uint pvr = get_pvr ();
349 /* 850 has PARTNUM 20 */
350 /* 801 has PARTNUM 10 */
351 return check_CPU (clock, pvr, immr);
354 /* ------------------------------------------------------------------------- */
356 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
357 /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
359 int checkicache (void)
361 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
362 volatile memctl8xx_t *memctl = &immap->im_memctl;
363 u32 cacheon = rd_ic_cst () & IDC_ENABLED;
366 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
368 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
373 wr_ic_cst (IDC_UNALL);
374 wr_ic_cst (IDC_INVALL);
375 wr_ic_cst (IDC_DISABLE);
376 __asm__ volatile ("isync");
378 while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
380 wr_ic_cst (IDC_LDLCK);
381 __asm__ volatile ("isync");
384 k += 0x10; /* the number of bytes in a cacheline */
387 wr_ic_cst (IDC_UNALL);
388 wr_ic_cst (IDC_INVALL);
391 wr_ic_cst (IDC_ENABLE);
393 wr_ic_cst (IDC_DISABLE);
395 __asm__ volatile ("isync");
400 /* ------------------------------------------------------------------------- */
402 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
403 /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
404 /* call with cache disabled */
406 int checkdcache (void)
408 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
409 volatile memctl8xx_t *memctl = &immap->im_memctl;
410 u32 cacheon = rd_dc_cst () & IDC_ENABLED;
413 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
415 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
420 wr_dc_cst (IDC_UNALL);
421 wr_dc_cst (IDC_INVALL);
422 wr_dc_cst (IDC_DISABLE);
424 while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
426 wr_dc_cst (IDC_LDLCK);
428 k += 0x10; /* the number of bytes in a cacheline */
431 wr_dc_cst (IDC_UNALL);
432 wr_dc_cst (IDC_INVALL);
435 wr_dc_cst (IDC_ENABLE);
437 wr_dc_cst (IDC_DISABLE);
442 /* ------------------------------------------------------------------------- */
444 void upmconfig (uint upm, uint * table, uint size)
448 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
449 volatile memctl8xx_t *memctl = &immap->im_memctl;
451 for (i = 0; i < size; i++) {
452 memctl->memc_mdr = table[i]; /* (16-15) */
453 memctl->memc_mcr = addr | upm; /* (16-16) */
458 /* ------------------------------------------------------------------------- */
462 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
466 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
468 immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
470 /* Interrupts and MMU off */
471 __asm__ volatile ("mtspr 81, 0");
472 __asm__ volatile ("mfmsr %0":"=r" (msr));
475 __asm__ volatile ("mtmsr %0"::"r" (msr));
478 * Trying to execute the next instruction at a non-existing address
479 * should cause a machine check, resulting in reset
481 #ifdef CONFIG_SYS_RESET_ADDRESS
482 addr = CONFIG_SYS_RESET_ADDRESS;
485 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
486 * - sizeof (ulong) is usually a valid address. Better pick an address
487 * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
488 * "(ulong)-1" used to be a good choice for many systems...
490 addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
492 ((void (*)(void)) addr) ();
496 #else /* CONFIG_LWMON */
499 * On the LWMON board, the MCLR reset input of the PIC's on the board
500 * uses a 47K/1n RC combination which has a 47us time constant. The
501 * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us
502 * and thus too short to reset the external hardware. So we use the
503 * watchdog to reset the board.
505 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
507 /* prevent triggering the watchdog */
508 disable_interrupts ();
510 /* make sure the watchdog is running */
511 reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
513 /* wait for watchdog reset */
520 #endif /* CONFIG_LWMON */
522 /* ------------------------------------------------------------------------- */
525 * Get timebase clock frequency (like cpu_clk in Hz)
527 * See sections 14.2 and 14.6 of the User's Manual
529 unsigned long get_tbclk (void)
531 uint immr = get_immr (0); /* Return full IMMR contents */
532 volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
533 ulong oscclk, factor, pll;
535 if (immap->im_clkrst.car_sccr & SCCR_TBS) {
536 return (gd->cpu_clk / 16);
539 pll = immap->im_clkrst.car_plprcr;
541 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
544 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
545 * factor is calculated as follows:
550 * factor = -----------------
553 * For older chips, it's just MF field of PLPRCR plus one.
555 if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
556 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
557 (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
559 factor = PLPRCR_val(MF)+1;
562 oscclk = gd->cpu_clk / factor;
564 if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
567 return (oscclk / 16);
570 /* ------------------------------------------------------------------------- */
572 #if defined(CONFIG_WATCHDOG)
573 void watchdog_reset (void)
575 int re_enable = disable_interrupts ();
577 reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
579 enable_interrupts ();
581 #endif /* CONFIG_WATCHDOG */
583 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)
585 void reset_8xx_watchdog (volatile immap_t * immr)
587 # if defined(CONFIG_LWMON)
589 * The LWMON board uses a MAX6301 Watchdog
590 * with the trigger pin connected to port PA.7
592 * (The old board version used a MAX706TESA Watchdog, which
593 * had to be handled exactly the same.)
595 # define WATCHDOG_BIT 0x0100
596 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
597 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
598 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
600 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
601 # elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
603 * The KUP4 boards uses a TPS3705 Watchdog
604 * with the trigger pin connected to port PA.5
606 # define WATCHDOG_BIT 0x0400
607 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
608 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
609 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
611 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
614 * All other boards use the MPC8xx Internal Watchdog
616 immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
617 immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
618 # endif /* CONFIG_LWMON */
620 #endif /* CONFIG_WATCHDOG */
623 * Initializes on-chip ethernet controllers.
624 * to override, implement board_eth_init()
626 int cpu_eth_init(bd_t *bis)
628 #if defined(SCC_ENET) && defined(CONFIG_CMD_NET)
631 #if defined(FEC_ENET)