3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <ppc_asm.tmpl>
10 #include <asm/cache.h>
12 #define CACHE_CMD_ENABLE 0x02000000
13 #define CACHE_CMD_DISABLE 0x04000000
14 #define CACHE_CMD_LOAD_LOCK 0x06000000
15 #define CACHE_CMD_UNLOCK_LINE 0x08000000
16 #define CACHE_CMD_UNLOCK_ALL 0x0A000000
17 #define CACHE_CMD_INVALIDATE 0x0C000000
18 #define SPEED_PLPRCR_WAIT_5CYC 150
19 #define _CACHE_ALIGN_SIZE 16
24 .globl plprcr_write_866
27 * void plprcr_write_866 (long plprcr)
28 * Write PLPRCR, including workaround for device errata SIU4 and SIU9.
32 mfspr r10, LR /* save the Link Register value */
34 /* turn instruction cache on (no MMU required for instructions)
36 lis r4, CACHE_CMD_ENABLE@h
37 ori r4, r4, CACHE_CMD_ENABLE@l
41 /* clear IC_CST error bits
50 /* calculate relocation offset
53 ori r4, r4, plprcr_here@l
56 /* calculate first address of this function
58 lis r6, plprcr_write_866@h
59 ori r6, r6, plprcr_write_866@l
62 /* calculate end address of this function
65 ori r7, r7, plprcr_end@l
68 /* load and lock code addresses
74 addi r5, r5, _CACHE_ALIGN_SIZE /* increment by one line */
76 lis r4, CACHE_CMD_LOAD_LOCK@h
77 ori r4, r4, CACHE_CMD_LOAD_LOCK@l
84 /* IC_CST error bits not evaluated
89 mfspr r4, IMMR /* read IMMR */
90 rlwinm r4, r4, 0, 0, 15 /* only high 16 bits count */
92 /* write sequence according to MPC866 Errata
97 lis r3, SPEED_PLPRCR_WAIT_5CYC@h
98 ori r3, r3, SPEED_PLPRCR_WAIT_5CYC@l
109 /* unlock instruction cache but leave it enabled
111 lis r4, CACHE_CMD_UNLOCK_ALL@h
112 ori r4, r4, CACHE_CMD_UNLOCK_ALL@l
116 mtspr LR, r10 /* restore original Link Register value */