3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <linux/compiler.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
35 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
37 #define PROFF_SMC PROFF_SMC1
38 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
40 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
42 #define PROFF_SMC PROFF_SMC2
43 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
45 #endif /* CONFIG_8xx_CONS_SMCx */
47 #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
49 #define PROFF_SCC PROFF_SCC1
50 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
52 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
54 #define PROFF_SCC PROFF_SCC2
55 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
57 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
59 #define PROFF_SCC PROFF_SCC3
60 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
62 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
64 #define PROFF_SCC PROFF_SCC4
65 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
67 #endif /* CONFIG_8xx_CONS_SCCx */
69 #if !defined(CONFIG_SYS_SMC_RXBUFLEN)
70 #define CONFIG_SYS_SMC_RXBUFLEN 1
71 #define CONFIG_SYS_MAXIDLE 0
73 #if !defined(CONFIG_SYS_MAXIDLE)
74 #error "you must define CONFIG_SYS_MAXIDLE"
78 typedef volatile struct serialbuffer {
79 cbd_t rxbd; /* Rx BD */
80 cbd_t txbd; /* Tx BD */
81 uint rxindex; /* index for next character to read */
82 volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
83 volatile uchar txbuf; /* tx buffers */
86 static void serial_setdivisor(volatile cpm8xx_t *cp)
88 int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
90 if(divisor/16>0x1000) {
91 /* bad divisor, assume 50MHz clock and 9600 baud */
92 divisor=(50*1000*1000 + 8*9600)/16/9600;
95 #ifdef CONFIG_SYS_BRGCLK_PRESCALE
96 divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
100 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
102 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
106 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
109 * Minimal serial functions needed to use one of the SMC ports
110 * as serial console interface.
113 static void smc_setbrg (void)
115 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
116 volatile cpm8xx_t *cp = &(im->im_cpm);
118 /* Set up the baud rate generator.
119 * See 8xx_io/commproc.c for details.
124 cp->cp_simode = 0x00000000;
126 serial_setdivisor(cp);
129 static int smc_init (void)
131 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
133 volatile smc_uart_t *up;
134 volatile cpm8xx_t *cp = &(im->im_cpm);
135 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
136 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
139 volatile serialbuffer_t *rtx;
141 /* initialize pointers to SMC */
143 sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
144 up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
145 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
146 up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase];
148 /* Disable relocation */
152 /* Disable transmitter/receiver. */
153 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
156 im->im_siu_conf.sc_sdcr = 1;
158 /* clear error conditions */
159 #ifdef CONFIG_SYS_SDSR
160 im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
162 im->im_sdma.sdma_sdsr = 0x83;
165 /* clear SDMA interrupt mask */
166 #ifdef CONFIG_SYS_SDMR
167 im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
169 im->im_sdma.sdma_sdmr = 0x00;
172 #if defined(CONFIG_8xx_CONS_SMC1)
173 /* Use Port B for SMC1 instead of other functions. */
174 cp->cp_pbpar |= 0x000000c0;
175 cp->cp_pbdir &= ~0x000000c0;
176 cp->cp_pbodr &= ~0x000000c0;
177 #else /* CONFIG_8xx_CONS_SMC2 */
178 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
179 /* Use Port A for SMC2 instead of other functions. */
180 ip->iop_papar |= 0x00c0;
181 ip->iop_padir &= ~0x00c0;
182 ip->iop_paodr &= ~0x00c0;
183 # else /* must be a 860 then */
184 /* Use Port B for SMC2 instead of other functions.
186 cp->cp_pbpar |= 0x00000c00;
187 cp->cp_pbdir &= ~0x00000c00;
188 cp->cp_pbodr &= ~0x00000c00;
192 #if defined(CONFIG_FADS) || defined(CONFIG_ADS)
194 #if defined(CONFIG_8xx_CONS_SMC1)
195 *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
197 *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
199 #endif /* CONFIG_FADS */
201 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
202 /* Enable Monitor Port Transceiver */
203 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
204 #endif /* CONFIG_RPXLITE */
206 /* Set the physical address of the host memory buffers in
207 * the buffer descriptors.
210 #ifdef CONFIG_SYS_ALLOC_DPRAM
212 * size of struct serialbuffer with bd rx/tx, buffer rx/tx and rx index
214 dpaddr = dpram_alloc_align((sizeof(serialbuffer_t)), 8);
216 dpaddr = CPM_SERIAL_BASE ;
219 rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
220 /* Allocate space for two buffer descriptors in the DP ram.
221 * For now, this address seems OK, but it may have to
222 * change with newer versions of the firmware.
223 * damm: allocating space after the two buffers for rx/tx data
226 rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
227 rtx->rxbd.cbd_sc = 0;
229 rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
230 rtx->txbd.cbd_sc = 0;
232 /* Set up the uart parameters in the parameter ram. */
233 up->smc_rbase = dpaddr;
234 up->smc_tbase = dpaddr+sizeof(cbd_t);
235 up->smc_rfcr = SMC_EB;
236 up->smc_tfcr = SMC_EB;
237 #if defined (CONFIG_SYS_SMC_UCODE_PATCH)
238 up->smc_rbptr = up->smc_rbase;
239 up->smc_tbptr = up->smc_tbase;
244 #if defined(CONFIG_MBX)
246 #endif /* CONFIG_MBX */
248 /* Set UART mode, 8 bit, no parity, one stop.
249 * Enable receive and transmit.
251 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
253 /* Mask all interrupts and remove anything pending.
258 #ifdef CONFIG_SYS_SPC1920_SMC1_CLK4
259 /* clock source is PLD */
261 /* set freq to 19200 Baud */
262 *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3;
263 /* configure clk4 as input */
264 im->im_ioport.iop_pdpar |= 0x800;
265 im->im_ioport.iop_pddir &= ~0x800;
267 cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000);
269 /* Set up the baud rate generator */
273 /* Make the first buffer the only buffer. */
274 rtx->txbd.cbd_sc |= BD_SC_WRAP;
275 rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
277 /* single/multi character receive. */
278 up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
279 up->smc_maxidl = CONFIG_SYS_MAXIDLE;
282 /* Initialize Tx/Rx parameters. */
283 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
286 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
288 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
291 /* Enable transmitter/receiver. */
292 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
298 smc_putc(const char c)
300 volatile smc_uart_t *up;
301 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
302 volatile cpm8xx_t *cpmp = &(im->im_cpm);
303 volatile serialbuffer_t *rtx;
305 #ifdef CONFIG_MODEM_SUPPORT
313 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
314 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
315 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
318 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
320 /* Wait for last character to go. */
322 rtx->txbd.cbd_datlen = 1;
323 rtx->txbd.cbd_sc |= BD_SC_READY;
326 while (rtx->txbd.cbd_sc & BD_SC_READY) {
333 smc_puts (const char *s)
343 volatile smc_uart_t *up;
344 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
345 volatile cpm8xx_t *cpmp = &(im->im_cpm);
346 volatile serialbuffer_t *rtx;
349 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
350 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
351 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
353 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
355 /* Wait for character to show up. */
356 while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
359 /* the characters are read one by one,
360 * use the rxindex to know the next char to deliver
362 c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
365 /* check if all char are readout, then make prepare for next receive */
366 if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
368 rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
376 volatile smc_uart_t *up;
377 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
378 volatile cpm8xx_t *cpmp = &(im->im_cpm);
379 volatile serialbuffer_t *rtx;
381 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
382 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
383 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
386 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
388 return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
391 struct serial_device serial_smc_device =
404 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
406 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
407 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
412 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
413 volatile cpm8xx_t *cp = &(im->im_cpm);
415 /* Set up the baud rate generator.
416 * See 8xx_io/commproc.c for details.
421 cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
423 serial_setdivisor(cp);
426 static int scc_init (void)
428 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
430 volatile scc_uart_t *up;
431 volatile cbd_t *tbdf, *rbdf;
432 volatile cpm8xx_t *cp = &(im->im_cpm);
434 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
435 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
438 /* initialize pointers to SCC */
440 sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
441 up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
443 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
444 { /* Disable Ethernet, enable Serial */
448 c &= ~0x40; /* enable COM3 */
449 c |= 0x80; /* disable Ethernet */
453 cp->cp_pbpar |= 0x2000;
454 cp->cp_pbdat |= 0x2000;
455 cp->cp_pbdir |= 0x2000;
457 #endif /* CONFIG_LWMON */
459 /* Disable transmitter/receiver. */
460 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
462 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
464 * The MPC850 has SCC3 on Port B
466 cp->cp_pbpar |= 0x06;
467 cp->cp_pbdir &= ~0x06;
468 cp->cp_pbodr &= ~0x06;
470 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
472 * Standard configuration for SCC's is on Part A
474 ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
475 ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
476 ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
479 * The IP860 has SCC3 and SCC4 on Port D
481 ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
484 /* Allocate space for two buffer descriptors in the DP ram. */
486 #ifdef CONFIG_SYS_ALLOC_DPRAM
487 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
489 dpaddr = CPM_SERIAL2_BASE ;
493 im->im_siu_conf.sc_sdcr = 0x0001;
495 /* Set the physical address of the host memory buffers in
496 * the buffer descriptors.
499 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
500 rbdf->cbd_bufaddr = (uint) (rbdf+2);
503 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
506 /* Set up the baud rate generator. */
509 /* Set up the uart parameters in the parameter ram. */
510 up->scc_genscc.scc_rbase = dpaddr;
511 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
513 /* Initialize Tx/Rx parameters. */
514 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
516 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
518 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
521 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
522 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
524 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
525 up->scc_maxidl = 0; /* disable max idle */
526 up->scc_brkcr = 1; /* send one break character on stop TX */
534 up->scc_char1 = 0x8000;
535 up->scc_char2 = 0x8000;
536 up->scc_char3 = 0x8000;
537 up->scc_char4 = 0x8000;
538 up->scc_char5 = 0x8000;
539 up->scc_char6 = 0x8000;
540 up->scc_char7 = 0x8000;
541 up->scc_char8 = 0x8000;
542 up->scc_rccm = 0xc0ff;
544 /* Set low latency / small fifo. */
545 sp->scc_gsmrh = SCC_GSMRH_RFW;
547 /* Set SCC(x) clock mode to 16x
548 * See 8xx_io/commproc.c for details.
553 /* Set UART mode, clock divider 16 on Tx and Rx */
554 sp->scc_gsmrl &= ~0xF;
556 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
559 sp->scc_psmr |= SCU_PSMR_CL;
561 /* Mask all interrupts and remove anything pending. */
563 sp->scc_scce = 0xffff;
564 sp->scc_dsr = 0x7e7e;
565 sp->scc_psmr = 0x3000;
567 /* Make the first buffer the only buffer. */
568 tbdf->cbd_sc |= BD_SC_WRAP;
569 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
571 /* Enable transmitter/receiver. */
572 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
578 scc_putc(const char c)
580 volatile cbd_t *tbdf;
582 volatile scc_uart_t *up;
583 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
584 volatile cpm8xx_t *cpmp = &(im->im_cpm);
586 #ifdef CONFIG_MODEM_SUPPORT
594 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
596 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
598 /* Wait for last character to go. */
600 buf = (char *)tbdf->cbd_bufaddr;
603 tbdf->cbd_datlen = 1;
604 tbdf->cbd_sc |= BD_SC_READY;
607 while (tbdf->cbd_sc & BD_SC_READY) {
614 scc_puts (const char *s)
624 volatile cbd_t *rbdf;
625 volatile unsigned char *buf;
626 volatile scc_uart_t *up;
627 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
628 volatile cpm8xx_t *cpmp = &(im->im_cpm);
631 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
633 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
635 /* Wait for character to show up. */
636 buf = (unsigned char *)rbdf->cbd_bufaddr;
638 while (rbdf->cbd_sc & BD_SC_EMPTY)
642 rbdf->cbd_sc |= BD_SC_EMPTY;
650 volatile cbd_t *rbdf;
651 volatile scc_uart_t *up;
652 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
653 volatile cpm8xx_t *cpmp = &(im->im_cpm);
655 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
657 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
659 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
662 struct serial_device serial_scc_device =
675 #endif /* CONFIG_8xx_CONS_SCCx */
677 __weak struct serial_device *default_serial_console(void)
679 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
680 return &serial_smc_device;
682 return &serial_scc_device;
686 #ifdef CONFIG_MODEM_SUPPORT
687 void disable_putc(void)
692 void enable_putc(void)
698 #if defined(CONFIG_CMD_KGDB)
701 kgdb_serial_init(void)
705 if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
707 #if defined(CONFIG_8xx_CONS_SMC1)
709 #elif defined(CONFIG_8xx_CONS_SMC2)
713 else if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
715 #if defined(CONFIG_8xx_CONS_SCC1)
717 #elif defined(CONFIG_8xx_CONS_SCC2)
719 #elif defined(CONFIG_8xx_CONS_SCC3)
721 #elif defined(CONFIG_8xx_CONS_SCC4)
728 serial_printf("[on %s%d] ", default_serial_console()->ctlr, i);
739 putDebugStr (const char *str)
747 return serial_getc();
751 kgdb_interruptible (int yes)
757 #endif /* CONFIG_8xx_CONS_NONE */