3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/compiler.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
19 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
21 #define PROFF_SMC PROFF_SMC1
22 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
24 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
26 #define PROFF_SMC PROFF_SMC2
27 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
29 #endif /* CONFIG_8xx_CONS_SMCx */
31 #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
33 #define PROFF_SCC PROFF_SCC1
34 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
36 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
38 #define PROFF_SCC PROFF_SCC2
39 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
41 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
43 #define PROFF_SCC PROFF_SCC3
44 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
46 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
48 #define PROFF_SCC PROFF_SCC4
49 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
51 #endif /* CONFIG_8xx_CONS_SCCx */
53 #if !defined(CONFIG_SYS_SMC_RXBUFLEN)
54 #define CONFIG_SYS_SMC_RXBUFLEN 1
55 #define CONFIG_SYS_MAXIDLE 0
57 #if !defined(CONFIG_SYS_MAXIDLE)
58 #error "you must define CONFIG_SYS_MAXIDLE"
62 typedef volatile struct serialbuffer {
63 cbd_t rxbd; /* Rx BD */
64 cbd_t txbd; /* Tx BD */
65 uint rxindex; /* index for next character to read */
66 volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
67 volatile uchar txbuf; /* tx buffers */
70 static void serial_setdivisor(volatile cpm8xx_t *cp)
72 int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
74 if(divisor/16>0x1000) {
75 /* bad divisor, assume 50MHz clock and 9600 baud */
76 divisor=(50*1000*1000 + 8*9600)/16/9600;
79 #ifdef CONFIG_SYS_BRGCLK_PRESCALE
80 divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
84 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
86 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
90 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
93 * Minimal serial functions needed to use one of the SMC ports
94 * as serial console interface.
97 static void smc_setbrg (void)
99 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
100 volatile cpm8xx_t *cp = &(im->im_cpm);
102 /* Set up the baud rate generator.
103 * See 8xx_io/commproc.c for details.
108 cp->cp_simode = 0x00000000;
110 serial_setdivisor(cp);
113 static int smc_init (void)
115 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
117 volatile smc_uart_t *up;
118 volatile cpm8xx_t *cp = &(im->im_cpm);
119 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
120 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
123 volatile serialbuffer_t *rtx;
125 /* initialize pointers to SMC */
127 sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
128 up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
129 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
130 up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase];
132 /* Disable relocation */
136 /* Disable transmitter/receiver. */
137 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
140 im->im_siu_conf.sc_sdcr = 1;
142 /* clear error conditions */
143 #ifdef CONFIG_SYS_SDSR
144 im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
146 im->im_sdma.sdma_sdsr = 0x83;
149 /* clear SDMA interrupt mask */
150 #ifdef CONFIG_SYS_SDMR
151 im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
153 im->im_sdma.sdma_sdmr = 0x00;
156 #if defined(CONFIG_8xx_CONS_SMC1)
157 /* Use Port B for SMC1 instead of other functions. */
158 cp->cp_pbpar |= 0x000000c0;
159 cp->cp_pbdir &= ~0x000000c0;
160 cp->cp_pbodr &= ~0x000000c0;
161 #else /* CONFIG_8xx_CONS_SMC2 */
162 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
163 /* Use Port A for SMC2 instead of other functions. */
164 ip->iop_papar |= 0x00c0;
165 ip->iop_padir &= ~0x00c0;
166 ip->iop_paodr &= ~0x00c0;
167 # else /* must be a 860 then */
168 /* Use Port B for SMC2 instead of other functions.
170 cp->cp_pbpar |= 0x00000c00;
171 cp->cp_pbdir &= ~0x00000c00;
172 cp->cp_pbodr &= ~0x00000c00;
176 #if defined(CONFIG_FADS)
178 #if defined(CONFIG_8xx_CONS_SMC1)
179 *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
181 *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
183 #endif /* CONFIG_FADS */
185 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
186 /* Enable Monitor Port Transceiver */
187 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
188 #endif /* CONFIG_RPXLITE */
190 /* Set the physical address of the host memory buffers in
191 * the buffer descriptors.
194 #ifdef CONFIG_SYS_ALLOC_DPRAM
196 * size of struct serialbuffer with bd rx/tx, buffer rx/tx and rx index
198 dpaddr = dpram_alloc_align((sizeof(serialbuffer_t)), 8);
200 dpaddr = CPM_SERIAL_BASE ;
203 rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
204 /* Allocate space for two buffer descriptors in the DP ram.
205 * For now, this address seems OK, but it may have to
206 * change with newer versions of the firmware.
207 * damm: allocating space after the two buffers for rx/tx data
210 rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
211 rtx->rxbd.cbd_sc = 0;
213 rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
214 rtx->txbd.cbd_sc = 0;
216 /* Set up the uart parameters in the parameter ram. */
217 up->smc_rbase = dpaddr;
218 up->smc_tbase = dpaddr+sizeof(cbd_t);
219 up->smc_rfcr = SMC_EB;
220 up->smc_tfcr = SMC_EB;
221 #if defined (CONFIG_SYS_SMC_UCODE_PATCH)
222 up->smc_rbptr = up->smc_rbase;
223 up->smc_tbptr = up->smc_tbase;
228 /* Set UART mode, 8 bit, no parity, one stop.
229 * Enable receive and transmit.
231 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
233 /* Mask all interrupts and remove anything pending.
238 #ifdef CONFIG_SYS_SPC1920_SMC1_CLK4
239 /* clock source is PLD */
241 /* set freq to 19200 Baud */
242 *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3;
243 /* configure clk4 as input */
244 im->im_ioport.iop_pdpar |= 0x800;
245 im->im_ioport.iop_pddir &= ~0x800;
247 cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000);
249 /* Set up the baud rate generator */
253 /* Make the first buffer the only buffer. */
254 rtx->txbd.cbd_sc |= BD_SC_WRAP;
255 rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
257 /* single/multi character receive. */
258 up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
259 up->smc_maxidl = CONFIG_SYS_MAXIDLE;
262 /* Initialize Tx/Rx parameters. */
263 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
266 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
268 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
271 /* Enable transmitter/receiver. */
272 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
278 smc_putc(const char c)
280 volatile smc_uart_t *up;
281 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
282 volatile cpm8xx_t *cpmp = &(im->im_cpm);
283 volatile serialbuffer_t *rtx;
285 #ifdef CONFIG_MODEM_SUPPORT
293 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
294 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
295 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
298 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
300 /* Wait for last character to go. */
302 rtx->txbd.cbd_datlen = 1;
303 rtx->txbd.cbd_sc |= BD_SC_READY;
306 while (rtx->txbd.cbd_sc & BD_SC_READY) {
313 smc_puts (const char *s)
323 volatile smc_uart_t *up;
324 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
325 volatile cpm8xx_t *cpmp = &(im->im_cpm);
326 volatile serialbuffer_t *rtx;
329 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
330 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
331 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
333 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
335 /* Wait for character to show up. */
336 while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
339 /* the characters are read one by one,
340 * use the rxindex to know the next char to deliver
342 c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
345 /* check if all char are readout, then make prepare for next receive */
346 if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
348 rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
356 volatile smc_uart_t *up;
357 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
358 volatile cpm8xx_t *cpmp = &(im->im_cpm);
359 volatile serialbuffer_t *rtx;
361 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
362 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
363 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
366 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
368 return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
371 struct serial_device serial_smc_device =
373 .name = "serial_smc",
376 .setbrg = smc_setbrg,
383 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
385 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
386 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
391 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
392 volatile cpm8xx_t *cp = &(im->im_cpm);
394 /* Set up the baud rate generator.
395 * See 8xx_io/commproc.c for details.
400 cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
402 serial_setdivisor(cp);
405 static int scc_init (void)
407 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
409 volatile scc_uart_t *up;
410 volatile cbd_t *tbdf, *rbdf;
411 volatile cpm8xx_t *cp = &(im->im_cpm);
413 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
414 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
417 /* initialize pointers to SCC */
419 sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
420 up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
422 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
423 { /* Disable Ethernet, enable Serial */
427 c &= ~0x40; /* enable COM3 */
428 c |= 0x80; /* disable Ethernet */
432 cp->cp_pbpar |= 0x2000;
433 cp->cp_pbdat |= 0x2000;
434 cp->cp_pbdir |= 0x2000;
436 #endif /* CONFIG_LWMON */
438 /* Disable transmitter/receiver. */
439 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
441 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
443 * The MPC850 has SCC3 on Port B
445 cp->cp_pbpar |= 0x06;
446 cp->cp_pbdir &= ~0x06;
447 cp->cp_pbodr &= ~0x06;
449 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
451 * Standard configuration for SCC's is on Part A
453 ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
454 ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
455 ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
458 * The IP860 has SCC3 and SCC4 on Port D
460 ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
463 /* Allocate space for two buffer descriptors in the DP ram. */
465 #ifdef CONFIG_SYS_ALLOC_DPRAM
466 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
468 dpaddr = CPM_SERIAL2_BASE ;
472 im->im_siu_conf.sc_sdcr = 0x0001;
474 /* Set the physical address of the host memory buffers in
475 * the buffer descriptors.
478 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
479 rbdf->cbd_bufaddr = (uint) (rbdf+2);
482 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
485 /* Set up the baud rate generator. */
488 /* Set up the uart parameters in the parameter ram. */
489 up->scc_genscc.scc_rbase = dpaddr;
490 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
492 /* Initialize Tx/Rx parameters. */
493 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
495 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
497 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
500 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
501 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
503 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
504 up->scc_maxidl = 0; /* disable max idle */
505 up->scc_brkcr = 1; /* send one break character on stop TX */
513 up->scc_char1 = 0x8000;
514 up->scc_char2 = 0x8000;
515 up->scc_char3 = 0x8000;
516 up->scc_char4 = 0x8000;
517 up->scc_char5 = 0x8000;
518 up->scc_char6 = 0x8000;
519 up->scc_char7 = 0x8000;
520 up->scc_char8 = 0x8000;
521 up->scc_rccm = 0xc0ff;
523 /* Set low latency / small fifo. */
524 sp->scc_gsmrh = SCC_GSMRH_RFW;
526 /* Set SCC(x) clock mode to 16x
527 * See 8xx_io/commproc.c for details.
532 /* Set UART mode, clock divider 16 on Tx and Rx */
533 sp->scc_gsmrl &= ~0xF;
535 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
538 sp->scc_psmr |= SCU_PSMR_CL;
540 /* Mask all interrupts and remove anything pending. */
542 sp->scc_scce = 0xffff;
543 sp->scc_dsr = 0x7e7e;
544 sp->scc_psmr = 0x3000;
546 /* Make the first buffer the only buffer. */
547 tbdf->cbd_sc |= BD_SC_WRAP;
548 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
550 /* Enable transmitter/receiver. */
551 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
557 scc_putc(const char c)
559 volatile cbd_t *tbdf;
561 volatile scc_uart_t *up;
562 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
563 volatile cpm8xx_t *cpmp = &(im->im_cpm);
565 #ifdef CONFIG_MODEM_SUPPORT
573 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
575 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
577 /* Wait for last character to go. */
579 buf = (char *)tbdf->cbd_bufaddr;
582 tbdf->cbd_datlen = 1;
583 tbdf->cbd_sc |= BD_SC_READY;
586 while (tbdf->cbd_sc & BD_SC_READY) {
593 scc_puts (const char *s)
603 volatile cbd_t *rbdf;
604 volatile unsigned char *buf;
605 volatile scc_uart_t *up;
606 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
607 volatile cpm8xx_t *cpmp = &(im->im_cpm);
610 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
612 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
614 /* Wait for character to show up. */
615 buf = (unsigned char *)rbdf->cbd_bufaddr;
617 while (rbdf->cbd_sc & BD_SC_EMPTY)
621 rbdf->cbd_sc |= BD_SC_EMPTY;
629 volatile cbd_t *rbdf;
630 volatile scc_uart_t *up;
631 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
632 volatile cpm8xx_t *cpmp = &(im->im_cpm);
634 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
636 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
638 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
641 struct serial_device serial_scc_device =
643 .name = "serial_scc",
646 .setbrg = scc_setbrg,
653 #endif /* CONFIG_8xx_CONS_SCCx */
655 __weak struct serial_device *default_serial_console(void)
657 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
658 return &serial_smc_device;
660 return &serial_scc_device;
664 void mpc8xx_serial_initialize(void)
666 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
667 serial_register(&serial_smc_device);
669 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
670 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
671 serial_register(&serial_scc_device);
675 #ifdef CONFIG_MODEM_SUPPORT
676 void disable_putc(void)
681 void enable_putc(void)
687 #if defined(CONFIG_CMD_KGDB)
690 kgdb_serial_init(void)
694 if (strcmp(default_serial_console()->name, "serial_smc") == 0)
696 #if defined(CONFIG_8xx_CONS_SMC1)
698 #elif defined(CONFIG_8xx_CONS_SMC2)
702 else if (strcmp(default_serial_console()->name, "serial_scc") == 0)
704 #if defined(CONFIG_8xx_CONS_SCC1)
706 #elif defined(CONFIG_8xx_CONS_SCC2)
708 #elif defined(CONFIG_8xx_CONS_SCC3)
710 #elif defined(CONFIG_8xx_CONS_SCC4)
717 serial_printf("[on %s%d] ", default_serial_console()->name, i);
728 putDebugStr (const char *str)
736 return serial_getc();
740 kgdb_interruptible (int yes)
746 #endif /* CONFIG_8xx_CONS_NONE */