2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CONFIG_SYS_MEASURE_CPUCLK) || defined(DEBUG)
18 /* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */
19 #define SPEED_PIT_COUNTS 58
20 #define SPEED_PITC ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT)
21 #define SPEED_PITC_INIT ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT)
23 /* Access functions for the Machine State Register */
24 static __inline__ unsigned long get_msr(void)
28 asm volatile("mfmsr %0" : "=r" (msr) :);
32 static __inline__ void set_msr(unsigned long msr)
34 asm volatile("mtmsr %0" : : "r" (msr));
37 /* ------------------------------------------------------------------------- */
40 * Measure CPU clock speed (core clock GCLK1, GCLK2),
41 * also determine bus clock speed (checking bus divider factor)
43 * (Approx. GCLK frequency in Hz)
45 * Initializes timer 2 and PIT, but disables them before return.
46 * [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4]
48 * When measuring the CPU clock against the PIT, we count cpu clocks
49 * for 58/8192 seconds with a prescale divide by 177 for the cpu clock.
50 * These strange values for the timing interval and prescaling are used
51 * because the formula for the CPU clock is:
53 * CPU clock = count * (177 * (8192 / 58))
55 * = count * 24999.7241
57 * which is very close to
61 * Since the count gives the CPU clock divided by 25000, we can get
62 * the CPU clock rounded to the nearest 0.1 MHz by
64 * CPU clock = ((count + 2) / 4) * 100000;
66 * The rounding is important since the measurement is sometimes going
67 * to be high or low by 0.025 MHz, depending on exactly how the clocks
68 * and counters interact. By rounding we get the exact answer for any
69 * CPU clock that is an even multiple of 0.1 MHz.
72 unsigned long measure_gclk(void)
74 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
75 volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
79 #ifdef CONFIG_SYS_8XX_XIN
80 /* dont use OSCM, only use EXTCLK/512 */
81 immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
83 immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV);
86 /* Reset + Stop Timer 2, no cascading
88 timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2);
90 /* Keep stopped, halt in debug mode
92 timerp->cpmt_tgcr |= (TGCR_FRZ2 | TGCR_STP2);
95 * Output ref. interrupt disable, int. clock
96 * Prescale by 177. Note that prescaler divides by value + 1
97 * so we must subtract 1 here.
99 timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN;
101 timerp->cpmt_tcn2 = 0; /* reset state */
102 timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */
107 * We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz),
108 * so the count value would be SPEED_PITC_COUNTS - 1.
109 * But there would be an uncertainty in the start time of 1/4
110 * count since when we enable the PIT the count is not
111 * synchronized to the 32768 Hz oscillator. The trick here is
112 * to start the count higher and wait until the PIT count
113 * changes to the required value before starting timer 2.
115 * One count high should be enough, but occasionally the start
116 * is off by 1 or 2 counts of 32768 Hz. With the start value
117 * set two counts high it seems very reliable.
120 immr->im_sitk.sitk_pitck = KAPWR_KEY; /* PIT initialization */
121 immr->im_sit.sit_pitc = SPEED_PITC_INIT;
123 immr->im_sitk.sitk_piscrk = KAPWR_KEY;
124 immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
127 * Start measurement - disable interrupts, just in case
129 msr_val = get_msr ();
130 set_msr (msr_val & ~MSR_EE);
132 immr->im_sit.sit_piscr |= PISCR_PTE;
134 /* spin until get exact count when we want to start */
135 while (immr->im_sit.sit_pitr > SPEED_PITC);
137 timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */
138 while ((immr->im_sit.sit_piscr & PISCR_PS) == 0);
139 timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */
141 /* re-enable external interrupts if they were on */
144 /* Disable timer and PIT
146 timer2_val = timerp->cpmt_tcn2; /* save before reset timer */
148 timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
149 immr->im_sit.sit_piscr &= ~PISCR_PTE;
151 #if defined(CONFIG_SYS_8XX_XIN)
152 /* not using OSCM, using XIN, so scale appropriately */
153 return (((timer2_val + 2) / 4) * (CONFIG_SYS_8XX_XIN/512))/8192 * 100000L;
155 return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
161 void get_brgclk(uint sccr)
165 switch((sccr&SCCR_DFBRG11)>>11){
179 gd->arch.brg_clk = gd->cpu_clk/divider;
182 #if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
185 * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
186 * or (if it is not defined) measure_gclk() (which uses the ref clock)
189 int get_clocks (void)
191 uint immr = get_immr (0); /* Return full IMMR contents */
192 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
193 uint sccr = immap->im_clkrst.car_sccr;
195 * If for some reason measuring the gclk frequency won't
196 * work, we return the hardwired value.
197 * (For example, the cogent CMA286-60 CPU module has no
198 * separate oscillator for PITRTCLK)
200 #if defined(CONFIG_8xx_GCLK_FREQ)
201 gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
202 #elif defined(CONFIG_8xx_OSCLK)
203 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
204 uint pll = immap->im_clkrst.car_plprcr;
207 if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
208 clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) *
209 (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) /
212 clk = CONFIG_8xx_OSCLK * (PLPRCR_val(MF)+1);
214 if (pll & PLPRCR_CSRC) { /* Low frequency division factor is used */
215 gd->cpu_clk = clk / (2 << ((sccr >> 8) & 7));
216 } else { /* High frequency division factor is used */
217 gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7));
220 gd->cpu_clk = measure_gclk();
221 #endif /* CONFIG_8xx_GCLK_FREQ */
223 if ((sccr & SCCR_EBDF11) == 0) {
224 /* No Bus Divider active */
225 gd->bus_clk = gd->cpu_clk;
227 /* The MPC8xx has only one BDF: half clock speed */
228 gd->bus_clk = gd->cpu_clk / 2;
236 #else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */
238 static long init_pll_866 (long clk);
240 /* This function sets up PLL (init_pll_866() is called) and
241 * fills gd->cpu_clk and gd->bus_clk according to the environment
242 * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk'
243 * contains invalid value).
244 * This functions requires an MPC866 or newer series CPU.
246 int get_clocks_866 (void)
248 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
253 if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0)
254 cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
256 if ((CONFIG_SYS_8xx_CPUCLK_MIN > cpuclk) || (CONFIG_SYS_8xx_CPUCLK_MAX < cpuclk))
257 cpuclk = CONFIG_8xx_CPUCLK_DEFAULT;
259 gd->cpu_clk = init_pll_866 (cpuclk);
260 #if defined(CONFIG_SYS_MEASURE_CPUCLK)
261 gd->cpu_clk = measure_gclk ();
264 get_brgclk(immr->im_clkrst.car_sccr);
266 /* if cpu clock <= 66 MHz then set bus division factor to 1,
267 * otherwise set it to 2
269 sccr_reg = immr->im_clkrst.car_sccr;
270 sccr_reg &= ~SCCR_EBDF11;
272 if (gd->cpu_clk <= 66000000) {
273 sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */
274 gd->bus_clk = gd->cpu_clk;
276 sccr_reg |= SCCR_EBDF01; /* bus division factor = 2 */
277 gd->bus_clk = gd->cpu_clk / 2;
279 immr->im_clkrst.car_sccr = sccr_reg;
284 /* Adjust sdram refresh rate to actual CPU clock.
286 int sdram_adjust_866 (void)
288 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
291 mamr = immr->im_memctl.memc_mamr;
292 mamr &= ~MAMR_PTA_MSK;
293 mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
294 immr->im_memctl.memc_mamr = mamr;
299 /* Configure PLL for MPC866/859/885 CPU series
300 * PLL multiplication factor is set to the value nearest to the desired clk,
301 * assuming a oscclk of 10 MHz.
303 static long init_pll_866 (long clk)
305 extern void plprcr_write_866 (long);
307 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
309 char mfi, mfn, mfd, s, pdf;
310 long step_mfi, step_mfn;
312 if (clk < 20000000) {
319 if (clk < 40000000) {
321 step_mfi = CONFIG_8xx_OSCLK / 4;
323 step_mfn = CONFIG_8xx_OSCLK / 30;
324 } else if (clk < 80000000) {
326 step_mfi = CONFIG_8xx_OSCLK / 2;
328 step_mfn = CONFIG_8xx_OSCLK / 30;
331 step_mfi = CONFIG_8xx_OSCLK;
333 step_mfn = CONFIG_8xx_OSCLK / 30;
336 /* Calculate integer part of multiplication factor
341 /* Calculate numerator of fractional part of multiplication factor
343 n = clk - (n * step_mfi);
344 mfn = (char)(n / step_mfn);
346 /* Calculate effective clk
348 n = ((mfi * step_mfi) + (mfn * step_mfn)) / (pdf + 1);
350 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
352 plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK
353 | PLPRCR_MFD_MSK | PLPRCR_S_MSK
354 | PLPRCR_MFI_MSK | PLPRCR_DBRMO
356 | (mfn << PLPRCR_MFN_SHIFT)
357 | (mfd << PLPRCR_MFD_SHIFT)
358 | (s << PLPRCR_S_SHIFT)
359 | (mfi << PLPRCR_MFI_SHIFT)
360 | (pdf << PLPRCR_PDF_SHIFT);
362 if( (mfn > 0) && ((mfd / mfn) > 10) )
363 plprcr |= PLPRCR_DBRMO;
365 plprcr_write_866 (plprcr); /* set value using SIU4/9 workaround */
366 immr->im_clkrstk.cark_plprcrk = 0x00000000;
371 #endif /* CONFIG_8xx_CPUCLK_DEFAULT */
373 #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
374 && !defined(CONFIG_TQM885D)
376 * Adjust sdram refresh rate to actual CPU clock
377 * and set timebase source according to actual CPU clock
379 int adjust_sdram_tbs_8xx (void)
381 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
385 mamr = immr->im_memctl.memc_mamr;
386 mamr &= ~MAMR_PTA_MSK;
387 mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
388 immr->im_memctl.memc_mamr = mamr;
390 if (gd->cpu_clk < 67000000) {
391 sccr = immr->im_clkrst.car_sccr;
393 immr->im_clkrst.car_sccr = sccr;
398 #endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
400 /* ------------------------------------------------------------------------- */