2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /* U-Boot - Startup Code for PowerPC based Embedded Boards
28 * The processor starts at 0x00000100 and the code is executed
29 * from flash. The code is organized to be at an other address
30 * in memory, but as long we don't jump around before relocating,
31 * board_init lies at a quite high address and when the cpu has
32 * jumped there, everything is ok.
33 * This works because the cpu gives the FLASH (CS0) the whole
34 * address space at startup, and board_init lies as a echo of
35 * the flash somewhere up there in the memory map.
37 * board_init will change CS0 to be positioned at the correct
38 * address and (s)dram will be positioned at address 0
40 #include <asm-offsets.h>
43 #include <timestamp.h>
46 #define CONFIG_8xx 1 /* needed for Linux kernel header files */
47 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
49 #include <ppc_asm.tmpl>
52 #include <asm/cache.h>
54 #include <asm/u-boot.h>
56 #ifndef CONFIG_IDENT_STRING
57 #define CONFIG_IDENT_STRING ""
60 /* We don't want the MMU yet.
63 #define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
66 * Set up GOT: Global Offset Table
68 * Use r12 to access the GOT
71 GOT_ENTRY(_GOT2_TABLE_)
72 GOT_ENTRY(_FIXUP_TABLE_)
75 GOT_ENTRY(_start_of_vectors)
76 GOT_ENTRY(_end_of_vectors)
77 GOT_ENTRY(transfer_to_handler)
80 GOT_ENTRY(__bss_end__)
81 GOT_ENTRY(__bss_start)
85 * r3 - 1st arg to board_init(): IMMP pointer
86 * r4 - 2nd arg to board_init(): boot flag
89 .long 0x27051956 /* U-Boot Magic Number */
93 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
94 .ascii CONFIG_IDENT_STRING, "\0"
99 lis r3, CONFIG_SYS_IMMR@h /* position IMMR */
102 /* Initialize machine status; enable machine check interrupt */
103 /*----------------------------------------------------------------------*/
104 li r3, MSR_KERNEL /* Set ME, RI flags */
106 mtspr SRR1, r3 /* Make SRR1 match MSR */
108 mfspr r3, ICR /* clear Interrupt Cause Register */
110 /* Initialize debug port registers */
111 /*----------------------------------------------------------------------*/
112 xor r0, r0, r0 /* Clear R0 */
113 mtspr LCTRL1, r0 /* Initialize debug port regs */
118 /* Reset the caches */
119 /*----------------------------------------------------------------------*/
121 mfspr r3, IC_CST /* Clear error bits */
124 lis r3, IDC_UNALL@h /* Unlock all */
128 lis r3, IDC_INVALL@h /* Invalidate all */
132 lis r3, IDC_DISABLE@h /* Disable data cache */
135 #if !defined(CONFIG_SYS_DELAYED_ICACHE)
136 /* On IP860 and PCU E,
137 * we cannot enable IC yet
139 lis r3, IDC_ENABLE@h /* Enable instruction cache */
143 /* invalidate all tlb's */
144 /*----------------------------------------------------------------------*/
150 * Calculate absolute address in FLASH and jump there
151 *----------------------------------------------------------------------*/
153 lis r3, CONFIG_SYS_MONITOR_BASE@h
154 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
155 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
161 /* initialize some SPRs that are hard to access from C */
162 /*----------------------------------------------------------------------*/
164 lis r3, CONFIG_SYS_IMMR@h /* pass IMMR as arg1 to C routine */
165 ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
166 /* Note: R0 is still 0 here */
167 stwu r0, -4(r1) /* clear final stack frame so that */
168 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
171 * Disable serialized ifetch and show cycles
172 * (i.e. set processor to normal mode).
173 * This is also a silicon bug workaround, see errata
179 /* Set up debug mode entry */
181 lis r2, CONFIG_SYS_DER@h
182 ori r2, r2, CONFIG_SYS_DER@l
185 /* let the C-code set up the rest */
187 /* Be careful to keep code relocatable ! */
188 /*----------------------------------------------------------------------*/
190 GET_GOT /* initialize GOT access */
191 #if defined(__pic__) && __pic__ == 1
192 /* Needed for upcoming -msingle-pic-base */
193 bl _GLOBAL_OFFSET_TABLE_@local-4
197 bl cpu_init_f /* run low-level CPU init code (from Flash) */
199 bl board_init_f /* run 1st part of board init code (from Flash) */
201 /* NOTREACHED - board_init_f() does not return */
204 .globl _start_of_vectors
208 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
210 /* Data Storage exception. "Never" generated on the 860. */
211 STD_EXCEPTION(0x300, DataStorage, UnknownException)
213 /* Instruction Storage exception. "Never" generated on the 860. */
214 STD_EXCEPTION(0x400, InstStorage, UnknownException)
216 /* External Interrupt exception. */
217 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
219 /* Alignment exception. */
222 EXCEPTION_PROLOG(SRR0, SRR1)
227 addi r3,r1,STACK_FRAME_OVERHEAD
228 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
230 /* Program check exception */
233 EXCEPTION_PROLOG(SRR0, SRR1)
234 addi r3,r1,STACK_FRAME_OVERHEAD
235 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
238 /* No FPU on MPC8xx. This exception is not supposed to happen.
240 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
242 /* I guess we could implement decrementer, and may have
243 * to someday for timekeeping.
245 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
246 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
247 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
248 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
249 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
251 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
252 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
254 /* On the MPC8xx, this is a software emulation interrupt. It occurs
255 * for all unimplemented and illegal instructions.
257 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
259 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
260 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
261 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
262 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
264 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
265 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
266 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
267 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
268 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
269 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
270 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
272 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
273 STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
274 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
275 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
278 .globl _end_of_vectors
285 * This code finishes saving the registers to the exception frame
286 * and jumps to the appropriate handler for the exception.
287 * Register r21 is pointer into trap frame, r1 has new stack pointer.
289 .globl transfer_to_handler
300 andi. r24,r23,0x3f00 /* get vector offset */
304 mtspr SPRG2,r22 /* r1 is now kernel sp */
305 lwz r24,0(r23) /* virtual address of handler */
306 lwz r23,4(r23) /* where to go when done */
311 rfi /* jump to handler, enable MMU */
314 mfmsr r28 /* Disable interrupts */
318 SYNC /* Some chip revs need this... */
333 lwz r2,_NIP(r1) /* Restore environment */
354 .globl icache_disable
357 lis r3, IDC_DISABLE@h
364 srwi r3, r3, 31 /* >>31 => select bit 0 */
373 lis r3, 0x0400 /* Set cache mode with MMU off */
387 .globl dcache_disable
390 lis r3, IDC_DISABLE@h
399 srwi r3, r3, 31 /* >>31 => select bit 0 */
409 * unsigned int get_immr (unsigned int mask)
411 * return (mask ? (IMMR & mask) : IMMR);
415 mr r4,r3 /* save mask */
416 mfspr r3, IMMR /* IMMR */
417 cmpwi 0,r4,0 /* mask != 0 ? */
419 and r3,r3,r4 /* IMMR & mask */
460 /*------------------------------------------------------------------------------*/
463 * void relocate_code (addr_sp, gd, addr_moni)
465 * This "function" does not return, instead it continues in RAM
466 * after relocating the monitor code.
470 * r5 = length in bytes
475 mr r1, r3 /* Set new stack pointer */
476 mr r9, r4 /* Save copy of Global Data pointer */
477 mr r10, r5 /* Save copy of Destination Address */
480 #if defined(__pic__) && __pic__ == 1
481 /* Needed for upcoming -msingle-pic-base */
482 bl _GLOBAL_OFFSET_TABLE_@local-4
485 mr r3, r5 /* Destination Address */
486 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
487 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
488 lwz r5, GOT(__init_end)
490 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
495 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
501 /* First our own GOT */
503 /* then the one used by the C code */
513 beq cr1,4f /* In place copy is not necessary */
514 beq 7f /* Protect against 0 count */
533 * Now flush the cache: note that we must start from a cache aligned
534 * address. Otherwise we might miss one cache line.
538 beq 7f /* Always flush prefetch queue in any case */
546 sync /* Wait for all dcbst to complete on bus */
552 7: sync /* Wait for all icbi to complete on bus */
556 * We are done. Do not return, instead branch to second part of board
557 * initialization, now running from RAM.
560 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
567 * Relocation Function, r12 point to got2+0x8000
569 * Adjust got2 pointers, no need to check for 0, this code
570 * already puts a few entries in the table.
572 li r0,__got2_entries@sectoff@l
573 la r3,GOT(_GOT2_TABLE_)
574 lwz r11,GOT(_GOT2_TABLE_)
586 * Now adjust the fixups and the pointers to the fixups
587 * in case we need to move ourselves again.
589 li r0,__fixup_entries@sectoff@l
590 lwz r3,GOT(_FIXUP_TABLE_)
606 * Now clear BSS segment
608 lwz r3,GOT(__bss_start)
609 lwz r4,GOT(__bss_end__)
622 mr r3, r9 /* Global Data pointer */
623 mr r4, r10 /* Destination Address */
627 * Copy exception vector code to low memory
630 * r7: source address, r8: end address, r9: target address
634 mflr r4 /* save link register */
637 lwz r8, GOT(_end_of_vectors)
639 li r9, 0x100 /* reset vector always at 0x100 */
642 bgelr /* return if r7>=r8 - just in case */
652 * relocate `hdlr' and `int_return' entries
654 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
655 li r8, Alignment - _start + EXC_OFF_SYS_RESET
658 addi r7, r7, 0x100 /* next exception vector */
662 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
665 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
668 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
669 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
672 addi r7, r7, 0x100 /* next exception vector */
676 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
677 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
680 addi r7, r7, 0x100 /* next exception vector */
684 mtlr r4 /* restore link register */