2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
14 #include <asm/fsl_ddr_sdram.h>
18 #define _DDR_ADDR CONFIG_SYS_MPC8xxx_DDR_ADDR
20 static u32 fsl_ddr_get_version(void)
23 u32 ver_major_minor_errata;
25 ddr = (void *)_DDR_ADDR;
26 ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
27 ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
29 return ver_major_minor_errata;
32 unsigned int picos_to_mclk(unsigned int picos);
35 * Determine Rtt value.
37 * This should likely be either board or controller specific.
39 * Rtt(nominal) - DDR2:
44 * Rtt(nominal) - DDR3:
52 * FIXME: Apparently 8641 needs a value of 2
53 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
55 * FIXME: There was some effort down this line earlier:
58 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
59 * if (popts->dimmslot[i].num_valid_cs
60 * && (popts->cs_local_opts[2*i].odt_rd_cfg
61 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
67 static inline int fsl_ddr_get_rtt(void)
71 #if defined(CONFIG_FSL_DDR1)
73 #elif defined(CONFIG_FSL_DDR2)
83 * compute the CAS write latency according to DDR3 spec
84 * CWL = 5 if tCK >= 2.5ns
85 * 6 if 2.5ns > tCK >= 1.875ns
86 * 7 if 1.875ns > tCK >= 1.5ns
87 * 8 if 1.5ns > tCK >= 1.25ns
88 * 9 if 1.25ns > tCK >= 1.07ns
89 * 10 if 1.07ns > tCK >= 0.935ns
90 * 11 if 0.935ns > tCK >= 0.833ns
91 * 12 if 0.833ns > tCK >= 0.75ns
93 static inline unsigned int compute_cas_write_latency(void)
96 const unsigned int mclk_ps = get_memory_clk_period_ps();
100 else if (mclk_ps >= 1875)
102 else if (mclk_ps >= 1500)
104 else if (mclk_ps >= 1250)
106 else if (mclk_ps >= 1070)
108 else if (mclk_ps >= 935)
110 else if (mclk_ps >= 833)
112 else if (mclk_ps >= 750)
116 printf("Warning: CWL is out of range\n");
121 /* Chip Select Configuration (CSn_CONFIG) */
122 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
123 const memctl_options_t *popts,
124 const dimm_params_t *dimm_params)
126 unsigned int cs_n_en = 0; /* Chip Select enable */
127 unsigned int intlv_en = 0; /* Memory controller interleave enable */
128 unsigned int intlv_ctl = 0; /* Interleaving control */
129 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
130 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
131 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
132 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
133 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
134 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
137 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
140 if (dimm_params[dimm_number].n_ranks > 0) {
142 /* These fields only available in CS0_CONFIG */
143 if (!popts->memctl_interleaving)
145 switch (popts->memctl_interleaving_mode) {
146 case FSL_DDR_CACHE_LINE_INTERLEAVING:
147 case FSL_DDR_PAGE_INTERLEAVING:
148 case FSL_DDR_BANK_INTERLEAVING:
149 case FSL_DDR_SUPERBANK_INTERLEAVING:
150 intlv_en = popts->memctl_interleaving;
151 intlv_ctl = popts->memctl_interleaving_mode;
159 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
160 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
164 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
165 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
169 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
170 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
171 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
178 unsigned int n_banks_per_sdram_device;
180 ap_n_en = popts->cs_local_opts[i].auto_precharge;
181 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
182 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
183 n_banks_per_sdram_device
184 = dimm_params[dimm_number].n_banks_per_sdram_device;
185 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
186 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
187 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
189 ddr->cs[i].config = (0
190 | ((cs_n_en & 0x1) << 31)
191 | ((intlv_en & 0x3) << 29)
192 | ((intlv_ctl & 0xf) << 24)
193 | ((ap_n_en & 0x1) << 23)
195 /* XXX: some implementation only have 1 bit starting at left */
196 | ((odt_rd_cfg & 0x7) << 20)
198 /* XXX: Some implementation only have 1 bit starting at left */
199 | ((odt_wr_cfg & 0x7) << 16)
201 | ((ba_bits_cs_n & 0x3) << 14)
202 | ((row_bits_cs_n & 0x7) << 8)
203 | ((col_bits_cs_n & 0x7) << 0)
205 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
208 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
210 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
212 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
214 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
215 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
218 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
220 #if !defined(CONFIG_FSL_DDR1)
221 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
223 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
224 if (dimm_params[0].n_ranks == 4)
228 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
229 if ((dimm_params[0].n_ranks == 2) &&
230 (dimm_params[1].n_ranks == 2))
233 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
234 if (dimm_params[0].n_ranks == 4)
242 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
244 * Avoid writing for DDR I. The new PQ38 DDR controller
245 * dreams up non-zero default values to be backwards compatible.
247 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
248 const memctl_options_t *popts,
249 const dimm_params_t *dimm_params)
251 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
252 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
253 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
254 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
255 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
257 /* Active powerdown exit timing (tXARD and tXARDS). */
258 unsigned char act_pd_exit_mclk;
259 /* Precharge powerdown exit timing (tXP). */
260 unsigned char pre_pd_exit_mclk;
261 /* ODT powerdown exit timing (tAXPD). */
262 unsigned char taxpd_mclk;
263 /* Mode register set cycle time (tMRD). */
264 unsigned char tmrd_mclk;
266 #ifdef CONFIG_FSL_DDR3
268 * (tXARD and tXARDS). Empirical?
269 * The DDR3 spec has not tXARD,
270 * we use the tXP instead of it.
271 * tXP=max(3nCK, 7.5ns) for DDR3.
272 * spec has not the tAXPD, we use
273 * tAXPD=1, need design to confirm.
275 int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
276 unsigned int data_rate = get_ddr_freq(0);
278 /* set the turnaround time */
281 * for single quad-rank DIMM and two dual-rank DIMMs
282 * to avoid ODT overlap
284 if (avoid_odt_overlap(dimm_params)) {
288 /* for faster clock, need more time for data setup */
289 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
291 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
294 if (popts->dynamic_power == 0) { /* powerdown is not used */
295 act_pd_exit_mclk = 1;
296 pre_pd_exit_mclk = 1;
299 /* act_pd_exit_mclk = tXARD, see above */
300 act_pd_exit_mclk = picos_to_mclk(tXP);
301 /* Mode register MR0[A12] is '1' - fast exit */
302 pre_pd_exit_mclk = act_pd_exit_mclk;
305 #else /* CONFIG_FSL_DDR2 */
307 * (tXARD and tXARDS). Empirical?
312 act_pd_exit_mclk = 2;
313 pre_pd_exit_mclk = 2;
318 if (popts->trwt_override)
319 trwt_mclk = popts->trwt;
321 ddr->timing_cfg_0 = (0
322 | ((trwt_mclk & 0x3) << 30) /* RWT */
323 | ((twrt_mclk & 0x3) << 28) /* WRT */
324 | ((trrt_mclk & 0x3) << 26) /* RRT */
325 | ((twwt_mclk & 0x3) << 24) /* WWT */
326 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
327 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
328 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
329 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
331 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
333 #endif /* defined(CONFIG_FSL_DDR2) */
335 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
336 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
337 const memctl_options_t *popts,
338 const common_timing_params_t *common_dimm,
339 unsigned int cas_latency)
341 /* Extended precharge to activate interval (tRP) */
342 unsigned int ext_pretoact = 0;
343 /* Extended Activate to precharge interval (tRAS) */
344 unsigned int ext_acttopre = 0;
345 /* Extended activate to read/write interval (tRCD) */
346 unsigned int ext_acttorw = 0;
347 /* Extended refresh recovery time (tRFC) */
348 unsigned int ext_refrec;
349 /* Extended MCAS latency from READ cmd */
350 unsigned int ext_caslat = 0;
351 /* Extended last data to precharge interval (tWR) */
352 unsigned int ext_wrrec = 0;
354 unsigned int cntl_adj = 0;
356 ext_pretoact = picos_to_mclk(common_dimm->tRP_ps) >> 4;
357 ext_acttopre = picos_to_mclk(common_dimm->tRAS_ps) >> 4;
358 ext_acttorw = picos_to_mclk(common_dimm->tRCD_ps) >> 4;
359 ext_caslat = (2 * cas_latency - 1) >> 4;
360 ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
361 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
362 ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) +
363 (popts->OTF_burst_chop_en ? 2 : 0)) >> 4;
365 ddr->timing_cfg_3 = (0
366 | ((ext_pretoact & 0x1) << 28)
367 | ((ext_acttopre & 0x3) << 24)
368 | ((ext_acttorw & 0x1) << 22)
369 | ((ext_refrec & 0x1F) << 16)
370 | ((ext_caslat & 0x3) << 12)
371 | ((ext_wrrec & 0x1) << 8)
372 | ((cntl_adj & 0x7) << 0)
374 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
377 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
378 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
379 const memctl_options_t *popts,
380 const common_timing_params_t *common_dimm,
381 unsigned int cas_latency)
383 /* Precharge-to-activate interval (tRP) */
384 unsigned char pretoact_mclk;
385 /* Activate to precharge interval (tRAS) */
386 unsigned char acttopre_mclk;
387 /* Activate to read/write interval (tRCD) */
388 unsigned char acttorw_mclk;
390 unsigned char caslat_ctrl;
391 /* Refresh recovery time (tRFC) ; trfc_low */
392 unsigned char refrec_ctrl;
393 /* Last data to precharge minimum interval (tWR) */
394 unsigned char wrrec_mclk;
395 /* Activate-to-activate interval (tRRD) */
396 unsigned char acttoact_mclk;
397 /* Last write data pair to read command issue interval (tWTR) */
398 unsigned char wrtord_mclk;
399 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
400 static const u8 wrrec_table[] = {
401 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
403 pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
404 acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
405 acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
408 * Translate CAS Latency to a DDR controller field value:
410 * CAS Lat DDR I DDR II Ctrl
411 * Clocks SPD Bit SPD Bit Value
412 * ------- ------- ------- -----
423 #if defined(CONFIG_FSL_DDR1)
424 caslat_ctrl = (cas_latency + 1) & 0x07;
425 #elif defined(CONFIG_FSL_DDR2)
426 caslat_ctrl = 2 * cas_latency - 1;
429 * if the CAS latency more than 8 cycle,
430 * we need set extend bit for it at
431 * TIMING_CFG_3[EXT_CASLAT]
433 caslat_ctrl = 2 * cas_latency - 1;
436 refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
437 wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
440 printf("Error: WRREC doesn't support more than 16 clocks\n");
442 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
443 if (popts->OTF_burst_chop_en)
446 acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
448 * JEDEC has min requirement for tRRD
450 #if defined(CONFIG_FSL_DDR3)
451 if (acttoact_mclk < 4)
454 wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
456 * JEDEC has some min requirements for tWTR
458 #if defined(CONFIG_FSL_DDR2)
461 #elif defined(CONFIG_FSL_DDR3)
465 if (popts->OTF_burst_chop_en)
468 ddr->timing_cfg_1 = (0
469 | ((pretoact_mclk & 0x0F) << 28)
470 | ((acttopre_mclk & 0x0F) << 24)
471 | ((acttorw_mclk & 0xF) << 20)
472 | ((caslat_ctrl & 0xF) << 16)
473 | ((refrec_ctrl & 0xF) << 12)
474 | ((wrrec_mclk & 0x0F) << 8)
475 | ((acttoact_mclk & 0x0F) << 4)
476 | ((wrtord_mclk & 0x0F) << 0)
478 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
481 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
482 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
483 const memctl_options_t *popts,
484 const common_timing_params_t *common_dimm,
485 unsigned int cas_latency,
486 unsigned int additive_latency)
488 /* Additive latency */
489 unsigned char add_lat_mclk;
490 /* CAS-to-preamble override */
493 unsigned char wr_lat;
494 /* Read to precharge (tRTP) */
495 unsigned char rd_to_pre;
496 /* Write command to write data strobe timing adjustment */
497 unsigned char wr_data_delay;
498 /* Minimum CKE pulse width (tCKE) */
499 unsigned char cke_pls;
500 /* Window for four activates (tFAW) */
501 unsigned short four_act;
503 /* FIXME add check that this must be less than acttorw_mclk */
504 add_lat_mclk = additive_latency;
505 cpo = popts->cpo_override;
507 #if defined(CONFIG_FSL_DDR1)
509 * This is a lie. It should really be 1, but if it is
510 * set to 1, bits overlap into the old controller's
511 * otherwise unused ACSM field. If we leave it 0, then
512 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
515 #elif defined(CONFIG_FSL_DDR2)
516 wr_lat = cas_latency - 1;
518 wr_lat = compute_cas_write_latency();
521 rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
523 * JEDEC has some min requirements for tRTP
525 #if defined(CONFIG_FSL_DDR2)
528 #elif defined(CONFIG_FSL_DDR3)
532 if (additive_latency)
533 rd_to_pre += additive_latency;
534 if (popts->OTF_burst_chop_en)
535 rd_to_pre += 2; /* according to UM */
537 wr_data_delay = popts->write_data_delay;
538 cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
539 four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
541 ddr->timing_cfg_2 = (0
542 | ((add_lat_mclk & 0xf) << 28)
543 | ((cpo & 0x1f) << 23)
544 | ((wr_lat & 0xf) << 19)
545 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
546 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
547 | ((cke_pls & 0x7) << 6)
548 | ((four_act & 0x3f) << 0)
550 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
553 /* DDR SDRAM Register Control Word */
554 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
555 const memctl_options_t *popts,
556 const common_timing_params_t *common_dimm)
558 if (common_dimm->all_DIMMs_registered
559 && !common_dimm->all_DIMMs_unbuffered) {
560 if (popts->rcw_override) {
561 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
562 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
564 ddr->ddr_sdram_rcw_1 =
565 common_dimm->rcw[0] << 28 | \
566 common_dimm->rcw[1] << 24 | \
567 common_dimm->rcw[2] << 20 | \
568 common_dimm->rcw[3] << 16 | \
569 common_dimm->rcw[4] << 12 | \
570 common_dimm->rcw[5] << 8 | \
571 common_dimm->rcw[6] << 4 | \
573 ddr->ddr_sdram_rcw_2 =
574 common_dimm->rcw[8] << 28 | \
575 common_dimm->rcw[9] << 24 | \
576 common_dimm->rcw[10] << 20 | \
577 common_dimm->rcw[11] << 16 | \
578 common_dimm->rcw[12] << 12 | \
579 common_dimm->rcw[13] << 8 | \
580 common_dimm->rcw[14] << 4 | \
581 common_dimm->rcw[15];
583 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
584 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
588 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
589 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
590 const memctl_options_t *popts,
591 const common_timing_params_t *common_dimm)
593 unsigned int mem_en; /* DDR SDRAM interface logic enable */
594 unsigned int sren; /* Self refresh enable (during sleep) */
595 unsigned int ecc_en; /* ECC enable. */
596 unsigned int rd_en; /* Registered DIMM enable */
597 unsigned int sdram_type; /* Type of SDRAM */
598 unsigned int dyn_pwr; /* Dynamic power management mode */
599 unsigned int dbw; /* DRAM dta bus width */
600 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
601 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
602 unsigned int threeT_en; /* Enable 3T timing */
603 unsigned int twoT_en; /* Enable 2T timing */
604 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
605 unsigned int x32_en = 0; /* x32 enable */
606 unsigned int pchb8 = 0; /* precharge bit 8 enable */
607 unsigned int hse; /* Global half strength override */
608 unsigned int mem_halt = 0; /* memory controller halt */
609 unsigned int bi = 0; /* Bypass initialization */
612 sren = popts->self_refresh_in_sleep;
613 if (common_dimm->all_DIMMs_ECC_capable) {
614 /* Allow setting of ECC only if all DIMMs are ECC. */
615 ecc_en = popts->ECC_mode;
620 if (common_dimm->all_DIMMs_registered
621 && !common_dimm->all_DIMMs_unbuffered) {
626 twoT_en = popts->twoT_en;
629 sdram_type = CONFIG_FSL_SDRAM_TYPE;
631 dyn_pwr = popts->dynamic_power;
632 dbw = popts->data_bus_width;
633 /* 8-beat burst enable DDR-III case
634 * we must clear it when use the on-the-fly mode,
635 * must set it when use the 32-bits bus mode.
637 if (sdram_type == SDRAM_TYPE_DDR3) {
638 if (popts->burst_length == DDR_BL8)
640 if (popts->burst_length == DDR_OTF)
646 threeT_en = popts->threeT_en;
647 ba_intlv_ctl = popts->ba_intlv_ctl;
648 hse = popts->half_strength_driver_enable;
650 ddr->ddr_sdram_cfg = (0
651 | ((mem_en & 0x1) << 31)
652 | ((sren & 0x1) << 30)
653 | ((ecc_en & 0x1) << 29)
654 | ((rd_en & 0x1) << 28)
655 | ((sdram_type & 0x7) << 24)
656 | ((dyn_pwr & 0x1) << 21)
657 | ((dbw & 0x3) << 19)
658 | ((eight_be & 0x1) << 18)
659 | ((ncap & 0x1) << 17)
660 | ((threeT_en & 0x1) << 16)
661 | ((twoT_en & 0x1) << 15)
662 | ((ba_intlv_ctl & 0x7F) << 8)
663 | ((x32_en & 0x1) << 5)
664 | ((pchb8 & 0x1) << 4)
666 | ((mem_halt & 0x1) << 1)
669 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
672 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
673 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
674 const memctl_options_t *popts,
675 const unsigned int unq_mrs_en)
677 unsigned int frc_sr = 0; /* Force self refresh */
678 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
679 unsigned int dll_rst_dis; /* DLL reset disable */
680 unsigned int dqs_cfg; /* DQS configuration */
681 unsigned int odt_cfg = 0; /* ODT configuration */
682 unsigned int num_pr; /* Number of posted refreshes */
683 unsigned int slow = 0; /* DDR will be run less than 1250 */
684 unsigned int x4_en = 0; /* x4 DRAM enable */
685 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
686 unsigned int ap_en; /* Address Parity Enable */
687 unsigned int d_init; /* DRAM data initialization */
688 unsigned int rcw_en = 0; /* Register Control Word Enable */
689 unsigned int md_en = 0; /* Mirrored DIMM Enable */
690 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
693 dll_rst_dis = 1; /* Make this configurable */
694 dqs_cfg = popts->DQS_config;
695 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
696 if (popts->cs_local_opts[i].odt_rd_cfg
697 || popts->cs_local_opts[i].odt_wr_cfg) {
698 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
703 num_pr = 1; /* Make this configurable */
707 * {TIMING_CFG_1[PRETOACT]
708 * + [DDR_SDRAM_CFG_2[NUM_PR]
709 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
710 * << DDR_SDRAM_INTERVAL[REFINT]
712 #if defined(CONFIG_FSL_DDR3)
713 obc_cfg = popts->OTF_burst_chop_en;
718 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
719 slow = get_ddr_freq(0) < 1249000000;
722 if (popts->registered_dimm_en) {
724 ap_en = popts->ap_en;
729 x4_en = popts->x4_en ? 1 : 0;
731 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
732 /* Use the DDR controller to auto initialize memory. */
733 d_init = popts->ECC_init_using_memctl;
734 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
735 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
737 /* Memory will be initialized via DMA, or not at all. */
741 #if defined(CONFIG_FSL_DDR3)
742 md_en = popts->mirrored_dimm;
744 qd_en = popts->quad_rank_present ? 1 : 0;
745 ddr->ddr_sdram_cfg_2 = (0
746 | ((frc_sr & 0x1) << 31)
747 | ((sr_ie & 0x1) << 30)
748 | ((dll_rst_dis & 0x1) << 29)
749 | ((dqs_cfg & 0x3) << 26)
750 | ((odt_cfg & 0x3) << 21)
751 | ((num_pr & 0xf) << 12)
756 | ((obc_cfg & 0x1) << 6)
757 | ((ap_en & 0x1) << 5)
758 | ((d_init & 0x1) << 4)
759 | ((rcw_en & 0x1) << 2)
760 | ((md_en & 0x1) << 0)
762 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
765 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
766 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
767 const memctl_options_t *popts,
768 const unsigned int unq_mrs_en)
770 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
771 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
773 #if defined(CONFIG_FSL_DDR3)
775 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
776 unsigned int srt = 0; /* self-refresh temerature, normal range */
777 unsigned int asr = 0; /* auto self-refresh disable */
778 unsigned int cwl = compute_cas_write_latency() - 5;
779 unsigned int pasr = 0; /* partial array self refresh disable */
781 if (popts->rtt_override)
782 rtt_wr = popts->rtt_wr_override_value;
784 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
786 | ((rtt_wr & 0x3) << 9)
790 | ((pasr & 0x7) << 0));
792 ddr->ddr_sdram_mode_2 = (0
793 | ((esdmode2 & 0xFFFF) << 16)
794 | ((esdmode3 & 0xFFFF) << 0)
796 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
798 #ifdef CONFIG_FSL_DDR3
799 if (unq_mrs_en) { /* unique mode registers are supported */
800 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
801 if (popts->rtt_override)
802 rtt_wr = popts->rtt_wr_override_value;
804 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
806 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
807 esdmode2 |= (rtt_wr & 0x3) << 9;
810 ddr->ddr_sdram_mode_4 = (0
811 | ((esdmode2 & 0xFFFF) << 16)
812 | ((esdmode3 & 0xFFFF) << 0)
816 ddr->ddr_sdram_mode_6 = (0
817 | ((esdmode2 & 0xFFFF) << 16)
818 | ((esdmode3 & 0xFFFF) << 0)
822 ddr->ddr_sdram_mode_8 = (0
823 | ((esdmode2 & 0xFFFF) << 16)
824 | ((esdmode3 & 0xFFFF) << 0)
829 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
830 ddr->ddr_sdram_mode_4);
831 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
832 ddr->ddr_sdram_mode_6);
833 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
834 ddr->ddr_sdram_mode_8);
839 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
840 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
841 const memctl_options_t *popts,
842 const common_timing_params_t *common_dimm)
844 unsigned int refint; /* Refresh interval */
845 unsigned int bstopre; /* Precharge interval */
847 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
849 bstopre = popts->bstopre;
851 /* refint field used 0x3FFF in earlier controllers */
852 ddr->ddr_sdram_interval = (0
853 | ((refint & 0xFFFF) << 16)
854 | ((bstopre & 0x3FFF) << 0)
856 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
859 #if defined(CONFIG_FSL_DDR3)
860 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
861 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
862 const memctl_options_t *popts,
863 const common_timing_params_t *common_dimm,
864 unsigned int cas_latency,
865 unsigned int additive_latency,
866 const unsigned int unq_mrs_en)
868 unsigned short esdmode; /* Extended SDRAM mode */
869 unsigned short sdmode; /* SDRAM mode */
871 /* Mode Register - MR1 */
872 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
873 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
875 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
876 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
877 unsigned int dic = 0; /* Output driver impedance, 40ohm */
878 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
879 1=Disable (Test/Debug) */
881 /* Mode Register - MR0 */
882 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
883 unsigned int wr = 0; /* Write Recovery */
884 unsigned int dll_rst; /* DLL Reset */
885 unsigned int mode; /* Normal=0 or Test=1 */
886 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
887 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
889 unsigned int bl; /* BL: Burst Length */
891 unsigned int wr_mclk;
893 * DDR_SDRAM_MODE doesn't support 9,11,13,15
894 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
897 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
899 const unsigned int mclk_ps = get_memory_clk_period_ps();
902 if (popts->rtt_override)
903 rtt = popts->rtt_override_value;
905 rtt = popts->cs_local_opts[0].odt_rtt_norm;
907 if (additive_latency == (cas_latency - 1))
909 if (additive_latency == (cas_latency - 2))
912 if (popts->quad_rank_present)
913 dic = 1; /* output driver impedance 240/7 ohm */
916 * The esdmode value will also be used for writing
917 * MR1 during write leveling for DDR3, although the
918 * bits specifically related to the write leveling
919 * scheme will be handled automatically by the DDR
920 * controller. so we set the wrlvl_en = 0 here.
923 | ((qoff & 0x1) << 12)
924 | ((tdqs_en & 0x1) << 11)
925 | ((rtt & 0x4) << 7) /* rtt field is split */
926 | ((wrlvl_en & 0x1) << 7)
927 | ((rtt & 0x2) << 5) /* rtt field is split */
928 | ((dic & 0x2) << 4) /* DIC field is split */
930 | ((rtt & 0x1) << 2) /* rtt field is split */
931 | ((dic & 0x1) << 1) /* DIC field is split */
932 | ((dll_en & 0x1) << 0)
936 * DLL control for precharge PD
937 * 0=slow exit DLL off (tXPDLL)
938 * 1=fast exit DLL on (tXP)
942 wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
944 wr = wr_table[wr_mclk - 5];
946 printf("Error: unsupported write recovery for mode register "
947 "wr_mclk = %d\n", wr_mclk);
950 dll_rst = 0; /* dll no reset */
951 mode = 0; /* normal mode */
953 /* look up table to get the cas latency bits */
954 if (cas_latency >= 5 && cas_latency <= 16) {
955 unsigned char cas_latency_table[] = {
969 caslat = cas_latency_table[cas_latency - 5];
971 printf("Error: unsupported cas latency for mode register\n");
974 bt = 0; /* Nibble sequential */
976 switch (popts->burst_length) {
987 printf("Error: invalid burst length of %u specified. "
988 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
989 popts->burst_length);
995 | ((dll_on & 0x1) << 12)
997 | ((dll_rst & 0x1) << 8)
998 | ((mode & 0x1) << 7)
999 | (((caslat >> 1) & 0x7) << 4)
1001 | ((caslat & 1) << 2)
1005 ddr->ddr_sdram_mode = (0
1006 | ((esdmode & 0xFFFF) << 16)
1007 | ((sdmode & 0xFFFF) << 0)
1010 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1012 if (unq_mrs_en) { /* unique mode registers are supported */
1013 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1014 if (popts->rtt_override)
1015 rtt = popts->rtt_override_value;
1017 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1019 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1021 | ((rtt & 0x4) << 7) /* rtt field is split */
1022 | ((rtt & 0x2) << 5) /* rtt field is split */
1023 | ((rtt & 0x1) << 2) /* rtt field is split */
1027 ddr->ddr_sdram_mode_3 = (0
1028 | ((esdmode & 0xFFFF) << 16)
1029 | ((sdmode & 0xFFFF) << 0)
1033 ddr->ddr_sdram_mode_5 = (0
1034 | ((esdmode & 0xFFFF) << 16)
1035 | ((sdmode & 0xFFFF) << 0)
1039 ddr->ddr_sdram_mode_7 = (0
1040 | ((esdmode & 0xFFFF) << 16)
1041 | ((sdmode & 0xFFFF) << 0)
1046 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1047 ddr->ddr_sdram_mode_3);
1048 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1049 ddr->ddr_sdram_mode_5);
1050 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1051 ddr->ddr_sdram_mode_5);
1055 #else /* !CONFIG_FSL_DDR3 */
1057 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1058 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1059 const memctl_options_t *popts,
1060 const common_timing_params_t *common_dimm,
1061 unsigned int cas_latency,
1062 unsigned int additive_latency,
1063 const unsigned int unq_mrs_en)
1065 unsigned short esdmode; /* Extended SDRAM mode */
1066 unsigned short sdmode; /* SDRAM mode */
1069 * FIXME: This ought to be pre-calculated in a
1070 * technology-specific routine,
1071 * e.g. compute_DDR2_mode_register(), and then the
1072 * sdmode and esdmode passed in as part of common_dimm.
1075 /* Extended Mode Register */
1076 unsigned int mrs = 0; /* Mode Register Set */
1077 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1078 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1079 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1080 unsigned int ocd = 0; /* 0x0=OCD not supported,
1081 0x7=OCD default state */
1083 unsigned int al; /* Posted CAS# additive latency (AL) */
1084 unsigned int ods = 0; /* Output Drive Strength:
1085 0 = Full strength (18ohm)
1086 1 = Reduced strength (4ohm) */
1087 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1088 1=Disable (Test/Debug) */
1090 /* Mode Register (MR) */
1091 unsigned int mr; /* Mode Register Definition */
1092 unsigned int pd; /* Power-Down Mode */
1093 unsigned int wr; /* Write Recovery */
1094 unsigned int dll_res; /* DLL Reset */
1095 unsigned int mode; /* Normal=0 or Test=1 */
1096 unsigned int caslat = 0;/* CAS# latency */
1097 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1099 unsigned int bl; /* BL: Burst Length */
1101 #if defined(CONFIG_FSL_DDR2)
1102 const unsigned int mclk_ps = get_memory_clk_period_ps();
1104 dqs_en = !popts->DQS_config;
1105 rtt = fsl_ddr_get_rtt();
1107 al = additive_latency;
1110 | ((mrs & 0x3) << 14)
1111 | ((outputs & 0x1) << 12)
1112 | ((rdqs_en & 0x1) << 11)
1113 | ((dqs_en & 0x1) << 10)
1114 | ((ocd & 0x7) << 7)
1115 | ((rtt & 0x2) << 5) /* rtt field is split */
1117 | ((rtt & 0x1) << 2) /* rtt field is split */
1118 | ((ods & 0x1) << 1)
1119 | ((dll_en & 0x1) << 0)
1122 mr = 0; /* FIXME: CHECKME */
1125 * 0 = Fast Exit (Normal)
1126 * 1 = Slow Exit (Low Power)
1130 #if defined(CONFIG_FSL_DDR1)
1131 wr = 0; /* Historical */
1132 #elif defined(CONFIG_FSL_DDR2)
1133 wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
1138 #if defined(CONFIG_FSL_DDR1)
1139 if (1 <= cas_latency && cas_latency <= 4) {
1140 unsigned char mode_caslat_table[4] = {
1141 0x5, /* 1.5 clocks */
1142 0x2, /* 2.0 clocks */
1143 0x6, /* 2.5 clocks */
1144 0x3 /* 3.0 clocks */
1146 caslat = mode_caslat_table[cas_latency - 1];
1148 printf("Warning: unknown cas_latency %d\n", cas_latency);
1150 #elif defined(CONFIG_FSL_DDR2)
1151 caslat = cas_latency;
1155 switch (popts->burst_length) {
1163 printf("Error: invalid burst length of %u specified. "
1164 " Defaulting to 4 beats.\n",
1165 popts->burst_length);
1171 | ((mr & 0x3) << 14)
1172 | ((pd & 0x1) << 12)
1174 | ((dll_res & 0x1) << 8)
1175 | ((mode & 0x1) << 7)
1176 | ((caslat & 0x7) << 4)
1181 ddr->ddr_sdram_mode = (0
1182 | ((esdmode & 0xFFFF) << 16)
1183 | ((sdmode & 0xFFFF) << 0)
1185 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1189 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1190 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1192 unsigned int init_value; /* Initialization value */
1194 #ifdef CONFIG_MEM_INIT_VALUE
1195 init_value = CONFIG_MEM_INIT_VALUE;
1197 init_value = 0xDEADBEEF;
1199 ddr->ddr_data_init = init_value;
1203 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1204 * The old controller on the 8540/60 doesn't have this register.
1205 * Hope it's OK to set it (to 0) anyway.
1207 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1208 const memctl_options_t *popts)
1210 unsigned int clk_adjust; /* Clock adjust */
1212 clk_adjust = popts->clk_adjust;
1213 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1214 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1217 /* DDR Initialization Address (DDR_INIT_ADDR) */
1218 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1220 unsigned int init_addr = 0; /* Initialization address */
1222 ddr->ddr_init_addr = init_addr;
1225 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1226 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1228 unsigned int uia = 0; /* Use initialization address */
1229 unsigned int init_ext_addr = 0; /* Initialization address */
1231 ddr->ddr_init_ext_addr = (0
1232 | ((uia & 0x1) << 31)
1233 | (init_ext_addr & 0xF)
1237 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1238 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1239 const memctl_options_t *popts)
1241 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1242 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1243 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1244 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1245 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1247 #if defined(CONFIG_FSL_DDR3)
1248 if (popts->burst_length == DDR_BL8) {
1249 /* We set BL/2 for fixed BL8 */
1250 rrt = 0; /* BL/2 clocks */
1251 wwt = 0; /* BL/2 clocks */
1253 /* We need to set BL/2 + 2 to BC4 and OTF */
1254 rrt = 2; /* BL/2 + 2 clocks */
1255 wwt = 2; /* BL/2 + 2 clocks */
1257 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1259 ddr->timing_cfg_4 = (0
1260 | ((rwt & 0xf) << 28)
1261 | ((wrt & 0xf) << 24)
1262 | ((rrt & 0xf) << 20)
1263 | ((wwt & 0xf) << 16)
1266 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1269 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1270 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1272 unsigned int rodt_on = 0; /* Read to ODT on */
1273 unsigned int rodt_off = 0; /* Read to ODT off */
1274 unsigned int wodt_on = 0; /* Write to ODT on */
1275 unsigned int wodt_off = 0; /* Write to ODT off */
1277 #if defined(CONFIG_FSL_DDR3)
1278 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1279 rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1280 rodt_off = 4; /* 4 clocks */
1281 wodt_on = 1; /* 1 clocks */
1282 wodt_off = 4; /* 4 clocks */
1285 ddr->timing_cfg_5 = (0
1286 | ((rodt_on & 0x1f) << 24)
1287 | ((rodt_off & 0x7) << 20)
1288 | ((wodt_on & 0x1f) << 12)
1289 | ((wodt_off & 0x7) << 8)
1291 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1294 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1295 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1297 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1298 /* Normal Operation Full Calibration Time (tZQoper) */
1299 unsigned int zqoper = 0;
1300 /* Normal Operation Short Calibration Time (tZQCS) */
1301 unsigned int zqcs = 0;
1304 zqinit = 9; /* 512 clocks */
1305 zqoper = 8; /* 256 clocks */
1306 zqcs = 6; /* 64 clocks */
1309 ddr->ddr_zq_cntl = (0
1310 | ((zq_en & 0x1) << 31)
1311 | ((zqinit & 0xF) << 24)
1312 | ((zqoper & 0xF) << 16)
1313 | ((zqcs & 0xF) << 8)
1315 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1318 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1319 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1320 const memctl_options_t *popts)
1323 * First DQS pulse rising edge after margining mode
1324 * is programmed (tWL_MRD)
1326 unsigned int wrlvl_mrd = 0;
1327 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1328 unsigned int wrlvl_odten = 0;
1329 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1330 unsigned int wrlvl_dqsen = 0;
1331 /* WRLVL_SMPL: Write leveling sample time */
1332 unsigned int wrlvl_smpl = 0;
1333 /* WRLVL_WLR: Write leveling repeition time */
1334 unsigned int wrlvl_wlr = 0;
1335 /* WRLVL_START: Write leveling start time */
1336 unsigned int wrlvl_start = 0;
1338 /* suggest enable write leveling for DDR3 due to fly-by topology */
1340 /* tWL_MRD min = 40 nCK, we set it 64 */
1344 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1347 * Write leveling sample time at least need 6 clocks
1348 * higher than tWLO to allow enough time for progagation
1349 * delay and sampling the prime data bits.
1353 * Write leveling repetition time
1354 * at least tWLO + 6 clocks clocks
1359 * Write leveling start time
1360 * The value use for the DQS_ADJUST for the first sample
1361 * when write leveling is enabled. It probably needs to be
1362 * overriden per platform.
1366 * Override the write leveling sample and start time
1367 * according to specific board
1369 if (popts->wrlvl_override) {
1370 wrlvl_smpl = popts->wrlvl_sample;
1371 wrlvl_start = popts->wrlvl_start;
1375 ddr->ddr_wrlvl_cntl = (0
1376 | ((wrlvl_en & 0x1) << 31)
1377 | ((wrlvl_mrd & 0x7) << 24)
1378 | ((wrlvl_odten & 0x7) << 20)
1379 | ((wrlvl_dqsen & 0x7) << 16)
1380 | ((wrlvl_smpl & 0xf) << 12)
1381 | ((wrlvl_wlr & 0x7) << 8)
1382 | ((wrlvl_start & 0x1F) << 0)
1384 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1385 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
1386 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
1387 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
1388 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
1392 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1393 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1395 /* Self Refresh Idle Threshold */
1396 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1399 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1401 if (popts->addr_hash) {
1402 ddr->ddr_eor = 0x40000000; /* address hash enable */
1403 puts("Address hashing enabled.\n");
1407 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1409 ddr->ddr_cdr1 = popts->ddr_cdr1;
1410 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1413 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1415 ddr->ddr_cdr2 = popts->ddr_cdr2;
1416 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
1420 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1422 unsigned int res = 0;
1425 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1426 * not set at the same time.
1428 if (ddr->ddr_sdram_cfg & 0x10000000
1429 && ddr->ddr_sdram_cfg & 0x00008000) {
1430 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1431 " should not be set at the same time.\n");
1439 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1440 fsl_ddr_cfg_regs_t *ddr,
1441 const common_timing_params_t *common_dimm,
1442 const dimm_params_t *dimm_params,
1443 unsigned int dbw_cap_adj,
1444 unsigned int size_only)
1447 unsigned int cas_latency;
1448 unsigned int additive_latency;
1451 unsigned int wrlvl_en;
1452 unsigned int ip_rev = 0;
1453 unsigned int unq_mrs_en = 0;
1456 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1458 if (common_dimm == NULL) {
1459 printf("Error: subset DIMM params struct null pointer\n");
1464 * Process overrides first.
1466 * FIXME: somehow add dereated caslat to this
1468 cas_latency = (popts->cas_latency_override)
1469 ? popts->cas_latency_override_value
1470 : common_dimm->lowest_common_SPD_caslat;
1472 additive_latency = (popts->additive_latency_override)
1473 ? popts->additive_latency_override_value
1474 : common_dimm->additive_latency;
1476 sr_it = (popts->auto_self_refresh_en)
1479 /* ZQ calibration */
1480 zq_en = (popts->zq_en) ? 1 : 0;
1481 /* write leveling */
1482 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1484 /* Chip Select Memory Bounds (CSn_BNDS) */
1485 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1486 unsigned long long ea, sa;
1487 unsigned int cs_per_dimm
1488 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1489 unsigned int dimm_number
1491 unsigned long long rank_density
1492 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
1494 if (dimm_params[dimm_number].n_ranks == 0) {
1495 debug("Skipping setup of CS%u "
1496 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1499 if (popts->memctl_interleaving) {
1500 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1501 case FSL_DDR_CS0_CS1_CS2_CS3:
1503 case FSL_DDR_CS0_CS1:
1504 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1508 case FSL_DDR_CS2_CS3:
1514 sa = common_dimm->base_address;
1515 ea = sa + common_dimm->total_mem - 1;
1516 } else if (!popts->memctl_interleaving) {
1518 * If memory interleaving between controllers is NOT
1519 * enabled, the starting address for each memory
1520 * controller is distinct. However, because rank
1521 * interleaving is enabled, the starting and ending
1522 * addresses of the total memory on that memory
1523 * controller needs to be programmed into its
1524 * respective CS0_BNDS.
1526 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1527 case FSL_DDR_CS0_CS1_CS2_CS3:
1528 sa = common_dimm->base_address;
1529 ea = sa + common_dimm->total_mem - 1;
1531 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1532 if ((i >= 2) && (dimm_number == 0)) {
1533 sa = dimm_params[dimm_number].base_address +
1535 ea = sa + 2 * rank_density - 1;
1537 sa = dimm_params[dimm_number].base_address;
1538 ea = sa + 2 * rank_density - 1;
1541 case FSL_DDR_CS0_CS1:
1542 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1543 sa = dimm_params[dimm_number].base_address;
1544 ea = sa + rank_density - 1;
1546 sa += (i % cs_per_dimm) * rank_density;
1547 ea += (i % cs_per_dimm) * rank_density;
1555 case FSL_DDR_CS2_CS3:
1556 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1557 sa = dimm_params[dimm_number].base_address;
1558 ea = sa + rank_density - 1;
1560 sa += (i % cs_per_dimm) * rank_density;
1561 ea += (i % cs_per_dimm) * rank_density;
1567 ea += (rank_density >> dbw_cap_adj);
1569 default: /* No bank(chip-select) interleaving */
1570 sa = dimm_params[dimm_number].base_address;
1571 ea = sa + rank_density - 1;
1572 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1573 sa += (i % cs_per_dimm) * rank_density;
1574 ea += (i % cs_per_dimm) * rank_density;
1587 ddr->cs[i].bnds = (0
1588 | ((sa & 0xFFF) << 16)/* starting address MSB */
1589 | ((ea & 0xFFF) << 0) /* ending address MSB */
1592 /* setting bnds to 0xffffffff for inactive CS */
1593 ddr->cs[i].bnds = 0xffffffff;
1596 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1597 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1598 set_csn_config_2(i, ddr);
1602 * In the case we only need to compute the ddr sdram size, we only need
1603 * to set csn registers, so return from here.
1608 set_ddr_eor(ddr, popts);
1610 #if !defined(CONFIG_FSL_DDR1)
1611 set_timing_cfg_0(ddr, popts, dimm_params);
1614 set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
1615 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1616 set_timing_cfg_2(ddr, popts, common_dimm,
1617 cas_latency, additive_latency);
1619 set_ddr_cdr1(ddr, popts);
1620 set_ddr_cdr2(ddr, popts);
1621 set_ddr_sdram_cfg(ddr, popts, common_dimm);
1622 ip_rev = fsl_ddr_get_version();
1623 if (ip_rev > 0x40400)
1626 set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1627 set_ddr_sdram_mode(ddr, popts, common_dimm,
1628 cas_latency, additive_latency, unq_mrs_en);
1629 set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
1630 set_ddr_sdram_interval(ddr, popts, common_dimm);
1631 set_ddr_data_init(ddr);
1632 set_ddr_sdram_clk_cntl(ddr, popts);
1633 set_ddr_init_addr(ddr);
1634 set_ddr_init_ext_addr(ddr);
1635 set_timing_cfg_4(ddr, popts);
1636 set_timing_cfg_5(ddr, cas_latency);
1638 set_ddr_zq_cntl(ddr, zq_en);
1639 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1641 set_ddr_sr_cntr(ddr, sr_it);
1643 set_ddr_sdram_rcw(ddr, popts, common_dimm);
1645 #ifdef CONFIG_SYS_FSL_DDR_EMU
1646 /* disble DDR training for emulator */
1647 ddr->debug[2] = 0x00000400;
1648 ddr->debug[4] = 0xff800000;
1650 return check_fsl_memctl_config_regs(ddr);