git.sur5r.net Git - u-boot/blob - arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 /*
  11  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  12  * Based on code from spd_sdram.c
  13  * Author: James Yang [at freescale.com]
  14  */
  15
  16 #include <common.h>
  17 #include <asm/fsl_ddr_sdram.h>
  18
  19 #include "ddr.h"
  20
  21 #ifdef CONFIG_MPC85xx
  22         #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
  23 #elif defined(CONFIG_MPC86xx)
  24         #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
  25 #else
  26         #error "Undefined _DDR_ADDR"
  27 #endif
  28
  29 u32 fsl_ddr_get_version(void)
  30 {
  31         ccsr_ddr_t *ddr;
  32         u32 ver_major_minor_errata;
  33
  34         ddr = (void *)_DDR_ADDR;
  35         ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
  36         ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
  37
  38         return ver_major_minor_errata;
  39 }
  40
  41 unsigned int picos_to_mclk(unsigned int picos);
  42
  43 /*
  44  * Determine Rtt value.
  45  *
  46  * This should likely be either board or controller specific.
  47  *
  48  * Rtt(nominal) - DDR2:
  49  *      0 = Rtt disabled
  50  *      1 = 75 ohm
  51  *      2 = 150 ohm
  52  *      3 = 50 ohm
  53  * Rtt(nominal) - DDR3:
  54  *      0 = Rtt disabled
  55  *      1 = 60 ohm
  56  *      2 = 120 ohm
  57  *      3 = 40 ohm
  58  *      4 = 20 ohm
  59  *      5 = 30 ohm
  60  *
  61  * FIXME: Apparently 8641 needs a value of 2
  62  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  63  *
  64  * FIXME: There was some effort down this line earlier:
  65  *
  66  *      unsigned int i;
  67  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  68  *              if (popts->dimmslot[i].num_valid_cs
  69  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  70  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  71  *                      rtt = 2;
  72  *                      break;
  73  *              }
  74  *      }
  75  */
  76 static inline int fsl_ddr_get_rtt(void)
  77 {
  78         int rtt;
  79
  80 #if defined(CONFIG_FSL_DDR1)
  81         rtt = 0;
  82 #elif defined(CONFIG_FSL_DDR2)
  83         rtt = 3;
  84 #else
  85         rtt = 0;
  86 #endif
  87
  88         return rtt;
  89 }
  90
  91 /*
  92  * compute the CAS write latency according to DDR3 spec
  93  * CWL = 5 if tCK >= 2.5ns
  94  *       6 if 2.5ns > tCK >= 1.875ns
  95  *       7 if 1.875ns > tCK >= 1.5ns
  96  *       8 if 1.5ns > tCK >= 1.25ns
  97  */
  98 static inline unsigned int compute_cas_write_latency(void)
  99 {
 100         unsigned int cwl;
 101         const unsigned int mclk_ps = get_memory_clk_period_ps();
 102
 103         if (mclk_ps >= 2500)
 104                 cwl = 5;
 105         else if (mclk_ps >= 1875)
 106                 cwl = 6;
 107         else if (mclk_ps >= 1500)
 108                 cwl = 7;
 109         else if (mclk_ps >= 1250)
 110                 cwl = 8;
 111         else
 112                 cwl = 8;
 113         return cwl;
 114 }
 115
 116 /* Chip Select Configuration (CSn_CONFIG) */
 117 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 118                                const memctl_options_t *popts,
 119                                const dimm_params_t *dimm_params)
 120 {
 121         unsigned int cs_n_en = 0; /* Chip Select enable */
 122         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 123         unsigned int intlv_ctl = 0; /* Interleaving control */
 124         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 125         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 126         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 127         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 128         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 129         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 130         int go_config = 0;
 131
 132         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 133         switch (i) {
 134         case 0:
 135                 if (dimm_params[dimm_number].n_ranks > 0) {
 136                         go_config = 1;
 137                         /* These fields only available in CS0_CONFIG */
 138                         intlv_en = popts->memctl_interleaving;
 139                         intlv_ctl = popts->memctl_interleaving_mode;
 140                 }
 141                 break;
 142         case 1:
 143                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 144                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 145                         go_config = 1;
 146                 break;
 147         case 2:
 148                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 149                    (dimm_number > 1 && dimm_params[dimm_number].n_ranks > 0))
 150                         go_config = 1;
 151                 break;
 152         case 3:
 153                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 154                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 155                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 156                         go_config = 1;
 157                 break;
 158         default:
 159                 break;
 160         }
 161         if (go_config) {
 162                 unsigned int n_banks_per_sdram_device;
 163                 cs_n_en = 1;
 164                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 165                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 166                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 167                 n_banks_per_sdram_device
 168                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 169                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 170                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 171                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 172         }
 173         ddr->cs[i].config = (0
 174                 | ((cs_n_en & 0x1) << 31)
 175                 | ((intlv_en & 0x3) << 29)
 176                 | ((intlv_ctl & 0xf) << 24)
 177                 | ((ap_n_en & 0x1) << 23)
 178
 179                 /* XXX: some implementation only have 1 bit starting at left */
 180                 | ((odt_rd_cfg & 0x7) << 20)
 181
 182                 /* XXX: Some implementation only have 1 bit starting at left */
 183                 | ((odt_wr_cfg & 0x7) << 16)
 184
 185                 | ((ba_bits_cs_n & 0x3) << 14)
 186                 | ((row_bits_cs_n & 0x7) << 8)
 187                 | ((col_bits_cs_n & 0x7) << 0)
 188                 );
 189         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 190 }
 191
 192 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 193 /* FIXME: 8572 */
 194 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 195 {
 196         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 197
 198         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 199         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 200 }
 201
 202 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 203
 204 #if !defined(CONFIG_FSL_DDR1)
 205 /*
 206  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 207  *
 208  * Avoid writing for DDR I.  The new PQ38 DDR controller
 209  * dreams up non-zero default values to be backwards compatible.
 210  */
 211 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 212                                 const memctl_options_t *popts)
 213 {
 214         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 215         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 216         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 217         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 218         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 219
 220         /* Active powerdown exit timing (tXARD and tXARDS). */
 221         unsigned char act_pd_exit_mclk;
 222         /* Precharge powerdown exit timing (tXP). */
 223         unsigned char pre_pd_exit_mclk;
 224         /* ODT powerdown exit timing (tAXPD). */
 225         unsigned char taxpd_mclk;
 226         /* Mode register set cycle time (tMRD). */
 227         unsigned char tmrd_mclk;
 228
 229 #ifdef CONFIG_FSL_DDR3
 230         /*
 231          * (tXARD and tXARDS). Empirical?
 232          * The DDR3 spec has not tXARD,
 233          * we use the tXP instead of it.
 234          * tXP=max(3nCK, 7.5ns) for DDR3.
 235          * spec has not the tAXPD, we use
 236          * tAXPD=1, need design to confirm.
 237          */
 238         int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
 239         unsigned int data_rate = fsl_ddr_get_mem_data_rate();
 240         tmrd_mclk = 4;
 241         /* set the turnaround time */
 242         trwt_mclk = 1;
 243         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 244                 twrt_mclk = 1;
 245
 246         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 247                 act_pd_exit_mclk = 1;
 248                 pre_pd_exit_mclk = 1;
 249                 taxpd_mclk = 1;
 250         } else {
 251                 /* act_pd_exit_mclk = tXARD, see above */
 252                 act_pd_exit_mclk = picos_to_mclk(tXP);
 253                 /* Mode register MR0[A12] is '1' - fast exit */
 254                 pre_pd_exit_mclk = act_pd_exit_mclk;
 255                 taxpd_mclk = 1;
 256         }
 257 #else /* CONFIG_FSL_DDR2 */
 258         /*
 259          * (tXARD and tXARDS). Empirical?
 260          * tXARD = 2 for DDR2
 261          * tXP=2
 262          * tAXPD=8
 263          */
 264         act_pd_exit_mclk = 2;
 265         pre_pd_exit_mclk = 2;
 266         taxpd_mclk = 8;
 267         tmrd_mclk = 2;
 268 #endif
 269
 270         ddr->timing_cfg_0 = (0
 271                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 272                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 273                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 274                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 275                 | ((act_pd_exit_mclk & 0x7) << 20)  /* ACT_PD_EXIT */
 276                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 277                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 278                 | ((tmrd_mclk & 0xf) << 0)      /* MRS_CYC */
 279                 );
 280         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 281 }
 282 #endif  /* defined(CONFIG_FSL_DDR2) */
 283
 284 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 285 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 286                                const common_timing_params_t *common_dimm,
 287                                unsigned int cas_latency)
 288 {
 289         /* Extended Activate to precharge interval (tRAS) */
 290         unsigned int ext_acttopre = 0;
 291         unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
 292         unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
 293         unsigned int cntl_adj = 0; /* Control Adjust */
 294
 295         /* If the tRAS > 19 MCLK, we use the ext mode */
 296         if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
 297                 ext_acttopre = 1;
 298
 299         ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
 300
 301         /* If the CAS latency more than 8, use the ext mode */
 302         if (cas_latency > 8)
 303                 ext_caslat = 1;
 304
 305         ddr->timing_cfg_3 = (0
 306                 | ((ext_acttopre & 0x1) << 24)
 307                 | ((ext_refrec & 0xF) << 16)
 308                 | ((ext_caslat & 0x1) << 12)
 309                 | ((cntl_adj & 0x7) << 0)
 310                 );
 311         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 312 }
 313
 314 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 315 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 316                                const memctl_options_t *popts,
 317                                const common_timing_params_t *common_dimm,
 318                                unsigned int cas_latency)
 319 {
 320         /* Precharge-to-activate interval (tRP) */
 321         unsigned char pretoact_mclk;
 322         /* Activate to precharge interval (tRAS) */
 323         unsigned char acttopre_mclk;
 324         /*  Activate to read/write interval (tRCD) */
 325         unsigned char acttorw_mclk;
 326         /* CASLAT */
 327         unsigned char caslat_ctrl;
 328         /*  Refresh recovery time (tRFC) ; trfc_low */
 329         unsigned char refrec_ctrl;
 330         /* Last data to precharge minimum interval (tWR) */
 331         unsigned char wrrec_mclk;
 332         /* Activate-to-activate interval (tRRD) */
 333         unsigned char acttoact_mclk;
 334         /* Last write data pair to read command issue interval (tWTR) */
 335         unsigned char wrtord_mclk;
 336         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 337         static const u8 wrrec_table[] = {
 338                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 339
 340         pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
 341         acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
 342         acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
 343
 344         /*
 345          * Translate CAS Latency to a DDR controller field value:
 346          *
 347          *      CAS Lat DDR I   DDR II  Ctrl
 348          *      Clocks  SPD Bit SPD Bit Value
 349          *      ------- ------- ------- -----
 350          *      1.0     0               0001
 351          *      1.5     1               0010
 352          *      2.0     2       2       0011
 353          *      2.5     3               0100
 354          *      3.0     4       3       0101
 355          *      3.5     5               0110
 356          *      4.0             4       0111
 357          *      4.5                     1000
 358          *      5.0             5       1001
 359          */
 360 #if defined(CONFIG_FSL_DDR1)
 361         caslat_ctrl = (cas_latency + 1) & 0x07;
 362 #elif defined(CONFIG_FSL_DDR2)
 363         caslat_ctrl = 2 * cas_latency - 1;
 364 #else
 365         /*
 366          * if the CAS latency more than 8 cycle,
 367          * we need set extend bit for it at
 368          * TIMING_CFG_3[EXT_CASLAT]
 369          */
 370         if (cas_latency > 8)
 371                 cas_latency -= 8;
 372         caslat_ctrl = 2 * cas_latency - 1;
 373 #endif
 374
 375         refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
 376         wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
 377
 378         wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 379         if (popts->OTF_burst_chop_en)
 380                 wrrec_mclk += 2;
 381
 382         acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
 383         /*
 384          * JEDEC has min requirement for tRRD
 385          */
 386 #if defined(CONFIG_FSL_DDR3)
 387         if (acttoact_mclk < 4)
 388                 acttoact_mclk = 4;
 389 #endif
 390         wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
 391         /*
 392          * JEDEC has some min requirements for tWTR
 393          */
 394 #if defined(CONFIG_FSL_DDR2)
 395         if (wrtord_mclk < 2)
 396                 wrtord_mclk = 2;
 397 #elif defined(CONFIG_FSL_DDR3)
 398         if (wrtord_mclk < 4)
 399                 wrtord_mclk = 4;
 400 #endif
 401         if (popts->OTF_burst_chop_en)
 402                 wrtord_mclk += 2;
 403
 404         ddr->timing_cfg_1 = (0
 405                 | ((pretoact_mclk & 0x0F) << 28)
 406                 | ((acttopre_mclk & 0x0F) << 24)
 407                 | ((acttorw_mclk & 0xF) << 20)
 408                 | ((caslat_ctrl & 0xF) << 16)
 409                 | ((refrec_ctrl & 0xF) << 12)
 410                 | ((wrrec_mclk & 0x0F) << 8)
 411                 | ((acttoact_mclk & 0x07) << 4)
 412                 | ((wrtord_mclk & 0x07) << 0)
 413                 );
 414         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 415 }
 416
 417 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 418 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 419                                const memctl_options_t *popts,
 420                                const common_timing_params_t *common_dimm,
 421                                unsigned int cas_latency,
 422                                unsigned int additive_latency)
 423 {
 424         /* Additive latency */
 425         unsigned char add_lat_mclk;
 426         /* CAS-to-preamble override */
 427         unsigned short cpo;
 428         /* Write latency */
 429         unsigned char wr_lat;
 430         /*  Read to precharge (tRTP) */
 431         unsigned char rd_to_pre;
 432         /* Write command to write data strobe timing adjustment */
 433         unsigned char wr_data_delay;
 434         /* Minimum CKE pulse width (tCKE) */
 435         unsigned char cke_pls;
 436         /* Window for four activates (tFAW) */
 437         unsigned short four_act;
 438
 439         /* FIXME add check that this must be less than acttorw_mclk */
 440         add_lat_mclk = additive_latency;
 441         cpo = popts->cpo_override;
 442
 443 #if defined(CONFIG_FSL_DDR1)
 444         /*
 445          * This is a lie.  It should really be 1, but if it is
 446          * set to 1, bits overlap into the old controller's
 447          * otherwise unused ACSM field.  If we leave it 0, then
 448          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 449          */
 450         wr_lat = 0;
 451 #elif defined(CONFIG_FSL_DDR2)
 452         wr_lat = cas_latency - 1;
 453 #else
 454         wr_lat = compute_cas_write_latency();
 455 #endif
 456
 457         rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
 458         /*
 459          * JEDEC has some min requirements for tRTP
 460          */
 461 #if defined(CONFIG_FSL_DDR2)
 462         if (rd_to_pre  < 2)
 463                 rd_to_pre  = 2;
 464 #elif defined(CONFIG_FSL_DDR3)
 465         if (rd_to_pre < 4)
 466                 rd_to_pre = 4;
 467 #endif
 468         if (additive_latency)
 469                 rd_to_pre += additive_latency;
 470         if (popts->OTF_burst_chop_en)
 471                 rd_to_pre += 2; /* according to UM */
 472
 473         wr_data_delay = popts->write_data_delay;
 474         cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
 475         four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
 476
 477         ddr->timing_cfg_2 = (0
 478                 | ((add_lat_mclk & 0xf) << 28)
 479                 | ((cpo & 0x1f) << 23)
 480                 | ((wr_lat & 0xf) << 19)
 481                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 482                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 483                 | ((cke_pls & 0x7) << 6)
 484                 | ((four_act & 0x3f) << 0)
 485                 );
 486         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 487 }
 488
 489 /* DDR SDRAM Register Control Word */
 490 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 491                                const memctl_options_t *popts,
 492                                const common_timing_params_t *common_dimm)
 493 {
 494         if (common_dimm->all_DIMMs_registered
 495                 && !common_dimm->all_DIMMs_unbuffered) {
 496                 if (popts->rcw_override) {
 497                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 498                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 499                 } else {
 500                         ddr->ddr_sdram_rcw_1 =
 501                                 common_dimm->rcw[0] << 28 | \
 502                                 common_dimm->rcw[1] << 24 | \
 503                                 common_dimm->rcw[2] << 20 | \
 504                                 common_dimm->rcw[3] << 16 | \
 505                                 common_dimm->rcw[4] << 12 | \
 506                                 common_dimm->rcw[5] << 8 | \
 507                                 common_dimm->rcw[6] << 4 | \
 508                                 common_dimm->rcw[7];
 509                         ddr->ddr_sdram_rcw_2 =
 510                                 common_dimm->rcw[8] << 28 | \
 511                                 common_dimm->rcw[9] << 24 | \
 512                                 common_dimm->rcw[10] << 20 | \
 513                                 common_dimm->rcw[11] << 16 | \
 514                                 common_dimm->rcw[12] << 12 | \
 515                                 common_dimm->rcw[13] << 8 | \
 516                                 common_dimm->rcw[14] << 4 | \
 517                                 common_dimm->rcw[15];
 518                 }
 519                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 520                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 521         }
 522 }
 523
 524 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 525 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 526                                const memctl_options_t *popts,
 527                                const common_timing_params_t *common_dimm)
 528 {
 529         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 530         unsigned int sren;              /* Self refresh enable (during sleep) */
 531         unsigned int ecc_en;            /* ECC enable. */
 532         unsigned int rd_en;             /* Registered DIMM enable */
 533         unsigned int sdram_type;        /* Type of SDRAM */
 534         unsigned int dyn_pwr;           /* Dynamic power management mode */
 535         unsigned int dbw;               /* DRAM dta bus width */
 536         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 537         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 538         unsigned int threeT_en;         /* Enable 3T timing */
 539         unsigned int twoT_en;           /* Enable 2T timing */
 540         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 541         unsigned int x32_en = 0;        /* x32 enable */
 542         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 543         unsigned int hse;               /* Global half strength override */
 544         unsigned int mem_halt = 0;      /* memory controller halt */
 545         unsigned int bi = 0;            /* Bypass initialization */
 546
 547         mem_en = 1;
 548         sren = popts->self_refresh_in_sleep;
 549         if (common_dimm->all_DIMMs_ECC_capable) {
 550                 /* Allow setting of ECC only if all DIMMs are ECC. */
 551                 ecc_en = popts->ECC_mode;
 552         } else {
 553                 ecc_en = 0;
 554         }
 555
 556         if (common_dimm->all_DIMMs_registered
 557                 && !common_dimm->all_DIMMs_unbuffered) {
 558                 rd_en = 1;
 559                 twoT_en = 0;
 560         } else {
 561                 rd_en = 0;
 562                 twoT_en = popts->twoT_en;
 563         }
 564
 565         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 566
 567         dyn_pwr = popts->dynamic_power;
 568         dbw = popts->data_bus_width;
 569         /* 8-beat burst enable DDR-III case
 570          * we must clear it when use the on-the-fly mode,
 571          * must set it when use the 32-bits bus mode.
 572          */
 573         if (sdram_type == SDRAM_TYPE_DDR3) {
 574                 if (popts->burst_length == DDR_BL8)
 575                         eight_be = 1;
 576                 if (popts->burst_length == DDR_OTF)
 577                         eight_be = 0;
 578                 if (dbw == 0x1)
 579                         eight_be = 1;
 580         }
 581
 582         threeT_en = popts->threeT_en;
 583         ba_intlv_ctl = popts->ba_intlv_ctl;
 584         hse = popts->half_strength_driver_enable;
 585
 586         ddr->ddr_sdram_cfg = (0
 587                         | ((mem_en & 0x1) << 31)
 588                         | ((sren & 0x1) << 30)
 589                         | ((ecc_en & 0x1) << 29)
 590                         | ((rd_en & 0x1) << 28)
 591                         | ((sdram_type & 0x7) << 24)
 592                         | ((dyn_pwr & 0x1) << 21)
 593                         | ((dbw & 0x3) << 19)
 594                         | ((eight_be & 0x1) << 18)
 595                         | ((ncap & 0x1) << 17)
 596                         | ((threeT_en & 0x1) << 16)
 597                         | ((twoT_en & 0x1) << 15)
 598                         | ((ba_intlv_ctl & 0x7F) << 8)
 599                         | ((x32_en & 0x1) << 5)
 600                         | ((pchb8 & 0x1) << 4)
 601                         | ((hse & 0x1) << 3)
 602                         | ((mem_halt & 0x1) << 1)
 603                         | ((bi & 0x1) << 0)
 604                         );
 605         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 606 }
 607
 608 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 609 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 610                                const memctl_options_t *popts,
 611                                const unsigned int unq_mrs_en)
 612 {
 613         unsigned int frc_sr = 0;        /* Force self refresh */
 614         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 615         unsigned int dll_rst_dis;       /* DLL reset disable */
 616         unsigned int dqs_cfg;           /* DQS configuration */
 617         unsigned int odt_cfg;           /* ODT configuration */
 618         unsigned int num_pr;            /* Number of posted refreshes */
 619         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 620         unsigned int ap_en;             /* Address Parity Enable */
 621         unsigned int d_init;            /* DRAM data initialization */
 622         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 623         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 624         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 625
 626         dll_rst_dis = 1;        /* Make this configurable */
 627         dqs_cfg = popts->DQS_config;
 628         if (popts->cs_local_opts[0].odt_rd_cfg
 629             || popts->cs_local_opts[0].odt_wr_cfg) {
 630                 /* FIXME */
 631                 odt_cfg = 2;
 632         } else {
 633                 odt_cfg = 0;
 634         }
 635
 636         num_pr = 1;     /* Make this configurable */
 637
 638         /*
 639          * 8572 manual says
 640          *     {TIMING_CFG_1[PRETOACT]
 641          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 642          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 643          *      << DDR_SDRAM_INTERVAL[REFINT]
 644          */
 645 #if defined(CONFIG_FSL_DDR3)
 646         obc_cfg = popts->OTF_burst_chop_en;
 647 #else
 648         obc_cfg = 0;
 649 #endif
 650
 651         if (popts->registered_dimm_en) {
 652                 rcw_en = 1;
 653                 ap_en = popts->ap_en;
 654         } else {
 655                 rcw_en = 0;
 656                 ap_en = 0;
 657         }
 658
 659 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 660         /* Use the DDR controller to auto initialize memory. */
 661         d_init = popts->ECC_init_using_memctl;
 662         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 663         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 664 #else
 665         /* Memory will be initialized via DMA, or not at all. */
 666         d_init = 0;
 667 #endif
 668
 669 #if defined(CONFIG_FSL_DDR3)
 670         md_en = popts->mirrored_dimm;
 671 #endif
 672         qd_en = popts->quad_rank_present ? 1 : 0;
 673         ddr->ddr_sdram_cfg_2 = (0
 674                 | ((frc_sr & 0x1) << 31)
 675                 | ((sr_ie & 0x1) << 30)
 676                 | ((dll_rst_dis & 0x1) << 29)
 677                 | ((dqs_cfg & 0x3) << 26)
 678                 | ((odt_cfg & 0x3) << 21)
 679                 | ((num_pr & 0xf) << 12)
 680                 | (qd_en << 9)
 681                 | (unq_mrs_en << 8)
 682                 | ((obc_cfg & 0x1) << 6)
 683                 | ((ap_en & 0x1) << 5)
 684                 | ((d_init & 0x1) << 4)
 685 #ifdef CONFIG_FSL_DDR3
 686                 | ((rcw_en & 0x1) << 2)
 687 #endif
 688                 | ((md_en & 0x1) << 0)
 689                 );
 690         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 691 }
 692
 693 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 694 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 695                                 const memctl_options_t *popts,
 696                                 const unsigned int unq_mrs_en)
 697 {
 698         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 699         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 700
 701 #if defined(CONFIG_FSL_DDR3)
 702         int i;
 703         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 704         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 705         unsigned int asr = 0;   /* auto self-refresh disable */
 706         unsigned int cwl = compute_cas_write_latency() - 5;
 707         unsigned int pasr = 0;  /* partial array self refresh disable */
 708
 709         if (popts->rtt_override)
 710                 rtt_wr = popts->rtt_wr_override_value;
 711         else
 712                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 713         esdmode2 = (0
 714                 | ((rtt_wr & 0x3) << 9)
 715                 | ((srt & 0x1) << 7)
 716                 | ((asr & 0x1) << 6)
 717                 | ((cwl & 0x7) << 3)
 718                 | ((pasr & 0x7) << 0));
 719 #endif
 720         ddr->ddr_sdram_mode_2 = (0
 721                                  | ((esdmode2 & 0xFFFF) << 16)
 722                                  | ((esdmode3 & 0xFFFF) << 0)
 723                                  );
 724         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 725
 726 #ifdef CONFIG_FSL_DDR3
 727         if (unq_mrs_en) {       /* unique mode registers are supported */
 728                 for (i = 1; i < 4; i++) {
 729                         if (popts->rtt_override)
 730                                 rtt_wr = popts->rtt_wr_override_value;
 731                         else
 732                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 733
 734                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 735                         esdmode2 |= (rtt_wr & 0x3) << 9;
 736                         switch (i) {
 737                         case 1:
 738                                 ddr->ddr_sdram_mode_4 = (0
 739                                         | ((esdmode2 & 0xFFFF) << 16)
 740                                         | ((esdmode3 & 0xFFFF) << 0)
 741                                         );
 742                                 break;
 743                         case 2:
 744                                 ddr->ddr_sdram_mode_6 = (0
 745                                         | ((esdmode2 & 0xFFFF) << 16)
 746                                         | ((esdmode3 & 0xFFFF) << 0)
 747                                         );
 748                                 break;
 749                         case 3:
 750                                 ddr->ddr_sdram_mode_8 = (0
 751                                         | ((esdmode2 & 0xFFFF) << 16)
 752                                         | ((esdmode3 & 0xFFFF) << 0)
 753                                         );
 754                                 break;
 755                         }
 756                 }
 757                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
 758                         ddr->ddr_sdram_mode_4);
 759                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
 760                         ddr->ddr_sdram_mode_6);
 761                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
 762                         ddr->ddr_sdram_mode_8);
 763         }
 764 #endif
 765 }
 766
 767 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
 768 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 769                                const memctl_options_t *popts,
 770                                const common_timing_params_t *common_dimm)
 771 {
 772         unsigned int refint;    /* Refresh interval */
 773         unsigned int bstopre;   /* Precharge interval */
 774
 775         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
 776
 777         bstopre = popts->bstopre;
 778
 779         /* refint field used 0x3FFF in earlier controllers */
 780         ddr->ddr_sdram_interval = (0
 781                                    | ((refint & 0xFFFF) << 16)
 782                                    | ((bstopre & 0x3FFF) << 0)
 783                                    );
 784         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 785 }
 786
 787 #if defined(CONFIG_FSL_DDR3)
 788 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 789 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 790                                const memctl_options_t *popts,
 791                                const common_timing_params_t *common_dimm,
 792                                unsigned int cas_latency,
 793                                unsigned int additive_latency,
 794                                const unsigned int unq_mrs_en)
 795 {
 796         unsigned short esdmode;         /* Extended SDRAM mode */
 797         unsigned short sdmode;          /* SDRAM mode */
 798
 799         /* Mode Register - MR1 */
 800         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
 801         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
 802         unsigned int rtt;
 803         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
 804         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
 805         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
 806         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 807                                                        1=Disable (Test/Debug) */
 808
 809         /* Mode Register - MR0 */
 810         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
 811         unsigned int wr;        /* Write Recovery */
 812         unsigned int dll_rst;   /* DLL Reset */
 813         unsigned int mode;      /* Normal=0 or Test=1 */
 814         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
 815         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
 816         unsigned int bt;
 817         unsigned int bl;        /* BL: Burst Length */
 818
 819         unsigned int wr_mclk;
 820         /*
 821          * DDR_SDRAM_MODE doesn't support 9,11,13,15
 822          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
 823          * for this table
 824          */
 825         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
 826
 827         const unsigned int mclk_ps = get_memory_clk_period_ps();
 828         int i;
 829
 830         if (popts->rtt_override)
 831                 rtt = popts->rtt_override_value;
 832         else
 833                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
 834
 835         if (additive_latency == (cas_latency - 1))
 836                 al = 1;
 837         if (additive_latency == (cas_latency - 2))
 838                 al = 2;
 839
 840         if (popts->quad_rank_present)
 841                 dic = 1;        /* output driver impedance 240/7 ohm */
 842
 843         /*
 844          * The esdmode value will also be used for writing
 845          * MR1 during write leveling for DDR3, although the
 846          * bits specifically related to the write leveling
 847          * scheme will be handled automatically by the DDR
 848          * controller. so we set the wrlvl_en = 0 here.
 849          */
 850         esdmode = (0
 851                 | ((qoff & 0x1) << 12)
 852                 | ((tdqs_en & 0x1) << 11)
 853                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 854                 | ((wrlvl_en & 0x1) << 7)
 855                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 856                 | ((dic & 0x2) << 4)   /* DIC field is split */
 857                 | ((al & 0x3) << 3)
 858                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 859                 | ((dic & 0x1) << 1)   /* DIC field is split */
 860                 | ((dll_en & 0x1) << 0)
 861                 );
 862
 863         /*
 864          * DLL control for precharge PD
 865          * 0=slow exit DLL off (tXPDLL)
 866          * 1=fast exit DLL on (tXP)
 867          */
 868         dll_on = 1;
 869
 870         wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
 871         wr = wr_table[wr_mclk - 5];
 872
 873         dll_rst = 0;    /* dll no reset */
 874         mode = 0;       /* normal mode */
 875
 876         /* look up table to get the cas latency bits */
 877         if (cas_latency >= 5 && cas_latency <= 11) {
 878                 unsigned char cas_latency_table[7] = {
 879                         0x2,    /* 5 clocks */
 880                         0x4,    /* 6 clocks */
 881                         0x6,    /* 7 clocks */
 882                         0x8,    /* 8 clocks */
 883                         0xa,    /* 9 clocks */
 884                         0xc,    /* 10 clocks */
 885                         0xe     /* 11 clocks */
 886                 };
 887                 caslat = cas_latency_table[cas_latency - 5];
 888         }
 889         bt = 0; /* Nibble sequential */
 890
 891         switch (popts->burst_length) {
 892         case DDR_BL8:
 893                 bl = 0;
 894                 break;
 895         case DDR_OTF:
 896                 bl = 1;
 897                 break;
 898         case DDR_BC4:
 899                 bl = 2;
 900                 break;
 901         default:
 902                 printf("Error: invalid burst length of %u specified. "
 903                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
 904                         popts->burst_length);
 905                 bl = 1;
 906                 break;
 907         }
 908
 909         sdmode = (0
 910                   | ((dll_on & 0x1) << 12)
 911                   | ((wr & 0x7) << 9)
 912                   | ((dll_rst & 0x1) << 8)
 913                   | ((mode & 0x1) << 7)
 914                   | (((caslat >> 1) & 0x7) << 4)
 915                   | ((bt & 0x1) << 3)
 916                   | ((bl & 0x3) << 0)
 917                   );
 918
 919         ddr->ddr_sdram_mode = (0
 920                                | ((esdmode & 0xFFFF) << 16)
 921                                | ((sdmode & 0xFFFF) << 0)
 922                                );
 923
 924         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
 925
 926         if (unq_mrs_en) {       /* unique mode registers are supported */
 927                 for (i = 1; i < 4; i++) {
 928                         if (popts->rtt_override)
 929                                 rtt = popts->rtt_override_value;
 930                         else
 931                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
 932
 933                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
 934                         esdmode |= (0
 935                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 936                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 937                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 938                                 );
 939                         switch (i) {
 940                         case 1:
 941                                 ddr->ddr_sdram_mode_3 = (0
 942                                        | ((esdmode & 0xFFFF) << 16)
 943                                        | ((sdmode & 0xFFFF) << 0)
 944                                        );
 945                                 break;
 946                         case 2:
 947                                 ddr->ddr_sdram_mode_5 = (0
 948                                        | ((esdmode & 0xFFFF) << 16)
 949                                        | ((sdmode & 0xFFFF) << 0)
 950                                        );
 951                                 break;
 952                         case 3:
 953                                 ddr->ddr_sdram_mode_7 = (0
 954                                        | ((esdmode & 0xFFFF) << 16)
 955                                        | ((sdmode & 0xFFFF) << 0)
 956                                        );
 957                                 break;
 958                         }
 959                 }
 960                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
 961                         ddr->ddr_sdram_mode_3);
 962                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
 963                         ddr->ddr_sdram_mode_5);
 964                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
 965                         ddr->ddr_sdram_mode_5);
 966         }
 967 }
 968
 969 #else /* !CONFIG_FSL_DDR3 */
 970
 971 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 972 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 973                                const memctl_options_t *popts,
 974                                const common_timing_params_t *common_dimm,
 975                                unsigned int cas_latency,
 976                                unsigned int additive_latency,
 977                                const unsigned int unq_mrs_en)
 978 {
 979         unsigned short esdmode;         /* Extended SDRAM mode */
 980         unsigned short sdmode;          /* SDRAM mode */
 981
 982         /*
 983          * FIXME: This ought to be pre-calculated in a
 984          * technology-specific routine,
 985          * e.g. compute_DDR2_mode_register(), and then the
 986          * sdmode and esdmode passed in as part of common_dimm.
 987          */
 988
 989         /* Extended Mode Register */
 990         unsigned int mrs = 0;           /* Mode Register Set */
 991         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
 992         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
 993         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
 994         unsigned int ocd = 0;           /* 0x0=OCD not supported,
 995                                            0x7=OCD default state */
 996         unsigned int rtt;
 997         unsigned int al;                /* Posted CAS# additive latency (AL) */
 998         unsigned int ods = 0;           /* Output Drive Strength:
 999                                                 0 = Full strength (18ohm)
1000                                                 1 = Reduced strength (4ohm) */
1001         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1002                                                        1=Disable (Test/Debug) */
1003
1004         /* Mode Register (MR) */
1005         unsigned int mr;        /* Mode Register Definition */
1006         unsigned int pd;        /* Power-Down Mode */
1007         unsigned int wr;        /* Write Recovery */
1008         unsigned int dll_res;   /* DLL Reset */
1009         unsigned int mode;      /* Normal=0 or Test=1 */
1010         unsigned int caslat = 0;/* CAS# latency */
1011         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1012         unsigned int bt;
1013         unsigned int bl;        /* BL: Burst Length */
1014
1015 #if defined(CONFIG_FSL_DDR2)
1016         const unsigned int mclk_ps = get_memory_clk_period_ps();
1017 #endif
1018
1019         rtt = fsl_ddr_get_rtt();
1020
1021         al = additive_latency;
1022
1023         esdmode = (0
1024                 | ((mrs & 0x3) << 14)
1025                 | ((outputs & 0x1) << 12)
1026                 | ((rdqs_en & 0x1) << 11)
1027                 | ((dqs_en & 0x1) << 10)
1028                 | ((ocd & 0x7) << 7)
1029                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1030                 | ((al & 0x7) << 3)
1031                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1032                 | ((ods & 0x1) << 1)
1033                 | ((dll_en & 0x1) << 0)
1034                 );
1035
1036         mr = 0;          /* FIXME: CHECKME */
1037
1038         /*
1039          * 0 = Fast Exit (Normal)
1040          * 1 = Slow Exit (Low Power)
1041          */
1042         pd = 0;
1043
1044 #if defined(CONFIG_FSL_DDR1)
1045         wr = 0;       /* Historical */
1046 #elif defined(CONFIG_FSL_DDR2)
1047         wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
1048 #endif
1049         dll_res = 0;
1050         mode = 0;
1051
1052 #if defined(CONFIG_FSL_DDR1)
1053         if (1 <= cas_latency && cas_latency <= 4) {
1054                 unsigned char mode_caslat_table[4] = {
1055                         0x5,    /* 1.5 clocks */
1056                         0x2,    /* 2.0 clocks */
1057                         0x6,    /* 2.5 clocks */
1058                         0x3     /* 3.0 clocks */
1059                 };
1060                 caslat = mode_caslat_table[cas_latency - 1];
1061         } else {
1062                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1063         }
1064 #elif defined(CONFIG_FSL_DDR2)
1065         caslat = cas_latency;
1066 #endif
1067         bt = 0;
1068
1069         switch (popts->burst_length) {
1070         case DDR_BL4:
1071                 bl = 2;
1072                 break;
1073         case DDR_BL8:
1074                 bl = 3;
1075                 break;
1076         default:
1077                 printf("Error: invalid burst length of %u specified. "
1078                         " Defaulting to 4 beats.\n",
1079                         popts->burst_length);
1080                 bl = 2;
1081                 break;
1082         }
1083
1084         sdmode = (0
1085                   | ((mr & 0x3) << 14)
1086                   | ((pd & 0x1) << 12)
1087                   | ((wr & 0x7) << 9)
1088                   | ((dll_res & 0x1) << 8)
1089                   | ((mode & 0x1) << 7)
1090                   | ((caslat & 0x7) << 4)
1091                   | ((bt & 0x1) << 3)
1092                   | ((bl & 0x7) << 0)
1093                   );
1094
1095         ddr->ddr_sdram_mode = (0
1096                                | ((esdmode & 0xFFFF) << 16)
1097                                | ((sdmode & 0xFFFF) << 0)
1098                                );
1099         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1100 }
1101 #endif
1102
1103 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1104 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1105 {
1106         unsigned int init_value;        /* Initialization value */
1107
1108         init_value = 0xDEADBEEF;
1109         ddr->ddr_data_init = init_value;
1110 }
1111
1112 /*
1113  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1114  * The old controller on the 8540/60 doesn't have this register.
1115  * Hope it's OK to set it (to 0) anyway.
1116  */
1117 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1118                                          const memctl_options_t *popts)
1119 {
1120         unsigned int clk_adjust;        /* Clock adjust */
1121
1122         clk_adjust = popts->clk_adjust;
1123         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1124         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1125 }
1126
1127 /* DDR Initialization Address (DDR_INIT_ADDR) */
1128 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1129 {
1130         unsigned int init_addr = 0;     /* Initialization address */
1131
1132         ddr->ddr_init_addr = init_addr;
1133 }
1134
1135 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1136 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1137 {
1138         unsigned int uia = 0;   /* Use initialization address */
1139         unsigned int init_ext_addr = 0; /* Initialization address */
1140
1141         ddr->ddr_init_ext_addr = (0
1142                                   | ((uia & 0x1) << 31)
1143                                   | (init_ext_addr & 0xF)
1144                                   );
1145 }
1146
1147 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1148 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1149                                 const memctl_options_t *popts)
1150 {
1151         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1152         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1153         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1154         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1155         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1156
1157 #if defined(CONFIG_FSL_DDR3)
1158         if (popts->burst_length == DDR_BL8) {
1159                 /* We set BL/2 for fixed BL8 */
1160                 rrt = 0;        /* BL/2 clocks */
1161                 wwt = 0;        /* BL/2 clocks */
1162         } else {
1163                 /* We need to set BL/2 + 2 to BC4 and OTF */
1164                 rrt = 2;        /* BL/2 + 2 clocks */
1165                 wwt = 2;        /* BL/2 + 2 clocks */
1166         }
1167         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1168 #endif
1169         ddr->timing_cfg_4 = (0
1170                              | ((rwt & 0xf) << 28)
1171                              | ((wrt & 0xf) << 24)
1172                              | ((rrt & 0xf) << 20)
1173                              | ((wwt & 0xf) << 16)
1174                              | (dll_lock & 0x3)
1175                              );
1176         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1177 }
1178
1179 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1180 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1181 {
1182         unsigned int rodt_on = 0;       /* Read to ODT on */
1183         unsigned int rodt_off = 0;      /* Read to ODT off */
1184         unsigned int wodt_on = 0;       /* Write to ODT on */
1185         unsigned int wodt_off = 0;      /* Write to ODT off */
1186
1187 #if defined(CONFIG_FSL_DDR3)
1188         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1189         rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1190         rodt_off = 4;   /*  4 clocks */
1191         wodt_on = 1;    /*  1 clocks */
1192         wodt_off = 4;   /*  4 clocks */
1193 #endif
1194
1195         ddr->timing_cfg_5 = (0
1196                              | ((rodt_on & 0x1f) << 24)
1197                              | ((rodt_off & 0x7) << 20)
1198                              | ((wodt_on & 0x1f) << 12)
1199                              | ((wodt_off & 0x7) << 8)
1200                              );
1201         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1202 }
1203
1204 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1205 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1206 {
1207         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1208         /* Normal Operation Full Calibration Time (tZQoper) */
1209         unsigned int zqoper = 0;
1210         /* Normal Operation Short Calibration Time (tZQCS) */
1211         unsigned int zqcs = 0;
1212
1213         if (zq_en) {
1214                 zqinit = 9;     /* 512 clocks */
1215                 zqoper = 8;     /* 256 clocks */
1216                 zqcs = 6;       /* 64 clocks */
1217         }
1218
1219         ddr->ddr_zq_cntl = (0
1220                             | ((zq_en & 0x1) << 31)
1221                             | ((zqinit & 0xF) << 24)
1222                             | ((zqoper & 0xF) << 16)
1223                             | ((zqcs & 0xF) << 8)
1224                             );
1225         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1226 }
1227
1228 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1229 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1230                                 const memctl_options_t *popts)
1231 {
1232         /*
1233          * First DQS pulse rising edge after margining mode
1234          * is programmed (tWL_MRD)
1235          */
1236         unsigned int wrlvl_mrd = 0;
1237         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1238         unsigned int wrlvl_odten = 0;
1239         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1240         unsigned int wrlvl_dqsen = 0;
1241         /* WRLVL_SMPL: Write leveling sample time */
1242         unsigned int wrlvl_smpl = 0;
1243         /* WRLVL_WLR: Write leveling repeition time */
1244         unsigned int wrlvl_wlr = 0;
1245         /* WRLVL_START: Write leveling start time */
1246         unsigned int wrlvl_start = 0;
1247
1248         /* suggest enable write leveling for DDR3 due to fly-by topology */
1249         if (wrlvl_en) {
1250                 /* tWL_MRD min = 40 nCK, we set it 64 */
1251                 wrlvl_mrd = 0x6;
1252                 /* tWL_ODTEN 128 */
1253                 wrlvl_odten = 0x7;
1254                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1255                 wrlvl_dqsen = 0x5;
1256                 /*
1257                  * Write leveling sample time at least need 6 clocks
1258                  * higher than tWLO to allow enough time for progagation
1259                  * delay and sampling the prime data bits.
1260                  */
1261                 wrlvl_smpl = 0xf;
1262                 /*
1263                  * Write leveling repetition time
1264                  * at least tWLO + 6 clocks clocks
1265                  * we set it 64
1266                  */
1267                 wrlvl_wlr = 0x6;
1268                 /*
1269                  * Write leveling start time
1270                  * The value use for the DQS_ADJUST for the first sample
1271                  * when write leveling is enabled. It probably needs to be
1272                  * overriden per platform.
1273                  */
1274                 wrlvl_start = 0x8;
1275                 /*
1276                  * Override the write leveling sample and start time
1277                  * according to specific board
1278                  */
1279                 if (popts->wrlvl_override) {
1280                         wrlvl_smpl = popts->wrlvl_sample;
1281                         wrlvl_start = popts->wrlvl_start;
1282                 }
1283         }
1284
1285         ddr->ddr_wrlvl_cntl = (0
1286                                | ((wrlvl_en & 0x1) << 31)
1287                                | ((wrlvl_mrd & 0x7) << 24)
1288                                | ((wrlvl_odten & 0x7) << 20)
1289                                | ((wrlvl_dqsen & 0x7) << 16)
1290                                | ((wrlvl_smpl & 0xf) << 12)
1291                                | ((wrlvl_wlr & 0x7) << 8)
1292                                | ((wrlvl_start & 0x1F) << 0)
1293                                );
1294         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1295 }
1296
1297 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1298 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1299 {
1300         /* Self Refresh Idle Threshold */
1301         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1302 }
1303
1304 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1305 {
1306         if (popts->addr_hash) {
1307                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
1308                 puts("Addess hashing enabled.\n");
1309         }
1310 }
1311
1312 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1313 {
1314         ddr->ddr_cdr1 = popts->ddr_cdr1;
1315         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1316 }
1317
1318 unsigned int
1319 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1320 {
1321         unsigned int res = 0;
1322
1323         /*
1324          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1325          * not set at the same time.
1326          */
1327         if (ddr->ddr_sdram_cfg & 0x10000000
1328             && ddr->ddr_sdram_cfg & 0x00008000) {
1329                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1330                                 " should not be set at the same time.\n");
1331                 res++;
1332         }
1333
1334         return res;
1335 }
1336
1337 unsigned int
1338 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1339                                fsl_ddr_cfg_regs_t *ddr,
1340                                const common_timing_params_t *common_dimm,
1341                                const dimm_params_t *dimm_params,
1342                                unsigned int dbw_cap_adj,
1343                                unsigned int size_only)
1344 {
1345         unsigned int i;
1346         unsigned int cas_latency;
1347         unsigned int additive_latency;
1348         unsigned int sr_it;
1349         unsigned int zq_en;
1350         unsigned int wrlvl_en;
1351         unsigned int ip_rev = 0;
1352         unsigned int unq_mrs_en = 0;
1353         int cs_en = 1;
1354
1355         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1356
1357         if (common_dimm == NULL) {
1358                 printf("Error: subset DIMM params struct null pointer\n");
1359                 return 1;
1360         }
1361
1362         /*
1363          * Process overrides first.
1364          *
1365          * FIXME: somehow add dereated caslat to this
1366          */
1367         cas_latency = (popts->cas_latency_override)
1368                 ? popts->cas_latency_override_value
1369                 : common_dimm->lowest_common_SPD_caslat;
1370
1371         additive_latency = (popts->additive_latency_override)
1372                 ? popts->additive_latency_override_value
1373                 : common_dimm->additive_latency;
1374
1375         sr_it = (popts->auto_self_refresh_en)
1376                 ? popts->sr_it
1377                 : 0;
1378         /* ZQ calibration */
1379         zq_en = (popts->zq_en) ? 1 : 0;
1380         /* write leveling */
1381         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1382
1383         /* Chip Select Memory Bounds (CSn_BNDS) */
1384         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1385                 unsigned long long ea = 0, sa = 0;
1386                 unsigned int cs_per_dimm
1387                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1388                 unsigned int dimm_number
1389                         = i / cs_per_dimm;
1390                 unsigned long long rank_density
1391                         = dimm_params[dimm_number].rank_density;
1392
1393                 if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) ||
1394                         ((i == 2) && (popts->ba_intlv_ctl & 0x04)) ||
1395                         ((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) {
1396                         /*
1397                          * Don't set up boundaries for unused CS
1398                          * cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1399                          * cs2 for cs0_cs1_cs2_cs3
1400                          * cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1401                          * But we need to set the ODT_RD_CFG and
1402                          * ODT_WR_CFG for CS1_CONFIG here.
1403                          */
1404                         set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1405                         continue;
1406                 }
1407                 if (dimm_params[dimm_number].n_ranks == 0) {
1408                         debug("Skipping setup of CS%u "
1409                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1410                         continue;
1411                 }
1412                 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
1413                         /*
1414                          * This works superbank 2CS
1415                          * There are 2 or more memory controllers configured
1416                          * identically, memory is interleaved between them,
1417                          * and each controller uses rank interleaving within
1418                          * itself. Therefore the starting and ending address
1419                          * on each controller is twice the amount present on
1420                          * each controller. If any CS is not included in the
1421                          * interleaving, the memory on that CS is not accssible
1422                          * and the total memory size is reduced. The CS is also
1423                          * disabled.
1424                          */
1425                         unsigned long long ctlr_density = 0;
1426                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1427                         case FSL_DDR_CS0_CS1:
1428                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1429                                 ctlr_density = dimm_params[0].rank_density * 2;
1430                                 if (i > 1)
1431                                         cs_en = 0;
1432                                 break;
1433                         case FSL_DDR_CS2_CS3:
1434                                 ctlr_density = dimm_params[0].rank_density;
1435                                 if (i > 0)
1436                                         cs_en = 0;
1437                                 break;
1438                         case FSL_DDR_CS0_CS1_CS2_CS3:
1439                                 /*
1440                                  * The four CS interleaving should have been verified by
1441                                  * populate_memctl_options()
1442                                  */
1443                                 ctlr_density = dimm_params[0].rank_density * 4;
1444                                 break;
1445                         default:
1446                                 break;
1447                         }
1448                         ea = (CONFIG_NUM_DDR_CONTROLLERS *
1449                                 (ctlr_density >> dbw_cap_adj)) - 1;
1450                 }
1451                 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
1452                         /*
1453                          * If memory interleaving between controllers is NOT
1454                          * enabled, the starting address for each memory
1455                          * controller is distinct.  However, because rank
1456                          * interleaving is enabled, the starting and ending
1457                          * addresses of the total memory on that memory
1458                          * controller needs to be programmed into its
1459                          * respective CS0_BNDS.
1460                          */
1461                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1462                         case FSL_DDR_CS0_CS1_CS2_CS3:
1463                                 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
1464                                  * needs to be set.
1465                                  */
1466                                 sa = common_dimm->base_address;
1467                                 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
1468                                 break;
1469                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1470                                 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
1471                                  * and CS2_CNDS need to be set.
1472                                  */
1473                                 if ((i == 2) && (dimm_number == 0)) {
1474                                         sa = dimm_params[dimm_number].base_address +
1475                                               2 * (rank_density >> dbw_cap_adj);
1476                                         ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1;
1477                                 } else {
1478                                         sa = dimm_params[dimm_number].base_address;
1479                                         ea = sa + (2 * (rank_density >>
1480                                                 dbw_cap_adj)) - 1;
1481                                 }
1482                                 break;
1483                         case FSL_DDR_CS0_CS1:
1484                                 /* CS0+CS1 interleaving, CS0_CNDS needs
1485                                  * to be set
1486                                  */
1487                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1488                                         sa = dimm_params[dimm_number].base_address;
1489                                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1490                                         sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1491                                         ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1492                                 } else {
1493                                         sa = 0;
1494                                         ea = 0;
1495                                 }
1496                                 if (i == 0)
1497                                         ea += (rank_density >> dbw_cap_adj);
1498                                 break;
1499                         case FSL_DDR_CS2_CS3:
1500                                 /* CS2+CS3 interleaving*/
1501                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1502                                         sa = dimm_params[dimm_number].base_address;
1503                                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1504                                         sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1505                                         ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1506                                 } else {
1507                                         sa = 0;
1508                                         ea = 0;
1509                                 }
1510                                 if (i == 2)
1511                                         ea += (rank_density >> dbw_cap_adj);
1512                                 break;
1513                         default:  /* No bank(chip-select) interleaving */
1514                                 break;
1515                         }
1516                 }
1517                 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1518                         /*
1519                          * Only the rank on CS0 of each memory controller may
1520                          * be used if memory controller interleaving is used
1521                          * without rank interleaving within each memory
1522                          * controller.  However, the ending address programmed
1523                          * into each CS0 must be the sum of the amount of
1524                          * memory in the two CS0 ranks.
1525                          */
1526                         if (i == 0) {
1527                                 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1528                         }
1529
1530                 }
1531                 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1532                         /*
1533                          * No rank interleaving and no memory controller
1534                          * interleaving.
1535                          */
1536                         sa = dimm_params[dimm_number].base_address;
1537                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1538                         if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1539                                 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1540                                 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1541                         } else {
1542                                 sa = 0;
1543                                 ea = 0;
1544                         }
1545                 }
1546
1547                 sa >>= 24;
1548                 ea >>= 24;
1549
1550                 ddr->cs[i].bnds = (0
1551                         | ((sa & 0xFFF) << 16)  /* starting address MSB */
1552                         | ((ea & 0xFFF) << 0)   /* ending address MSB */
1553                         );
1554
1555                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1556                 if (cs_en) {
1557                         set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1558                         set_csn_config_2(i, ddr);
1559                 } else
1560                         printf("CS%d is disabled.\n", i);
1561         }
1562
1563         /*
1564          * In the case we only need to compute the ddr sdram size, we only need
1565          * to set csn registers, so return from here.
1566          */
1567         if (size_only)
1568                 return 0;
1569
1570         set_ddr_eor(ddr, popts);
1571
1572 #if !defined(CONFIG_FSL_DDR1)
1573         set_timing_cfg_0(ddr, popts);
1574 #endif
1575
1576         set_timing_cfg_3(ddr, common_dimm, cas_latency);
1577         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1578         set_timing_cfg_2(ddr, popts, common_dimm,
1579                                 cas_latency, additive_latency);
1580
1581         set_ddr_cdr1(ddr, popts);
1582         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1583         ip_rev = fsl_ddr_get_version();
1584         if (ip_rev > 0x40400)
1585                 unq_mrs_en = 1;
1586
1587         set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1588         set_ddr_sdram_mode(ddr, popts, common_dimm,
1589                                 cas_latency, additive_latency, unq_mrs_en);
1590         set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
1591         set_ddr_sdram_interval(ddr, popts, common_dimm);
1592         set_ddr_data_init(ddr);
1593         set_ddr_sdram_clk_cntl(ddr, popts);
1594         set_ddr_init_addr(ddr);
1595         set_ddr_init_ext_addr(ddr);
1596         set_timing_cfg_4(ddr, popts);
1597         set_timing_cfg_5(ddr, cas_latency);
1598
1599         set_ddr_zq_cntl(ddr, zq_en);
1600         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1601
1602         set_ddr_sr_cntr(ddr, sr_it);
1603
1604         set_ddr_sdram_rcw(ddr, popts, common_dimm);
1605
1606         return check_fsl_memctl_config_regs(ddr);
1607 }