2 * Copyright 2008-2010 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
11 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
12 * Based on code from spd_sdram.c
13 * Author: James Yang [at freescale.com]
17 #include <asm/fsl_ddr_sdram.h>
21 extern unsigned int picos_to_mclk(unsigned int picos);
23 * Determine Rtt value.
25 * This should likely be either board or controller specific.
27 * Rtt(nominal) - DDR2:
32 * Rtt(nominal) - DDR3:
40 * FIXME: Apparently 8641 needs a value of 2
41 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
43 * FIXME: There was some effort down this line earlier:
46 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
47 * if (popts->dimmslot[i].num_valid_cs
48 * && (popts->cs_local_opts[2*i].odt_rd_cfg
49 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
55 static inline int fsl_ddr_get_rtt(void)
59 #if defined(CONFIG_FSL_DDR1)
61 #elif defined(CONFIG_FSL_DDR2)
71 * compute the CAS write latency according to DDR3 spec
72 * CWL = 5 if tCK >= 2.5ns
73 * 6 if 2.5ns > tCK >= 1.875ns
74 * 7 if 1.875ns > tCK >= 1.5ns
75 * 8 if 1.5ns > tCK >= 1.25ns
77 static inline unsigned int compute_cas_write_latency(void)
80 const unsigned int mclk_ps = get_memory_clk_period_ps();
84 else if (mclk_ps >= 1875)
86 else if (mclk_ps >= 1500)
88 else if (mclk_ps >= 1250)
95 /* Chip Select Configuration (CSn_CONFIG) */
96 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
97 const memctl_options_t *popts,
98 const dimm_params_t *dimm_params)
100 unsigned int cs_n_en = 0; /* Chip Select enable */
101 unsigned int intlv_en = 0; /* Memory controller interleave enable */
102 unsigned int intlv_ctl = 0; /* Interleaving control */
103 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
104 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
105 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
106 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
107 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
108 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
111 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
114 if (dimm_params[dimm_number].n_ranks > 0) {
116 /* These fields only available in CS0_CONFIG */
117 intlv_en = popts->memctl_interleaving;
118 intlv_ctl = popts->memctl_interleaving_mode;
122 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
123 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
127 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
128 (dimm_number > 1 && dimm_params[dimm_number].n_ranks > 0))
132 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
133 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
134 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
141 unsigned int n_banks_per_sdram_device;
143 ap_n_en = popts->cs_local_opts[i].auto_precharge;
144 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
145 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
146 n_banks_per_sdram_device
147 = dimm_params[dimm_number].n_banks_per_sdram_device;
148 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
149 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
150 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
152 ddr->cs[i].config = (0
153 | ((cs_n_en & 0x1) << 31)
154 | ((intlv_en & 0x3) << 29)
155 | ((intlv_ctl & 0xf) << 24)
156 | ((ap_n_en & 0x1) << 23)
158 /* XXX: some implementation only have 1 bit starting at left */
159 | ((odt_rd_cfg & 0x7) << 20)
161 /* XXX: Some implementation only have 1 bit starting at left */
162 | ((odt_wr_cfg & 0x7) << 16)
164 | ((ba_bits_cs_n & 0x3) << 14)
165 | ((row_bits_cs_n & 0x7) << 8)
166 | ((col_bits_cs_n & 0x7) << 0)
168 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
171 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
173 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
175 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
177 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
178 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
181 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
183 #if !defined(CONFIG_FSL_DDR1)
185 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
187 * Avoid writing for DDR I. The new PQ38 DDR controller
188 * dreams up non-zero default values to be backwards compatible.
190 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
192 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
193 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
194 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
195 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
196 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
198 /* Active powerdown exit timing (tXARD and tXARDS). */
199 unsigned char act_pd_exit_mclk;
200 /* Precharge powerdown exit timing (tXP). */
201 unsigned char pre_pd_exit_mclk;
202 /* Precharge powerdown exit timing (tAXPD). */
203 unsigned char taxpd_mclk;
204 /* Mode register set cycle time (tMRD). */
205 unsigned char tmrd_mclk;
207 #if defined(CONFIG_FSL_DDR3)
209 * (tXARD and tXARDS). Empirical?
210 * The DDR3 spec has not tXARD,
211 * we use the tXP instead of it.
212 * tXP=max(3nCK, 7.5ns) for DDR3.
213 * spec has not the tAXPD, we use
214 * tAXPD=8, need design to confirm.
216 int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
217 act_pd_exit_mclk = picos_to_mclk(tXP);
218 /* Mode register MR0[A12] is '1' - fast exit */
219 pre_pd_exit_mclk = act_pd_exit_mclk;
222 /* set the turnaround time */
224 #else /* CONFIG_FSL_DDR2 */
226 * (tXARD and tXARDS). Empirical?
231 act_pd_exit_mclk = 2;
232 pre_pd_exit_mclk = 2;
237 ddr->timing_cfg_0 = (0
238 | ((trwt_mclk & 0x3) << 30) /* RWT */
239 | ((twrt_mclk & 0x3) << 28) /* WRT */
240 | ((trrt_mclk & 0x3) << 26) /* RRT */
241 | ((twwt_mclk & 0x3) << 24) /* WWT */
242 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
243 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
244 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
245 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
247 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
249 #endif /* defined(CONFIG_FSL_DDR2) */
251 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
252 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
253 const common_timing_params_t *common_dimm,
254 unsigned int cas_latency)
256 /* Extended Activate to precharge interval (tRAS) */
257 unsigned int ext_acttopre = 0;
258 unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
259 unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
260 unsigned int cntl_adj = 0; /* Control Adjust */
262 /* If the tRAS > 19 MCLK, we use the ext mode */
263 if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
266 ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
268 /* If the CAS latency more than 8, use the ext mode */
272 ddr->timing_cfg_3 = (0
273 | ((ext_acttopre & 0x1) << 24)
274 | ((ext_refrec & 0xF) << 16)
275 | ((ext_caslat & 0x1) << 12)
276 | ((cntl_adj & 0x7) << 0)
278 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
281 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
282 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
283 const memctl_options_t *popts,
284 const common_timing_params_t *common_dimm,
285 unsigned int cas_latency)
287 /* Precharge-to-activate interval (tRP) */
288 unsigned char pretoact_mclk;
289 /* Activate to precharge interval (tRAS) */
290 unsigned char acttopre_mclk;
291 /* Activate to read/write interval (tRCD) */
292 unsigned char acttorw_mclk;
294 unsigned char caslat_ctrl;
295 /* Refresh recovery time (tRFC) ; trfc_low */
296 unsigned char refrec_ctrl;
297 /* Last data to precharge minimum interval (tWR) */
298 unsigned char wrrec_mclk;
299 /* Activate-to-activate interval (tRRD) */
300 unsigned char acttoact_mclk;
301 /* Last write data pair to read command issue interval (tWTR) */
302 unsigned char wrtord_mclk;
304 pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
305 acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
306 acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
309 * Translate CAS Latency to a DDR controller field value:
311 * CAS Lat DDR I DDR II Ctrl
312 * Clocks SPD Bit SPD Bit Value
313 * ------- ------- ------- -----
324 #if defined(CONFIG_FSL_DDR1)
325 caslat_ctrl = (cas_latency + 1) & 0x07;
326 #elif defined(CONFIG_FSL_DDR2)
327 caslat_ctrl = 2 * cas_latency - 1;
330 * if the CAS latency more than 8 cycle,
331 * we need set extend bit for it at
332 * TIMING_CFG_3[EXT_CASLAT]
336 caslat_ctrl = 2 * cas_latency - 1;
339 refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
340 wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
341 if (popts->OTF_burst_chop_en)
344 acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
346 * JEDEC has min requirement for tRRD
348 #if defined(CONFIG_FSL_DDR3)
349 if (acttoact_mclk < 4)
352 wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
354 * JEDEC has some min requirements for tWTR
356 #if defined(CONFIG_FSL_DDR2)
359 #elif defined(CONFIG_FSL_DDR3)
363 if (popts->OTF_burst_chop_en)
366 ddr->timing_cfg_1 = (0
367 | ((pretoact_mclk & 0x0F) << 28)
368 | ((acttopre_mclk & 0x0F) << 24)
369 | ((acttorw_mclk & 0xF) << 20)
370 | ((caslat_ctrl & 0xF) << 16)
371 | ((refrec_ctrl & 0xF) << 12)
372 | ((wrrec_mclk & 0x0F) << 8)
373 | ((acttoact_mclk & 0x07) << 4)
374 | ((wrtord_mclk & 0x07) << 0)
376 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
379 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
380 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
381 const memctl_options_t *popts,
382 const common_timing_params_t *common_dimm,
383 unsigned int cas_latency,
384 unsigned int additive_latency)
386 /* Additive latency */
387 unsigned char add_lat_mclk;
388 /* CAS-to-preamble override */
391 unsigned char wr_lat;
392 /* Read to precharge (tRTP) */
393 unsigned char rd_to_pre;
394 /* Write command to write data strobe timing adjustment */
395 unsigned char wr_data_delay;
396 /* Minimum CKE pulse width (tCKE) */
397 unsigned char cke_pls;
398 /* Window for four activates (tFAW) */
399 unsigned short four_act;
401 /* FIXME add check that this must be less than acttorw_mclk */
402 add_lat_mclk = additive_latency;
403 cpo = popts->cpo_override;
405 #if defined(CONFIG_FSL_DDR1)
407 * This is a lie. It should really be 1, but if it is
408 * set to 1, bits overlap into the old controller's
409 * otherwise unused ACSM field. If we leave it 0, then
410 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
413 #elif defined(CONFIG_FSL_DDR2)
414 wr_lat = cas_latency - 1;
416 wr_lat = compute_cas_write_latency();
419 rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
421 * JEDEC has some min requirements for tRTP
423 #if defined(CONFIG_FSL_DDR2)
426 #elif defined(CONFIG_FSL_DDR3)
430 if (additive_latency)
431 rd_to_pre += additive_latency;
432 if (popts->OTF_burst_chop_en)
433 rd_to_pre += 2; /* according to UM */
435 wr_data_delay = popts->write_data_delay;
436 cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
437 four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
439 ddr->timing_cfg_2 = (0
440 | ((add_lat_mclk & 0xf) << 28)
441 | ((cpo & 0x1f) << 23)
442 | ((wr_lat & 0xf) << 19)
443 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
444 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
445 | ((cke_pls & 0x7) << 6)
446 | ((four_act & 0x3f) << 0)
448 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
451 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
452 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
453 const memctl_options_t *popts,
454 const common_timing_params_t *common_dimm)
456 unsigned int mem_en; /* DDR SDRAM interface logic enable */
457 unsigned int sren; /* Self refresh enable (during sleep) */
458 unsigned int ecc_en; /* ECC enable. */
459 unsigned int rd_en; /* Registered DIMM enable */
460 unsigned int sdram_type; /* Type of SDRAM */
461 unsigned int dyn_pwr; /* Dynamic power management mode */
462 unsigned int dbw; /* DRAM dta bus width */
463 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
464 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
465 unsigned int threeT_en; /* Enable 3T timing */
466 unsigned int twoT_en; /* Enable 2T timing */
467 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
468 unsigned int x32_en = 0; /* x32 enable */
469 unsigned int pchb8 = 0; /* precharge bit 8 enable */
470 unsigned int hse; /* Global half strength override */
471 unsigned int mem_halt = 0; /* memory controller halt */
472 unsigned int bi = 0; /* Bypass initialization */
475 sren = popts->self_refresh_in_sleep;
476 if (common_dimm->all_DIMMs_ECC_capable) {
477 /* Allow setting of ECC only if all DIMMs are ECC. */
478 ecc_en = popts->ECC_mode;
483 rd_en = (common_dimm->all_DIMMs_registered
484 && !common_dimm->all_DIMMs_unbuffered);
486 sdram_type = CONFIG_FSL_SDRAM_TYPE;
488 dyn_pwr = popts->dynamic_power;
489 dbw = popts->data_bus_width;
490 /* 8-beat burst enable DDR-III case
491 * we must clear it when use the on-the-fly mode,
492 * must set it when use the 32-bits bus mode.
494 if (sdram_type == SDRAM_TYPE_DDR3) {
495 if (popts->burst_length == DDR_BL8)
497 if (popts->burst_length == DDR_OTF)
503 threeT_en = popts->threeT_en;
504 twoT_en = popts->twoT_en;
505 ba_intlv_ctl = popts->ba_intlv_ctl;
506 hse = popts->half_strength_driver_enable;
508 ddr->ddr_sdram_cfg = (0
509 | ((mem_en & 0x1) << 31)
510 | ((sren & 0x1) << 30)
511 | ((ecc_en & 0x1) << 29)
512 | ((rd_en & 0x1) << 28)
513 | ((sdram_type & 0x7) << 24)
514 | ((dyn_pwr & 0x1) << 21)
515 | ((dbw & 0x3) << 19)
516 | ((eight_be & 0x1) << 18)
517 | ((ncap & 0x1) << 17)
518 | ((threeT_en & 0x1) << 16)
519 | ((twoT_en & 0x1) << 15)
520 | ((ba_intlv_ctl & 0x7F) << 8)
521 | ((x32_en & 0x1) << 5)
522 | ((pchb8 & 0x1) << 4)
524 | ((mem_halt & 0x1) << 1)
527 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
530 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
531 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
532 const memctl_options_t *popts)
534 unsigned int frc_sr = 0; /* Force self refresh */
535 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
536 unsigned int dll_rst_dis; /* DLL reset disable */
537 unsigned int dqs_cfg; /* DQS configuration */
538 unsigned int odt_cfg; /* ODT configuration */
539 unsigned int num_pr; /* Number of posted refreshes */
540 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
541 unsigned int ap_en; /* Address Parity Enable */
542 unsigned int d_init; /* DRAM data initialization */
543 unsigned int rcw_en = 0; /* Register Control Word Enable */
544 unsigned int md_en = 0; /* Mirrored DIMM Enable */
545 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
547 dll_rst_dis = 1; /* Make this configurable */
548 dqs_cfg = popts->DQS_config;
549 if (popts->cs_local_opts[0].odt_rd_cfg
550 || popts->cs_local_opts[0].odt_wr_cfg) {
557 num_pr = 1; /* Make this configurable */
561 * {TIMING_CFG_1[PRETOACT]
562 * + [DDR_SDRAM_CFG_2[NUM_PR]
563 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
564 * << DDR_SDRAM_INTERVAL[REFINT]
566 #if defined(CONFIG_FSL_DDR3)
567 obc_cfg = popts->OTF_burst_chop_en;
572 ap_en = 0; /* Make this configurable? */
574 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
575 /* Use the DDR controller to auto initialize memory. */
577 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
578 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
580 /* Memory will be initialized via DMA, or not at all. */
584 #if defined(CONFIG_FSL_DDR3)
585 md_en = popts->mirrored_dimm;
587 qd_en = popts->quad_rank_present ? 1 : 0;
588 ddr->ddr_sdram_cfg_2 = (0
589 | ((frc_sr & 0x1) << 31)
590 | ((sr_ie & 0x1) << 30)
591 | ((dll_rst_dis & 0x1) << 29)
592 | ((dqs_cfg & 0x3) << 26)
593 | ((odt_cfg & 0x3) << 21)
594 | ((num_pr & 0xf) << 12)
596 | ((obc_cfg & 0x1) << 6)
597 | ((ap_en & 0x1) << 5)
598 | ((d_init & 0x1) << 4)
599 | ((rcw_en & 0x1) << 2)
600 | ((md_en & 0x1) << 0)
602 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
605 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
606 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
607 const memctl_options_t *popts)
609 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
610 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
612 #if defined(CONFIG_FSL_DDR3)
613 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
614 unsigned int srt = 0; /* self-refresh temerature, normal range */
615 unsigned int asr = 0; /* auto self-refresh disable */
616 unsigned int cwl = compute_cas_write_latency() - 5;
617 unsigned int pasr = 0; /* partial array self refresh disable */
619 if (popts->rtt_override)
620 rtt_wr = popts->rtt_wr_override_value;
623 | ((rtt_wr & 0x3) << 9)
627 | ((pasr & 0x7) << 0));
629 ddr->ddr_sdram_mode_2 = (0
630 | ((esdmode2 & 0xFFFF) << 16)
631 | ((esdmode3 & 0xFFFF) << 0)
633 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
636 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
637 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
638 const memctl_options_t *popts,
639 const common_timing_params_t *common_dimm)
641 unsigned int refint; /* Refresh interval */
642 unsigned int bstopre; /* Precharge interval */
644 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
646 bstopre = popts->bstopre;
648 /* refint field used 0x3FFF in earlier controllers */
649 ddr->ddr_sdram_interval = (0
650 | ((refint & 0xFFFF) << 16)
651 | ((bstopre & 0x3FFF) << 0)
653 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
656 #if defined(CONFIG_FSL_DDR3)
657 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
658 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
659 const memctl_options_t *popts,
660 const common_timing_params_t *common_dimm,
661 unsigned int cas_latency,
662 unsigned int additive_latency)
664 unsigned short esdmode; /* Extended SDRAM mode */
665 unsigned short sdmode; /* SDRAM mode */
667 /* Mode Register - MR1 */
668 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
669 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
671 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
672 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
673 unsigned int dic = 1; /* Output driver impedance, 34ohm */
674 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
675 1=Disable (Test/Debug) */
677 /* Mode Register - MR0 */
678 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
679 unsigned int wr; /* Write Recovery */
680 unsigned int dll_rst; /* DLL Reset */
681 unsigned int mode; /* Normal=0 or Test=1 */
682 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
683 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
685 unsigned int bl; /* BL: Burst Length */
687 unsigned int wr_mclk;
689 const unsigned int mclk_ps = get_memory_clk_period_ps();
691 rtt = fsl_ddr_get_rtt();
692 if (popts->rtt_override)
693 rtt = popts->rtt_override_value;
695 if (additive_latency == (cas_latency - 1))
697 if (additive_latency == (cas_latency - 2))
701 * The esdmode value will also be used for writing
702 * MR1 during write leveling for DDR3, although the
703 * bits specifically related to the write leveling
704 * scheme will be handled automatically by the DDR
705 * controller. so we set the wrlvl_en = 0 here.
708 | ((qoff & 0x1) << 12)
709 | ((tdqs_en & 0x1) << 11)
710 | ((rtt & 0x4) << 7) /* rtt field is split */
711 | ((wrlvl_en & 0x1) << 7)
712 | ((rtt & 0x2) << 5) /* rtt field is split */
713 | ((dic & 0x2) << 4) /* DIC field is split */
715 | ((rtt & 0x1) << 2) /* rtt field is split */
716 | ((dic & 0x1) << 1) /* DIC field is split */
717 | ((dll_en & 0x1) << 0)
721 * DLL control for precharge PD
722 * 0=slow exit DLL off (tXPDLL)
723 * 1=fast exit DLL on (tXP)
726 wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
729 else if (wr_mclk >= 9)
733 dll_rst = 0; /* dll no reset */
734 mode = 0; /* normal mode */
736 /* look up table to get the cas latency bits */
737 if (cas_latency >= 5 && cas_latency <= 11) {
738 unsigned char cas_latency_table[7] = {
747 caslat = cas_latency_table[cas_latency - 5];
749 bt = 0; /* Nibble sequential */
751 switch (popts->burst_length) {
762 printf("Error: invalid burst length of %u specified. "
763 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
764 popts->burst_length);
770 | ((dll_on & 0x1) << 12)
772 | ((dll_rst & 0x1) << 8)
773 | ((mode & 0x1) << 7)
774 | (((caslat >> 1) & 0x7) << 4)
779 ddr->ddr_sdram_mode = (0
780 | ((esdmode & 0xFFFF) << 16)
781 | ((sdmode & 0xFFFF) << 0)
784 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
787 #else /* !CONFIG_FSL_DDR3 */
789 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
790 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
791 const memctl_options_t *popts,
792 const common_timing_params_t *common_dimm,
793 unsigned int cas_latency,
794 unsigned int additive_latency)
796 unsigned short esdmode; /* Extended SDRAM mode */
797 unsigned short sdmode; /* SDRAM mode */
800 * FIXME: This ought to be pre-calculated in a
801 * technology-specific routine,
802 * e.g. compute_DDR2_mode_register(), and then the
803 * sdmode and esdmode passed in as part of common_dimm.
806 /* Extended Mode Register */
807 unsigned int mrs = 0; /* Mode Register Set */
808 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
809 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
810 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
811 unsigned int ocd = 0; /* 0x0=OCD not supported,
812 0x7=OCD default state */
814 unsigned int al; /* Posted CAS# additive latency (AL) */
815 unsigned int ods = 0; /* Output Drive Strength:
816 0 = Full strength (18ohm)
817 1 = Reduced strength (4ohm) */
818 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
819 1=Disable (Test/Debug) */
821 /* Mode Register (MR) */
822 unsigned int mr; /* Mode Register Definition */
823 unsigned int pd; /* Power-Down Mode */
824 unsigned int wr; /* Write Recovery */
825 unsigned int dll_res; /* DLL Reset */
826 unsigned int mode; /* Normal=0 or Test=1 */
827 unsigned int caslat = 0;/* CAS# latency */
828 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
830 unsigned int bl; /* BL: Burst Length */
832 #if defined(CONFIG_FSL_DDR2)
833 const unsigned int mclk_ps = get_memory_clk_period_ps();
836 rtt = fsl_ddr_get_rtt();
838 al = additive_latency;
841 | ((mrs & 0x3) << 14)
842 | ((outputs & 0x1) << 12)
843 | ((rdqs_en & 0x1) << 11)
844 | ((dqs_en & 0x1) << 10)
846 | ((rtt & 0x2) << 5) /* rtt field is split */
848 | ((rtt & 0x1) << 2) /* rtt field is split */
850 | ((dll_en & 0x1) << 0)
853 mr = 0; /* FIXME: CHECKME */
856 * 0 = Fast Exit (Normal)
857 * 1 = Slow Exit (Low Power)
861 #if defined(CONFIG_FSL_DDR1)
862 wr = 0; /* Historical */
863 #elif defined(CONFIG_FSL_DDR2)
864 wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
869 #if defined(CONFIG_FSL_DDR1)
870 if (1 <= cas_latency && cas_latency <= 4) {
871 unsigned char mode_caslat_table[4] = {
872 0x5, /* 1.5 clocks */
873 0x2, /* 2.0 clocks */
874 0x6, /* 2.5 clocks */
877 caslat = mode_caslat_table[cas_latency - 1];
879 printf("Warning: unknown cas_latency %d\n", cas_latency);
881 #elif defined(CONFIG_FSL_DDR2)
882 caslat = cas_latency;
886 switch (popts->burst_length) {
894 printf("Error: invalid burst length of %u specified. "
895 " Defaulting to 4 beats.\n",
896 popts->burst_length);
905 | ((dll_res & 0x1) << 8)
906 | ((mode & 0x1) << 7)
907 | ((caslat & 0x7) << 4)
912 ddr->ddr_sdram_mode = (0
913 | ((esdmode & 0xFFFF) << 16)
914 | ((sdmode & 0xFFFF) << 0)
916 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
920 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
921 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
923 unsigned int init_value; /* Initialization value */
925 init_value = 0xDEADBEEF;
926 ddr->ddr_data_init = init_value;
930 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
931 * The old controller on the 8540/60 doesn't have this register.
932 * Hope it's OK to set it (to 0) anyway.
934 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
935 const memctl_options_t *popts)
937 unsigned int clk_adjust; /* Clock adjust */
939 clk_adjust = popts->clk_adjust;
940 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
943 /* DDR Initialization Address (DDR_INIT_ADDR) */
944 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
946 unsigned int init_addr = 0; /* Initialization address */
948 ddr->ddr_init_addr = init_addr;
951 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
952 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
954 unsigned int uia = 0; /* Use initialization address */
955 unsigned int init_ext_addr = 0; /* Initialization address */
957 ddr->ddr_init_ext_addr = (0
958 | ((uia & 0x1) << 31)
959 | (init_ext_addr & 0xF)
963 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
964 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
965 const memctl_options_t *popts)
967 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
968 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
969 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
970 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
971 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
973 #if defined(CONFIG_FSL_DDR3)
974 if (popts->burst_length == DDR_BL8) {
975 /* We set BL/2 for fixed BL8 */
976 rrt = 0; /* BL/2 clocks */
977 wwt = 0; /* BL/2 clocks */
979 /* We need to set BL/2 + 2 to BC4 and OTF */
980 rrt = 2; /* BL/2 + 2 clocks */
981 wwt = 2; /* BL/2 + 2 clocks */
983 dll_lock = 1; /* tDLLK = 512 clocks from spec */
985 ddr->timing_cfg_4 = (0
986 | ((rwt & 0xf) << 28)
987 | ((wrt & 0xf) << 24)
988 | ((rrt & 0xf) << 20)
989 | ((wwt & 0xf) << 16)
992 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
995 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
996 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
998 unsigned int rodt_on = 0; /* Read to ODT on */
999 unsigned int rodt_off = 0; /* Read to ODT off */
1000 unsigned int wodt_on = 0; /* Write to ODT on */
1001 unsigned int wodt_off = 0; /* Write to ODT off */
1003 #if defined(CONFIG_FSL_DDR3)
1004 rodt_on = 3; /* 2 clocks */
1005 rodt_off = 4; /* 4 clocks */
1006 wodt_on = 2; /* 1 clocks */
1007 wodt_off = 4; /* 4 clocks */
1010 ddr->timing_cfg_5 = (0
1011 | ((rodt_on & 0x1f) << 24)
1012 | ((rodt_off & 0x7) << 20)
1013 | ((wodt_on & 0x1f) << 12)
1014 | ((wodt_off & 0x7) << 8)
1016 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1019 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1020 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1022 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1023 /* Normal Operation Full Calibration Time (tZQoper) */
1024 unsigned int zqoper = 0;
1025 /* Normal Operation Short Calibration Time (tZQCS) */
1026 unsigned int zqcs = 0;
1029 zqinit = 9; /* 512 clocks */
1030 zqoper = 8; /* 256 clocks */
1031 zqcs = 6; /* 64 clocks */
1034 ddr->ddr_zq_cntl = (0
1035 | ((zq_en & 0x1) << 31)
1036 | ((zqinit & 0xF) << 24)
1037 | ((zqoper & 0xF) << 16)
1038 | ((zqcs & 0xF) << 8)
1042 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1043 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1044 const memctl_options_t *popts)
1047 * First DQS pulse rising edge after margining mode
1048 * is programmed (tWL_MRD)
1050 unsigned int wrlvl_mrd = 0;
1051 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1052 unsigned int wrlvl_odten = 0;
1053 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1054 unsigned int wrlvl_dqsen = 0;
1055 /* WRLVL_SMPL: Write leveling sample time */
1056 unsigned int wrlvl_smpl = 0;
1057 /* WRLVL_WLR: Write leveling repeition time */
1058 unsigned int wrlvl_wlr = 0;
1059 /* WRLVL_START: Write leveling start time */
1060 unsigned int wrlvl_start = 0;
1062 /* suggest enable write leveling for DDR3 due to fly-by topology */
1064 /* tWL_MRD min = 40 nCK, we set it 64 */
1068 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1071 * Write leveling sample time at least need 6 clocks
1072 * higher than tWLO to allow enough time for progagation
1073 * delay and sampling the prime data bits.
1077 * Write leveling repetition time
1078 * at least tWLO + 6 clocks clocks
1083 * Write leveling start time
1084 * The value use for the DQS_ADJUST for the first sample
1085 * when write leveling is enabled.
1089 * Override the write leveling sample and start time
1090 * according to specific board
1092 if (popts->wrlvl_override) {
1093 wrlvl_smpl = popts->wrlvl_sample;
1094 wrlvl_start = popts->wrlvl_start;
1098 ddr->ddr_wrlvl_cntl = (0
1099 | ((wrlvl_en & 0x1) << 31)
1100 | ((wrlvl_mrd & 0x7) << 24)
1101 | ((wrlvl_odten & 0x7) << 20)
1102 | ((wrlvl_dqsen & 0x7) << 16)
1103 | ((wrlvl_smpl & 0xf) << 12)
1104 | ((wrlvl_wlr & 0x7) << 8)
1105 | ((wrlvl_start & 0x1F) << 0)
1109 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1110 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1112 /* Self Refresh Idle Threshold */
1113 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1116 /* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */
1117 static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr)
1119 unsigned int rcw0 = 0; /* RCW0: Register Control Word 0 */
1120 unsigned int rcw1 = 0; /* RCW1: Register Control Word 1 */
1121 unsigned int rcw2 = 0; /* RCW2: Register Control Word 2 */
1122 unsigned int rcw3 = 0; /* RCW3: Register Control Word 3 */
1123 unsigned int rcw4 = 0; /* RCW4: Register Control Word 4 */
1124 unsigned int rcw5 = 0; /* RCW5: Register Control Word 5 */
1125 unsigned int rcw6 = 0; /* RCW6: Register Control Word 6 */
1126 unsigned int rcw7 = 0; /* RCW7: Register Control Word 7 */
1128 ddr->ddr_sdram_rcw_1 = (0
1129 | ((rcw0 & 0xF) << 28)
1130 | ((rcw1 & 0xF) << 24)
1131 | ((rcw2 & 0xF) << 20)
1132 | ((rcw3 & 0xF) << 16)
1133 | ((rcw4 & 0xF) << 12)
1134 | ((rcw5 & 0xF) << 8)
1135 | ((rcw6 & 0xF) << 4)
1136 | ((rcw7 & 0xF) << 0)
1140 /* DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2) */
1141 static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr)
1143 unsigned int rcw8 = 0; /* RCW0: Register Control Word 8 */
1144 unsigned int rcw9 = 0; /* RCW1: Register Control Word 9 */
1145 unsigned int rcw10 = 0; /* RCW2: Register Control Word 10 */
1146 unsigned int rcw11 = 0; /* RCW3: Register Control Word 11 */
1147 unsigned int rcw12 = 0; /* RCW4: Register Control Word 12 */
1148 unsigned int rcw13 = 0; /* RCW5: Register Control Word 13 */
1149 unsigned int rcw14 = 0; /* RCW6: Register Control Word 14 */
1150 unsigned int rcw15 = 0; /* RCW7: Register Control Word 15 */
1152 ddr->ddr_sdram_rcw_2 = (0
1153 | ((rcw8 & 0xF) << 28)
1154 | ((rcw9 & 0xF) << 24)
1155 | ((rcw10 & 0xF) << 20)
1156 | ((rcw11 & 0xF) << 16)
1157 | ((rcw12 & 0xF) << 12)
1158 | ((rcw13 & 0xF) << 8)
1159 | ((rcw14 & 0xF) << 4)
1160 | ((rcw15 & 0xF) << 0)
1165 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1167 unsigned int res = 0;
1170 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1171 * not set at the same time.
1173 if (ddr->ddr_sdram_cfg & 0x10000000
1174 && ddr->ddr_sdram_cfg & 0x00008000) {
1175 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1176 " should not be set at the same time.\n");
1184 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1185 fsl_ddr_cfg_regs_t *ddr,
1186 const common_timing_params_t *common_dimm,
1187 const dimm_params_t *dimm_params,
1188 unsigned int dbw_cap_adj)
1191 unsigned int cas_latency;
1192 unsigned int additive_latency;
1195 unsigned int wrlvl_en;
1197 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1199 if (common_dimm == NULL) {
1200 printf("Error: subset DIMM params struct null pointer\n");
1205 * Process overrides first.
1207 * FIXME: somehow add dereated caslat to this
1209 cas_latency = (popts->cas_latency_override)
1210 ? popts->cas_latency_override_value
1211 : common_dimm->lowest_common_SPD_caslat;
1213 additive_latency = (popts->additive_latency_override)
1214 ? popts->additive_latency_override_value
1215 : common_dimm->additive_latency;
1217 sr_it = (popts->auto_self_refresh_en)
1220 /* ZQ calibration */
1221 zq_en = (popts->zq_en) ? 1 : 0;
1222 /* write leveling */
1223 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1225 /* Chip Select Memory Bounds (CSn_BNDS) */
1226 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1227 unsigned long long ea = 0, sa = 0;
1228 unsigned int cs_per_dimm
1229 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1230 unsigned int dimm_number
1232 unsigned long long rank_density
1233 = dimm_params[dimm_number].rank_density;
1235 if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) ||
1236 ((i == 2) && (popts->ba_intlv_ctl & 0x04)) ||
1237 ((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) {
1239 * Don't set up boundaries for unused CS
1240 * cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1241 * cs2 for cs0_cs1_cs2_cs3
1242 * cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1243 * But we need to set the ODT_RD_CFG and
1244 * ODT_WR_CFG for CS1_CONFIG here.
1246 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1249 if (dimm_params[dimm_number].n_ranks == 0) {
1250 debug("Skipping setup of CS%u "
1251 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1254 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
1256 * This works superbank 2CS
1257 * There are 2 or more memory controllers configured
1258 * identically, memory is interleaved between them,
1259 * and each controller uses rank interleaving within
1260 * itself. Therefore the starting and ending address
1261 * on each controller is twice the amount present on
1264 unsigned long long ctlr_density = 0;
1265 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1266 case FSL_DDR_CS0_CS1:
1267 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1268 ctlr_density = dimm_params[0].rank_density * 2;
1270 case FSL_DDR_CS2_CS3:
1271 ctlr_density = dimm_params[0].rank_density;
1273 case FSL_DDR_CS0_CS1_CS2_CS3:
1275 * The four CS interleaving should have been verified by
1276 * populate_memctl_options()
1278 ctlr_density = dimm_params[0].rank_density * 4;
1283 ea = (CONFIG_NUM_DDR_CONTROLLERS *
1284 (ctlr_density >> dbw_cap_adj)) - 1;
1286 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
1288 * If memory interleaving between controllers is NOT
1289 * enabled, the starting address for each memory
1290 * controller is distinct. However, because rank
1291 * interleaving is enabled, the starting and ending
1292 * addresses of the total memory on that memory
1293 * controller needs to be programmed into its
1294 * respective CS0_BNDS.
1296 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1297 case FSL_DDR_CS0_CS1_CS2_CS3:
1298 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
1301 sa = common_dimm->base_address;
1302 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
1304 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1305 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
1306 * and CS2_CNDS need to be set.
1308 if ((i == 2) && (dimm_number == 0)) {
1309 sa = dimm_params[dimm_number].base_address +
1310 2 * (rank_density >> dbw_cap_adj);
1311 ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1;
1313 sa = dimm_params[dimm_number].base_address;
1314 ea = sa + (2 * (rank_density >>
1318 case FSL_DDR_CS0_CS1:
1319 /* CS0+CS1 interleaving, CS0_CNDS needs
1322 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1323 sa = dimm_params[dimm_number].base_address;
1324 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1325 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1326 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1332 ea += (rank_density >> dbw_cap_adj);
1334 case FSL_DDR_CS2_CS3:
1335 /* CS2+CS3 interleaving*/
1336 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1337 sa = dimm_params[dimm_number].base_address;
1338 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1339 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1340 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1346 ea += (rank_density >> dbw_cap_adj);
1348 default: /* No bank(chip-select) interleaving */
1352 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1354 * Only the rank on CS0 of each memory controller may
1355 * be used if memory controller interleaving is used
1356 * without rank interleaving within each memory
1357 * controller. However, the ending address programmed
1358 * into each CS0 must be the sum of the amount of
1359 * memory in the two CS0 ranks.
1362 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1366 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1368 * No rank interleaving and no memory controller
1371 sa = dimm_params[dimm_number].base_address;
1372 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1373 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1374 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1375 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1385 ddr->cs[i].bnds = (0
1386 | ((sa & 0xFFF) << 16) /* starting address MSB */
1387 | ((ea & 0xFFF) << 0) /* ending address MSB */
1390 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1391 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1392 set_csn_config_2(i, ddr);
1395 #if !defined(CONFIG_FSL_DDR1)
1396 set_timing_cfg_0(ddr);
1399 set_timing_cfg_3(ddr, common_dimm, cas_latency);
1400 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1401 set_timing_cfg_2(ddr, popts, common_dimm,
1402 cas_latency, additive_latency);
1404 set_ddr_sdram_cfg(ddr, popts, common_dimm);
1406 set_ddr_sdram_cfg_2(ddr, popts);
1407 set_ddr_sdram_mode(ddr, popts, common_dimm,
1408 cas_latency, additive_latency);
1409 set_ddr_sdram_mode_2(ddr, popts);
1410 set_ddr_sdram_interval(ddr, popts, common_dimm);
1411 set_ddr_data_init(ddr);
1412 set_ddr_sdram_clk_cntl(ddr, popts);
1413 set_ddr_init_addr(ddr);
1414 set_ddr_init_ext_addr(ddr);
1415 set_timing_cfg_4(ddr, popts);
1416 set_timing_cfg_5(ddr);
1418 set_ddr_zq_cntl(ddr, zq_en);
1419 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1421 set_ddr_sr_cntr(ddr, sr_it);
1423 set_ddr_sdram_rcw_1(ddr);
1424 set_ddr_sdram_rcw_2(ddr);
1426 return check_fsl_memctl_config_regs(ddr);