2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
11 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
12 * Based on code from spd_sdram.c
13 * Author: James Yang [at freescale.com]
17 #include <asm/fsl_ddr_sdram.h>
21 #define _DDR_ADDR CONFIG_SYS_MPC8xxx_DDR_ADDR
23 static u32 fsl_ddr_get_version(void)
26 u32 ver_major_minor_errata;
28 ddr = (void *)_DDR_ADDR;
29 ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
30 ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
32 return ver_major_minor_errata;
35 unsigned int picos_to_mclk(unsigned int picos);
38 * Determine Rtt value.
40 * This should likely be either board or controller specific.
42 * Rtt(nominal) - DDR2:
47 * Rtt(nominal) - DDR3:
55 * FIXME: Apparently 8641 needs a value of 2
56 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
58 * FIXME: There was some effort down this line earlier:
61 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
62 * if (popts->dimmslot[i].num_valid_cs
63 * && (popts->cs_local_opts[2*i].odt_rd_cfg
64 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
70 static inline int fsl_ddr_get_rtt(void)
74 #if defined(CONFIG_FSL_DDR1)
76 #elif defined(CONFIG_FSL_DDR2)
86 * compute the CAS write latency according to DDR3 spec
87 * CWL = 5 if tCK >= 2.5ns
88 * 6 if 2.5ns > tCK >= 1.875ns
89 * 7 if 1.875ns > tCK >= 1.5ns
90 * 8 if 1.5ns > tCK >= 1.25ns
91 * 9 if 1.25ns > tCK >= 1.07ns
92 * 10 if 1.07ns > tCK >= 0.935ns
93 * 11 if 0.935ns > tCK >= 0.833ns
94 * 12 if 0.833ns > tCK >= 0.75ns
96 static inline unsigned int compute_cas_write_latency(void)
99 const unsigned int mclk_ps = get_memory_clk_period_ps();
103 else if (mclk_ps >= 1875)
105 else if (mclk_ps >= 1500)
107 else if (mclk_ps >= 1250)
109 else if (mclk_ps >= 1070)
111 else if (mclk_ps >= 935)
113 else if (mclk_ps >= 833)
115 else if (mclk_ps >= 750)
119 printf("Warning: CWL is out of range\n");
124 /* Chip Select Configuration (CSn_CONFIG) */
125 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
126 const memctl_options_t *popts,
127 const dimm_params_t *dimm_params)
129 unsigned int cs_n_en = 0; /* Chip Select enable */
130 unsigned int intlv_en = 0; /* Memory controller interleave enable */
131 unsigned int intlv_ctl = 0; /* Interleaving control */
132 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
133 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
134 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
135 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
136 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
137 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
140 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
143 if (dimm_params[dimm_number].n_ranks > 0) {
145 /* These fields only available in CS0_CONFIG */
146 if (!popts->memctl_interleaving)
148 switch (popts->memctl_interleaving_mode) {
149 case FSL_DDR_CACHE_LINE_INTERLEAVING:
150 case FSL_DDR_PAGE_INTERLEAVING:
151 case FSL_DDR_BANK_INTERLEAVING:
152 case FSL_DDR_SUPERBANK_INTERLEAVING:
153 intlv_en = popts->memctl_interleaving;
154 intlv_ctl = popts->memctl_interleaving_mode;
162 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
163 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
167 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
168 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
172 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
173 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
174 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
181 unsigned int n_banks_per_sdram_device;
183 ap_n_en = popts->cs_local_opts[i].auto_precharge;
184 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
185 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
186 n_banks_per_sdram_device
187 = dimm_params[dimm_number].n_banks_per_sdram_device;
188 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
189 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
190 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
192 ddr->cs[i].config = (0
193 | ((cs_n_en & 0x1) << 31)
194 | ((intlv_en & 0x3) << 29)
195 | ((intlv_ctl & 0xf) << 24)
196 | ((ap_n_en & 0x1) << 23)
198 /* XXX: some implementation only have 1 bit starting at left */
199 | ((odt_rd_cfg & 0x7) << 20)
201 /* XXX: Some implementation only have 1 bit starting at left */
202 | ((odt_wr_cfg & 0x7) << 16)
204 | ((ba_bits_cs_n & 0x3) << 14)
205 | ((row_bits_cs_n & 0x7) << 8)
206 | ((col_bits_cs_n & 0x7) << 0)
208 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
211 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
213 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
215 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
217 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
218 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
221 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
223 #if !defined(CONFIG_FSL_DDR1)
224 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
226 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
227 if (dimm_params[0].n_ranks == 4)
231 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
232 if ((dimm_params[0].n_ranks == 2) &&
233 (dimm_params[1].n_ranks == 2))
236 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
237 if (dimm_params[0].n_ranks == 4)
245 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
247 * Avoid writing for DDR I. The new PQ38 DDR controller
248 * dreams up non-zero default values to be backwards compatible.
250 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
251 const memctl_options_t *popts,
252 const dimm_params_t *dimm_params)
254 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
255 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
256 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
257 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
258 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
260 /* Active powerdown exit timing (tXARD and tXARDS). */
261 unsigned char act_pd_exit_mclk;
262 /* Precharge powerdown exit timing (tXP). */
263 unsigned char pre_pd_exit_mclk;
264 /* ODT powerdown exit timing (tAXPD). */
265 unsigned char taxpd_mclk;
266 /* Mode register set cycle time (tMRD). */
267 unsigned char tmrd_mclk;
269 #ifdef CONFIG_FSL_DDR3
271 * (tXARD and tXARDS). Empirical?
272 * The DDR3 spec has not tXARD,
273 * we use the tXP instead of it.
274 * tXP=max(3nCK, 7.5ns) for DDR3.
275 * spec has not the tAXPD, we use
276 * tAXPD=1, need design to confirm.
278 int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
279 unsigned int data_rate = get_ddr_freq(0);
281 /* set the turnaround time */
284 * for single quad-rank DIMM and two dual-rank DIMMs
285 * to avoid ODT overlap
287 if (avoid_odt_overlap(dimm_params)) {
291 /* for faster clock, need more time for data setup */
292 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
294 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
297 if (popts->dynamic_power == 0) { /* powerdown is not used */
298 act_pd_exit_mclk = 1;
299 pre_pd_exit_mclk = 1;
302 /* act_pd_exit_mclk = tXARD, see above */
303 act_pd_exit_mclk = picos_to_mclk(tXP);
304 /* Mode register MR0[A12] is '1' - fast exit */
305 pre_pd_exit_mclk = act_pd_exit_mclk;
308 #else /* CONFIG_FSL_DDR2 */
310 * (tXARD and tXARDS). Empirical?
315 act_pd_exit_mclk = 2;
316 pre_pd_exit_mclk = 2;
321 if (popts->trwt_override)
322 trwt_mclk = popts->trwt;
324 ddr->timing_cfg_0 = (0
325 | ((trwt_mclk & 0x3) << 30) /* RWT */
326 | ((twrt_mclk & 0x3) << 28) /* WRT */
327 | ((trrt_mclk & 0x3) << 26) /* RRT */
328 | ((twwt_mclk & 0x3) << 24) /* WWT */
329 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
330 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
331 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
332 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
334 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
336 #endif /* defined(CONFIG_FSL_DDR2) */
338 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
339 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
340 const memctl_options_t *popts,
341 const common_timing_params_t *common_dimm,
342 unsigned int cas_latency)
344 /* Extended precharge to activate interval (tRP) */
345 unsigned int ext_pretoact = 0;
346 /* Extended Activate to precharge interval (tRAS) */
347 unsigned int ext_acttopre = 0;
348 /* Extended activate to read/write interval (tRCD) */
349 unsigned int ext_acttorw = 0;
350 /* Extended refresh recovery time (tRFC) */
351 unsigned int ext_refrec;
352 /* Extended MCAS latency from READ cmd */
353 unsigned int ext_caslat = 0;
354 /* Extended last data to precharge interval (tWR) */
355 unsigned int ext_wrrec = 0;
357 unsigned int cntl_adj = 0;
359 ext_pretoact = picos_to_mclk(common_dimm->tRP_ps) >> 4;
360 ext_acttopre = picos_to_mclk(common_dimm->tRAS_ps) >> 4;
361 ext_acttorw = picos_to_mclk(common_dimm->tRCD_ps) >> 4;
362 ext_caslat = (2 * cas_latency - 1) >> 4;
363 ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
364 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
365 ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) +
366 (popts->OTF_burst_chop_en ? 2 : 0)) >> 4;
368 ddr->timing_cfg_3 = (0
369 | ((ext_pretoact & 0x1) << 28)
370 | ((ext_acttopre & 0x2) << 24)
371 | ((ext_acttorw & 0x1) << 22)
372 | ((ext_refrec & 0x1F) << 16)
373 | ((ext_caslat & 0x3) << 12)
374 | ((ext_wrrec & 0x1) << 8)
375 | ((cntl_adj & 0x7) << 0)
377 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
380 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
381 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
382 const memctl_options_t *popts,
383 const common_timing_params_t *common_dimm,
384 unsigned int cas_latency)
386 /* Precharge-to-activate interval (tRP) */
387 unsigned char pretoact_mclk;
388 /* Activate to precharge interval (tRAS) */
389 unsigned char acttopre_mclk;
390 /* Activate to read/write interval (tRCD) */
391 unsigned char acttorw_mclk;
393 unsigned char caslat_ctrl;
394 /* Refresh recovery time (tRFC) ; trfc_low */
395 unsigned char refrec_ctrl;
396 /* Last data to precharge minimum interval (tWR) */
397 unsigned char wrrec_mclk;
398 /* Activate-to-activate interval (tRRD) */
399 unsigned char acttoact_mclk;
400 /* Last write data pair to read command issue interval (tWTR) */
401 unsigned char wrtord_mclk;
402 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
403 static const u8 wrrec_table[] = {
404 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
406 pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
407 acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
408 acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
411 * Translate CAS Latency to a DDR controller field value:
413 * CAS Lat DDR I DDR II Ctrl
414 * Clocks SPD Bit SPD Bit Value
415 * ------- ------- ------- -----
426 #if defined(CONFIG_FSL_DDR1)
427 caslat_ctrl = (cas_latency + 1) & 0x07;
428 #elif defined(CONFIG_FSL_DDR2)
429 caslat_ctrl = 2 * cas_latency - 1;
432 * if the CAS latency more than 8 cycle,
433 * we need set extend bit for it at
434 * TIMING_CFG_3[EXT_CASLAT]
436 caslat_ctrl = 2 * cas_latency - 1;
439 refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
440 wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
443 printf("Error: WRREC doesn't support more than 16 clocks\n");
445 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
446 if (popts->OTF_burst_chop_en)
449 acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
451 * JEDEC has min requirement for tRRD
453 #if defined(CONFIG_FSL_DDR3)
454 if (acttoact_mclk < 4)
457 wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
459 * JEDEC has some min requirements for tWTR
461 #if defined(CONFIG_FSL_DDR2)
464 #elif defined(CONFIG_FSL_DDR3)
468 if (popts->OTF_burst_chop_en)
471 ddr->timing_cfg_1 = (0
472 | ((pretoact_mclk & 0x0F) << 28)
473 | ((acttopre_mclk & 0x0F) << 24)
474 | ((acttorw_mclk & 0xF) << 20)
475 | ((caslat_ctrl & 0xF) << 16)
476 | ((refrec_ctrl & 0xF) << 12)
477 | ((wrrec_mclk & 0x0F) << 8)
478 | ((acttoact_mclk & 0x0F) << 4)
479 | ((wrtord_mclk & 0x0F) << 0)
481 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
484 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
485 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
486 const memctl_options_t *popts,
487 const common_timing_params_t *common_dimm,
488 unsigned int cas_latency,
489 unsigned int additive_latency)
491 /* Additive latency */
492 unsigned char add_lat_mclk;
493 /* CAS-to-preamble override */
496 unsigned char wr_lat;
497 /* Read to precharge (tRTP) */
498 unsigned char rd_to_pre;
499 /* Write command to write data strobe timing adjustment */
500 unsigned char wr_data_delay;
501 /* Minimum CKE pulse width (tCKE) */
502 unsigned char cke_pls;
503 /* Window for four activates (tFAW) */
504 unsigned short four_act;
506 /* FIXME add check that this must be less than acttorw_mclk */
507 add_lat_mclk = additive_latency;
508 cpo = popts->cpo_override;
510 #if defined(CONFIG_FSL_DDR1)
512 * This is a lie. It should really be 1, but if it is
513 * set to 1, bits overlap into the old controller's
514 * otherwise unused ACSM field. If we leave it 0, then
515 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
518 #elif defined(CONFIG_FSL_DDR2)
519 wr_lat = cas_latency - 1;
521 wr_lat = compute_cas_write_latency();
524 rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
526 * JEDEC has some min requirements for tRTP
528 #if defined(CONFIG_FSL_DDR2)
531 #elif defined(CONFIG_FSL_DDR3)
535 if (additive_latency)
536 rd_to_pre += additive_latency;
537 if (popts->OTF_burst_chop_en)
538 rd_to_pre += 2; /* according to UM */
540 wr_data_delay = popts->write_data_delay;
541 cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
542 four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
544 ddr->timing_cfg_2 = (0
545 | ((add_lat_mclk & 0xf) << 28)
546 | ((cpo & 0x1f) << 23)
547 | ((wr_lat & 0xf) << 19)
548 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
549 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
550 | ((cke_pls & 0x7) << 6)
551 | ((four_act & 0x3f) << 0)
553 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
556 /* DDR SDRAM Register Control Word */
557 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
558 const memctl_options_t *popts,
559 const common_timing_params_t *common_dimm)
561 if (common_dimm->all_DIMMs_registered
562 && !common_dimm->all_DIMMs_unbuffered) {
563 if (popts->rcw_override) {
564 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
565 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
567 ddr->ddr_sdram_rcw_1 =
568 common_dimm->rcw[0] << 28 | \
569 common_dimm->rcw[1] << 24 | \
570 common_dimm->rcw[2] << 20 | \
571 common_dimm->rcw[3] << 16 | \
572 common_dimm->rcw[4] << 12 | \
573 common_dimm->rcw[5] << 8 | \
574 common_dimm->rcw[6] << 4 | \
576 ddr->ddr_sdram_rcw_2 =
577 common_dimm->rcw[8] << 28 | \
578 common_dimm->rcw[9] << 24 | \
579 common_dimm->rcw[10] << 20 | \
580 common_dimm->rcw[11] << 16 | \
581 common_dimm->rcw[12] << 12 | \
582 common_dimm->rcw[13] << 8 | \
583 common_dimm->rcw[14] << 4 | \
584 common_dimm->rcw[15];
586 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
587 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
591 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
592 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
593 const memctl_options_t *popts,
594 const common_timing_params_t *common_dimm)
596 unsigned int mem_en; /* DDR SDRAM interface logic enable */
597 unsigned int sren; /* Self refresh enable (during sleep) */
598 unsigned int ecc_en; /* ECC enable. */
599 unsigned int rd_en; /* Registered DIMM enable */
600 unsigned int sdram_type; /* Type of SDRAM */
601 unsigned int dyn_pwr; /* Dynamic power management mode */
602 unsigned int dbw; /* DRAM dta bus width */
603 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
604 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
605 unsigned int threeT_en; /* Enable 3T timing */
606 unsigned int twoT_en; /* Enable 2T timing */
607 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
608 unsigned int x32_en = 0; /* x32 enable */
609 unsigned int pchb8 = 0; /* precharge bit 8 enable */
610 unsigned int hse; /* Global half strength override */
611 unsigned int mem_halt = 0; /* memory controller halt */
612 unsigned int bi = 0; /* Bypass initialization */
615 sren = popts->self_refresh_in_sleep;
616 if (common_dimm->all_DIMMs_ECC_capable) {
617 /* Allow setting of ECC only if all DIMMs are ECC. */
618 ecc_en = popts->ECC_mode;
623 if (common_dimm->all_DIMMs_registered
624 && !common_dimm->all_DIMMs_unbuffered) {
629 twoT_en = popts->twoT_en;
632 sdram_type = CONFIG_FSL_SDRAM_TYPE;
634 dyn_pwr = popts->dynamic_power;
635 dbw = popts->data_bus_width;
636 /* 8-beat burst enable DDR-III case
637 * we must clear it when use the on-the-fly mode,
638 * must set it when use the 32-bits bus mode.
640 if (sdram_type == SDRAM_TYPE_DDR3) {
641 if (popts->burst_length == DDR_BL8)
643 if (popts->burst_length == DDR_OTF)
649 threeT_en = popts->threeT_en;
650 ba_intlv_ctl = popts->ba_intlv_ctl;
651 hse = popts->half_strength_driver_enable;
653 ddr->ddr_sdram_cfg = (0
654 | ((mem_en & 0x1) << 31)
655 | ((sren & 0x1) << 30)
656 | ((ecc_en & 0x1) << 29)
657 | ((rd_en & 0x1) << 28)
658 | ((sdram_type & 0x7) << 24)
659 | ((dyn_pwr & 0x1) << 21)
660 | ((dbw & 0x3) << 19)
661 | ((eight_be & 0x1) << 18)
662 | ((ncap & 0x1) << 17)
663 | ((threeT_en & 0x1) << 16)
664 | ((twoT_en & 0x1) << 15)
665 | ((ba_intlv_ctl & 0x7F) << 8)
666 | ((x32_en & 0x1) << 5)
667 | ((pchb8 & 0x1) << 4)
669 | ((mem_halt & 0x1) << 1)
672 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
675 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
676 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
677 const memctl_options_t *popts,
678 const unsigned int unq_mrs_en)
680 unsigned int frc_sr = 0; /* Force self refresh */
681 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
682 unsigned int dll_rst_dis; /* DLL reset disable */
683 unsigned int dqs_cfg; /* DQS configuration */
684 unsigned int odt_cfg = 0; /* ODT configuration */
685 unsigned int num_pr; /* Number of posted refreshes */
686 unsigned int slow = 0; /* DDR will be run less than 1250 */
687 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
688 unsigned int ap_en; /* Address Parity Enable */
689 unsigned int d_init; /* DRAM data initialization */
690 unsigned int rcw_en = 0; /* Register Control Word Enable */
691 unsigned int md_en = 0; /* Mirrored DIMM Enable */
692 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
695 dll_rst_dis = 1; /* Make this configurable */
696 dqs_cfg = popts->DQS_config;
697 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
698 if (popts->cs_local_opts[i].odt_rd_cfg
699 || popts->cs_local_opts[i].odt_wr_cfg) {
700 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
705 num_pr = 1; /* Make this configurable */
709 * {TIMING_CFG_1[PRETOACT]
710 * + [DDR_SDRAM_CFG_2[NUM_PR]
711 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
712 * << DDR_SDRAM_INTERVAL[REFINT]
714 #if defined(CONFIG_FSL_DDR3)
715 obc_cfg = popts->OTF_burst_chop_en;
720 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
721 slow = get_ddr_freq(0) < 1249000000;
724 if (popts->registered_dimm_en) {
726 ap_en = popts->ap_en;
731 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
732 /* Use the DDR controller to auto initialize memory. */
733 d_init = popts->ECC_init_using_memctl;
734 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
735 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
737 /* Memory will be initialized via DMA, or not at all. */
741 #if defined(CONFIG_FSL_DDR3)
742 md_en = popts->mirrored_dimm;
744 qd_en = popts->quad_rank_present ? 1 : 0;
745 ddr->ddr_sdram_cfg_2 = (0
746 | ((frc_sr & 0x1) << 31)
747 | ((sr_ie & 0x1) << 30)
748 | ((dll_rst_dis & 0x1) << 29)
749 | ((dqs_cfg & 0x3) << 26)
750 | ((odt_cfg & 0x3) << 21)
751 | ((num_pr & 0xf) << 12)
755 | ((obc_cfg & 0x1) << 6)
756 | ((ap_en & 0x1) << 5)
757 | ((d_init & 0x1) << 4)
758 | ((rcw_en & 0x1) << 2)
759 | ((md_en & 0x1) << 0)
761 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
764 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
765 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
766 const memctl_options_t *popts,
767 const unsigned int unq_mrs_en)
769 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
770 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
772 #if defined(CONFIG_FSL_DDR3)
774 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
775 unsigned int srt = 0; /* self-refresh temerature, normal range */
776 unsigned int asr = 0; /* auto self-refresh disable */
777 unsigned int cwl = compute_cas_write_latency() - 5;
778 unsigned int pasr = 0; /* partial array self refresh disable */
780 if (popts->rtt_override)
781 rtt_wr = popts->rtt_wr_override_value;
783 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
785 | ((rtt_wr & 0x3) << 9)
789 | ((pasr & 0x7) << 0));
791 ddr->ddr_sdram_mode_2 = (0
792 | ((esdmode2 & 0xFFFF) << 16)
793 | ((esdmode3 & 0xFFFF) << 0)
795 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
797 #ifdef CONFIG_FSL_DDR3
798 if (unq_mrs_en) { /* unique mode registers are supported */
799 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
800 if (popts->rtt_override)
801 rtt_wr = popts->rtt_wr_override_value;
803 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
805 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
806 esdmode2 |= (rtt_wr & 0x3) << 9;
809 ddr->ddr_sdram_mode_4 = (0
810 | ((esdmode2 & 0xFFFF) << 16)
811 | ((esdmode3 & 0xFFFF) << 0)
815 ddr->ddr_sdram_mode_6 = (0
816 | ((esdmode2 & 0xFFFF) << 16)
817 | ((esdmode3 & 0xFFFF) << 0)
821 ddr->ddr_sdram_mode_8 = (0
822 | ((esdmode2 & 0xFFFF) << 16)
823 | ((esdmode3 & 0xFFFF) << 0)
828 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
829 ddr->ddr_sdram_mode_4);
830 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
831 ddr->ddr_sdram_mode_6);
832 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
833 ddr->ddr_sdram_mode_8);
838 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
839 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
840 const memctl_options_t *popts,
841 const common_timing_params_t *common_dimm)
843 unsigned int refint; /* Refresh interval */
844 unsigned int bstopre; /* Precharge interval */
846 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
848 bstopre = popts->bstopre;
850 /* refint field used 0x3FFF in earlier controllers */
851 ddr->ddr_sdram_interval = (0
852 | ((refint & 0xFFFF) << 16)
853 | ((bstopre & 0x3FFF) << 0)
855 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
858 #if defined(CONFIG_FSL_DDR3)
859 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
860 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
861 const memctl_options_t *popts,
862 const common_timing_params_t *common_dimm,
863 unsigned int cas_latency,
864 unsigned int additive_latency,
865 const unsigned int unq_mrs_en)
867 unsigned short esdmode; /* Extended SDRAM mode */
868 unsigned short sdmode; /* SDRAM mode */
870 /* Mode Register - MR1 */
871 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
872 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
874 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
875 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
876 unsigned int dic = 0; /* Output driver impedance, 40ohm */
877 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
878 1=Disable (Test/Debug) */
880 /* Mode Register - MR0 */
881 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
882 unsigned int wr = 0; /* Write Recovery */
883 unsigned int dll_rst; /* DLL Reset */
884 unsigned int mode; /* Normal=0 or Test=1 */
885 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
886 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
888 unsigned int bl; /* BL: Burst Length */
890 unsigned int wr_mclk;
892 * DDR_SDRAM_MODE doesn't support 9,11,13,15
893 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
896 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
898 const unsigned int mclk_ps = get_memory_clk_period_ps();
901 if (popts->rtt_override)
902 rtt = popts->rtt_override_value;
904 rtt = popts->cs_local_opts[0].odt_rtt_norm;
906 if (additive_latency == (cas_latency - 1))
908 if (additive_latency == (cas_latency - 2))
911 if (popts->quad_rank_present)
912 dic = 1; /* output driver impedance 240/7 ohm */
915 * The esdmode value will also be used for writing
916 * MR1 during write leveling for DDR3, although the
917 * bits specifically related to the write leveling
918 * scheme will be handled automatically by the DDR
919 * controller. so we set the wrlvl_en = 0 here.
922 | ((qoff & 0x1) << 12)
923 | ((tdqs_en & 0x1) << 11)
924 | ((rtt & 0x4) << 7) /* rtt field is split */
925 | ((wrlvl_en & 0x1) << 7)
926 | ((rtt & 0x2) << 5) /* rtt field is split */
927 | ((dic & 0x2) << 4) /* DIC field is split */
929 | ((rtt & 0x1) << 2) /* rtt field is split */
930 | ((dic & 0x1) << 1) /* DIC field is split */
931 | ((dll_en & 0x1) << 0)
935 * DLL control for precharge PD
936 * 0=slow exit DLL off (tXPDLL)
937 * 1=fast exit DLL on (tXP)
941 wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
943 wr = wr_table[wr_mclk - 5];
945 printf("Error: unsupported write recovery for mode register "
946 "wr_mclk = %d\n", wr_mclk);
949 dll_rst = 0; /* dll no reset */
950 mode = 0; /* normal mode */
952 /* look up table to get the cas latency bits */
953 if (cas_latency >= 5 && cas_latency <= 16) {
954 unsigned char cas_latency_table[] = {
968 caslat = cas_latency_table[cas_latency - 5];
970 printf("Error: unsupported cas latency for mode register\n");
973 bt = 0; /* Nibble sequential */
975 switch (popts->burst_length) {
986 printf("Error: invalid burst length of %u specified. "
987 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
988 popts->burst_length);
994 | ((dll_on & 0x1) << 12)
996 | ((dll_rst & 0x1) << 8)
997 | ((mode & 0x1) << 7)
998 | (((caslat >> 1) & 0x7) << 4)
1000 | ((caslat & 1) << 2)
1004 ddr->ddr_sdram_mode = (0
1005 | ((esdmode & 0xFFFF) << 16)
1006 | ((sdmode & 0xFFFF) << 0)
1009 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1011 if (unq_mrs_en) { /* unique mode registers are supported */
1012 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1013 if (popts->rtt_override)
1014 rtt = popts->rtt_override_value;
1016 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1018 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1020 | ((rtt & 0x4) << 7) /* rtt field is split */
1021 | ((rtt & 0x2) << 5) /* rtt field is split */
1022 | ((rtt & 0x1) << 2) /* rtt field is split */
1026 ddr->ddr_sdram_mode_3 = (0
1027 | ((esdmode & 0xFFFF) << 16)
1028 | ((sdmode & 0xFFFF) << 0)
1032 ddr->ddr_sdram_mode_5 = (0
1033 | ((esdmode & 0xFFFF) << 16)
1034 | ((sdmode & 0xFFFF) << 0)
1038 ddr->ddr_sdram_mode_7 = (0
1039 | ((esdmode & 0xFFFF) << 16)
1040 | ((sdmode & 0xFFFF) << 0)
1045 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1046 ddr->ddr_sdram_mode_3);
1047 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1048 ddr->ddr_sdram_mode_5);
1049 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1050 ddr->ddr_sdram_mode_5);
1054 #else /* !CONFIG_FSL_DDR3 */
1056 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1057 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1058 const memctl_options_t *popts,
1059 const common_timing_params_t *common_dimm,
1060 unsigned int cas_latency,
1061 unsigned int additive_latency,
1062 const unsigned int unq_mrs_en)
1064 unsigned short esdmode; /* Extended SDRAM mode */
1065 unsigned short sdmode; /* SDRAM mode */
1068 * FIXME: This ought to be pre-calculated in a
1069 * technology-specific routine,
1070 * e.g. compute_DDR2_mode_register(), and then the
1071 * sdmode and esdmode passed in as part of common_dimm.
1074 /* Extended Mode Register */
1075 unsigned int mrs = 0; /* Mode Register Set */
1076 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1077 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1078 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1079 unsigned int ocd = 0; /* 0x0=OCD not supported,
1080 0x7=OCD default state */
1082 unsigned int al; /* Posted CAS# additive latency (AL) */
1083 unsigned int ods = 0; /* Output Drive Strength:
1084 0 = Full strength (18ohm)
1085 1 = Reduced strength (4ohm) */
1086 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1087 1=Disable (Test/Debug) */
1089 /* Mode Register (MR) */
1090 unsigned int mr; /* Mode Register Definition */
1091 unsigned int pd; /* Power-Down Mode */
1092 unsigned int wr; /* Write Recovery */
1093 unsigned int dll_res; /* DLL Reset */
1094 unsigned int mode; /* Normal=0 or Test=1 */
1095 unsigned int caslat = 0;/* CAS# latency */
1096 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1098 unsigned int bl; /* BL: Burst Length */
1100 #if defined(CONFIG_FSL_DDR2)
1101 const unsigned int mclk_ps = get_memory_clk_period_ps();
1103 dqs_en = !popts->DQS_config;
1104 rtt = fsl_ddr_get_rtt();
1106 al = additive_latency;
1109 | ((mrs & 0x3) << 14)
1110 | ((outputs & 0x1) << 12)
1111 | ((rdqs_en & 0x1) << 11)
1112 | ((dqs_en & 0x1) << 10)
1113 | ((ocd & 0x7) << 7)
1114 | ((rtt & 0x2) << 5) /* rtt field is split */
1116 | ((rtt & 0x1) << 2) /* rtt field is split */
1117 | ((ods & 0x1) << 1)
1118 | ((dll_en & 0x1) << 0)
1121 mr = 0; /* FIXME: CHECKME */
1124 * 0 = Fast Exit (Normal)
1125 * 1 = Slow Exit (Low Power)
1129 #if defined(CONFIG_FSL_DDR1)
1130 wr = 0; /* Historical */
1131 #elif defined(CONFIG_FSL_DDR2)
1132 wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
1137 #if defined(CONFIG_FSL_DDR1)
1138 if (1 <= cas_latency && cas_latency <= 4) {
1139 unsigned char mode_caslat_table[4] = {
1140 0x5, /* 1.5 clocks */
1141 0x2, /* 2.0 clocks */
1142 0x6, /* 2.5 clocks */
1143 0x3 /* 3.0 clocks */
1145 caslat = mode_caslat_table[cas_latency - 1];
1147 printf("Warning: unknown cas_latency %d\n", cas_latency);
1149 #elif defined(CONFIG_FSL_DDR2)
1150 caslat = cas_latency;
1154 switch (popts->burst_length) {
1162 printf("Error: invalid burst length of %u specified. "
1163 " Defaulting to 4 beats.\n",
1164 popts->burst_length);
1170 | ((mr & 0x3) << 14)
1171 | ((pd & 0x1) << 12)
1173 | ((dll_res & 0x1) << 8)
1174 | ((mode & 0x1) << 7)
1175 | ((caslat & 0x7) << 4)
1180 ddr->ddr_sdram_mode = (0
1181 | ((esdmode & 0xFFFF) << 16)
1182 | ((sdmode & 0xFFFF) << 0)
1184 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1188 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1189 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1191 unsigned int init_value; /* Initialization value */
1193 init_value = 0xDEADBEEF;
1194 ddr->ddr_data_init = init_value;
1198 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1199 * The old controller on the 8540/60 doesn't have this register.
1200 * Hope it's OK to set it (to 0) anyway.
1202 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1203 const memctl_options_t *popts)
1205 unsigned int clk_adjust; /* Clock adjust */
1207 clk_adjust = popts->clk_adjust;
1208 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1209 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1212 /* DDR Initialization Address (DDR_INIT_ADDR) */
1213 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1215 unsigned int init_addr = 0; /* Initialization address */
1217 ddr->ddr_init_addr = init_addr;
1220 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1221 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1223 unsigned int uia = 0; /* Use initialization address */
1224 unsigned int init_ext_addr = 0; /* Initialization address */
1226 ddr->ddr_init_ext_addr = (0
1227 | ((uia & 0x1) << 31)
1228 | (init_ext_addr & 0xF)
1232 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1233 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1234 const memctl_options_t *popts)
1236 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1237 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1238 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1239 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1240 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1242 #if defined(CONFIG_FSL_DDR3)
1243 if (popts->burst_length == DDR_BL8) {
1244 /* We set BL/2 for fixed BL8 */
1245 rrt = 0; /* BL/2 clocks */
1246 wwt = 0; /* BL/2 clocks */
1248 /* We need to set BL/2 + 2 to BC4 and OTF */
1249 rrt = 2; /* BL/2 + 2 clocks */
1250 wwt = 2; /* BL/2 + 2 clocks */
1252 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1254 ddr->timing_cfg_4 = (0
1255 | ((rwt & 0xf) << 28)
1256 | ((wrt & 0xf) << 24)
1257 | ((rrt & 0xf) << 20)
1258 | ((wwt & 0xf) << 16)
1261 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1264 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1265 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1267 unsigned int rodt_on = 0; /* Read to ODT on */
1268 unsigned int rodt_off = 0; /* Read to ODT off */
1269 unsigned int wodt_on = 0; /* Write to ODT on */
1270 unsigned int wodt_off = 0; /* Write to ODT off */
1272 #if defined(CONFIG_FSL_DDR3)
1273 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1274 rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1275 rodt_off = 4; /* 4 clocks */
1276 wodt_on = 1; /* 1 clocks */
1277 wodt_off = 4; /* 4 clocks */
1280 ddr->timing_cfg_5 = (0
1281 | ((rodt_on & 0x1f) << 24)
1282 | ((rodt_off & 0x7) << 20)
1283 | ((wodt_on & 0x1f) << 12)
1284 | ((wodt_off & 0x7) << 8)
1286 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1289 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1290 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1292 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1293 /* Normal Operation Full Calibration Time (tZQoper) */
1294 unsigned int zqoper = 0;
1295 /* Normal Operation Short Calibration Time (tZQCS) */
1296 unsigned int zqcs = 0;
1299 zqinit = 9; /* 512 clocks */
1300 zqoper = 8; /* 256 clocks */
1301 zqcs = 6; /* 64 clocks */
1304 ddr->ddr_zq_cntl = (0
1305 | ((zq_en & 0x1) << 31)
1306 | ((zqinit & 0xF) << 24)
1307 | ((zqoper & 0xF) << 16)
1308 | ((zqcs & 0xF) << 8)
1310 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1313 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1314 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1315 const memctl_options_t *popts)
1318 * First DQS pulse rising edge after margining mode
1319 * is programmed (tWL_MRD)
1321 unsigned int wrlvl_mrd = 0;
1322 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1323 unsigned int wrlvl_odten = 0;
1324 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1325 unsigned int wrlvl_dqsen = 0;
1326 /* WRLVL_SMPL: Write leveling sample time */
1327 unsigned int wrlvl_smpl = 0;
1328 /* WRLVL_WLR: Write leveling repeition time */
1329 unsigned int wrlvl_wlr = 0;
1330 /* WRLVL_START: Write leveling start time */
1331 unsigned int wrlvl_start = 0;
1333 /* suggest enable write leveling for DDR3 due to fly-by topology */
1335 /* tWL_MRD min = 40 nCK, we set it 64 */
1339 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1342 * Write leveling sample time at least need 6 clocks
1343 * higher than tWLO to allow enough time for progagation
1344 * delay and sampling the prime data bits.
1348 * Write leveling repetition time
1349 * at least tWLO + 6 clocks clocks
1354 * Write leveling start time
1355 * The value use for the DQS_ADJUST for the first sample
1356 * when write leveling is enabled. It probably needs to be
1357 * overriden per platform.
1361 * Override the write leveling sample and start time
1362 * according to specific board
1364 if (popts->wrlvl_override) {
1365 wrlvl_smpl = popts->wrlvl_sample;
1366 wrlvl_start = popts->wrlvl_start;
1370 ddr->ddr_wrlvl_cntl = (0
1371 | ((wrlvl_en & 0x1) << 31)
1372 | ((wrlvl_mrd & 0x7) << 24)
1373 | ((wrlvl_odten & 0x7) << 20)
1374 | ((wrlvl_dqsen & 0x7) << 16)
1375 | ((wrlvl_smpl & 0xf) << 12)
1376 | ((wrlvl_wlr & 0x7) << 8)
1377 | ((wrlvl_start & 0x1F) << 0)
1379 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1380 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
1381 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
1382 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
1383 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
1387 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1388 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1390 /* Self Refresh Idle Threshold */
1391 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1394 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1396 if (popts->addr_hash) {
1397 ddr->ddr_eor = 0x40000000; /* address hash enable */
1398 puts("Address hashing enabled.\n");
1402 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1404 ddr->ddr_cdr1 = popts->ddr_cdr1;
1405 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1408 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1410 ddr->ddr_cdr2 = popts->ddr_cdr2;
1411 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
1415 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1417 unsigned int res = 0;
1420 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1421 * not set at the same time.
1423 if (ddr->ddr_sdram_cfg & 0x10000000
1424 && ddr->ddr_sdram_cfg & 0x00008000) {
1425 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1426 " should not be set at the same time.\n");
1434 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1435 fsl_ddr_cfg_regs_t *ddr,
1436 const common_timing_params_t *common_dimm,
1437 const dimm_params_t *dimm_params,
1438 unsigned int dbw_cap_adj,
1439 unsigned int size_only)
1442 unsigned int cas_latency;
1443 unsigned int additive_latency;
1446 unsigned int wrlvl_en;
1447 unsigned int ip_rev = 0;
1448 unsigned int unq_mrs_en = 0;
1451 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1453 if (common_dimm == NULL) {
1454 printf("Error: subset DIMM params struct null pointer\n");
1459 * Process overrides first.
1461 * FIXME: somehow add dereated caslat to this
1463 cas_latency = (popts->cas_latency_override)
1464 ? popts->cas_latency_override_value
1465 : common_dimm->lowest_common_SPD_caslat;
1467 additive_latency = (popts->additive_latency_override)
1468 ? popts->additive_latency_override_value
1469 : common_dimm->additive_latency;
1471 sr_it = (popts->auto_self_refresh_en)
1474 /* ZQ calibration */
1475 zq_en = (popts->zq_en) ? 1 : 0;
1476 /* write leveling */
1477 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1479 /* Chip Select Memory Bounds (CSn_BNDS) */
1480 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1481 unsigned long long ea, sa;
1482 unsigned int cs_per_dimm
1483 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1484 unsigned int dimm_number
1486 unsigned long long rank_density
1487 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
1489 if (dimm_params[dimm_number].n_ranks == 0) {
1490 debug("Skipping setup of CS%u "
1491 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1494 if (popts->memctl_interleaving) {
1495 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1496 case FSL_DDR_CS0_CS1_CS2_CS3:
1498 case FSL_DDR_CS0_CS1:
1499 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1503 case FSL_DDR_CS2_CS3:
1509 sa = common_dimm->base_address;
1510 ea = sa + common_dimm->total_mem - 1;
1511 } else if (!popts->memctl_interleaving) {
1513 * If memory interleaving between controllers is NOT
1514 * enabled, the starting address for each memory
1515 * controller is distinct. However, because rank
1516 * interleaving is enabled, the starting and ending
1517 * addresses of the total memory on that memory
1518 * controller needs to be programmed into its
1519 * respective CS0_BNDS.
1521 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1522 case FSL_DDR_CS0_CS1_CS2_CS3:
1523 sa = common_dimm->base_address;
1524 ea = sa + common_dimm->total_mem - 1;
1526 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1527 if ((i >= 2) && (dimm_number == 0)) {
1528 sa = dimm_params[dimm_number].base_address +
1530 ea = sa + 2 * rank_density - 1;
1532 sa = dimm_params[dimm_number].base_address;
1533 ea = sa + 2 * rank_density - 1;
1536 case FSL_DDR_CS0_CS1:
1537 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1538 sa = dimm_params[dimm_number].base_address;
1539 ea = sa + rank_density - 1;
1541 sa += (i % cs_per_dimm) * rank_density;
1542 ea += (i % cs_per_dimm) * rank_density;
1550 case FSL_DDR_CS2_CS3:
1551 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1552 sa = dimm_params[dimm_number].base_address;
1553 ea = sa + rank_density - 1;
1555 sa += (i % cs_per_dimm) * rank_density;
1556 ea += (i % cs_per_dimm) * rank_density;
1562 ea += (rank_density >> dbw_cap_adj);
1564 default: /* No bank(chip-select) interleaving */
1565 sa = dimm_params[dimm_number].base_address;
1566 ea = sa + rank_density - 1;
1567 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1568 sa += (i % cs_per_dimm) * rank_density;
1569 ea += (i % cs_per_dimm) * rank_density;
1582 ddr->cs[i].bnds = (0
1583 | ((sa & 0xFFF) << 16)/* starting address MSB */
1584 | ((ea & 0xFFF) << 0) /* ending address MSB */
1587 debug("FSLDDR: setting bnds to 0 for inactive CS\n");
1588 ddr->cs[i].bnds = 0;
1591 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1592 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1593 set_csn_config_2(i, ddr);
1597 * In the case we only need to compute the ddr sdram size, we only need
1598 * to set csn registers, so return from here.
1603 set_ddr_eor(ddr, popts);
1605 #if !defined(CONFIG_FSL_DDR1)
1606 set_timing_cfg_0(ddr, popts, dimm_params);
1609 set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
1610 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1611 set_timing_cfg_2(ddr, popts, common_dimm,
1612 cas_latency, additive_latency);
1614 set_ddr_cdr1(ddr, popts);
1615 set_ddr_cdr2(ddr, popts);
1616 set_ddr_sdram_cfg(ddr, popts, common_dimm);
1617 ip_rev = fsl_ddr_get_version();
1618 if (ip_rev > 0x40400)
1621 set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1622 set_ddr_sdram_mode(ddr, popts, common_dimm,
1623 cas_latency, additive_latency, unq_mrs_en);
1624 set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
1625 set_ddr_sdram_interval(ddr, popts, common_dimm);
1626 set_ddr_data_init(ddr);
1627 set_ddr_sdram_clk_cntl(ddr, popts);
1628 set_ddr_init_addr(ddr);
1629 set_ddr_init_ext_addr(ddr);
1630 set_timing_cfg_4(ddr, popts);
1631 set_timing_cfg_5(ddr, cas_latency);
1633 set_ddr_zq_cntl(ddr, zq_en);
1634 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1636 set_ddr_sr_cntr(ddr, sr_it);
1638 set_ddr_sdram_rcw(ddr, popts, common_dimm);
1640 return check_fsl_memctl_config_regs(ddr);