git.sur5r.net Git - u-boot/blob - arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 /*
  11  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  12  * Based on code from spd_sdram.c
  13  * Author: James Yang [at freescale.com]
  14  */
  15
  16 #include <common.h>
  17 #include <asm/fsl_ddr_sdram.h>
  18
  19 #include "ddr.h"
  20
  21 #ifdef CONFIG_MPC85xx
  22         #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
  23 #elif defined(CONFIG_MPC86xx)
  24         #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
  25 #else
  26         #error "Undefined _DDR_ADDR"
  27 #endif
  28
  29 u32 fsl_ddr_get_version(void)
  30 {
  31         ccsr_ddr_t *ddr;
  32         u32 ver_major_minor_errata;
  33
  34         ddr = (void *)_DDR_ADDR;
  35         ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
  36         ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
  37
  38         return ver_major_minor_errata;
  39 }
  40
  41 unsigned int picos_to_mclk(unsigned int picos);
  42
  43 /*
  44  * Determine Rtt value.
  45  *
  46  * This should likely be either board or controller specific.
  47  *
  48  * Rtt(nominal) - DDR2:
  49  *      0 = Rtt disabled
  50  *      1 = 75 ohm
  51  *      2 = 150 ohm
  52  *      3 = 50 ohm
  53  * Rtt(nominal) - DDR3:
  54  *      0 = Rtt disabled
  55  *      1 = 60 ohm
  56  *      2 = 120 ohm
  57  *      3 = 40 ohm
  58  *      4 = 20 ohm
  59  *      5 = 30 ohm
  60  *
  61  * FIXME: Apparently 8641 needs a value of 2
  62  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  63  *
  64  * FIXME: There was some effort down this line earlier:
  65  *
  66  *      unsigned int i;
  67  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  68  *              if (popts->dimmslot[i].num_valid_cs
  69  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  70  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  71  *                      rtt = 2;
  72  *                      break;
  73  *              }
  74  *      }
  75  */
  76 static inline int fsl_ddr_get_rtt(void)
  77 {
  78         int rtt;
  79
  80 #if defined(CONFIG_FSL_DDR1)
  81         rtt = 0;
  82 #elif defined(CONFIG_FSL_DDR2)
  83         rtt = 3;
  84 #else
  85         rtt = 0;
  86 #endif
  87
  88         return rtt;
  89 }
  90
  91 /*
  92  * compute the CAS write latency according to DDR3 spec
  93  * CWL = 5 if tCK >= 2.5ns
  94  *       6 if 2.5ns > tCK >= 1.875ns
  95  *       7 if 1.875ns > tCK >= 1.5ns
  96  *       8 if 1.5ns > tCK >= 1.25ns
  97  *       9 if 1.25ns > tCK >= 1.07ns
  98  *       10 if 1.07ns > tCK >= 0.935ns
  99  *       11 if 0.935ns > tCK >= 0.833ns
 100  *       12 if 0.833ns > tCK >= 0.75ns
 101  */
 102 static inline unsigned int compute_cas_write_latency(void)
 103 {
 104         unsigned int cwl;
 105         const unsigned int mclk_ps = get_memory_clk_period_ps();
 106
 107         if (mclk_ps >= 2500)
 108                 cwl = 5;
 109         else if (mclk_ps >= 1875)
 110                 cwl = 6;
 111         else if (mclk_ps >= 1500)
 112                 cwl = 7;
 113         else if (mclk_ps >= 1250)
 114                 cwl = 8;
 115         else if (mclk_ps >= 1070)
 116                 cwl = 9;
 117         else if (mclk_ps >= 935)
 118                 cwl = 10;
 119         else if (mclk_ps >= 833)
 120                 cwl = 11;
 121         else if (mclk_ps >= 750)
 122                 cwl = 12;
 123         else {
 124                 cwl = 12;
 125                 printf("Warning: CWL is out of range\n");
 126         }
 127         return cwl;
 128 }
 129
 130 /* Chip Select Configuration (CSn_CONFIG) */
 131 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 132                                const memctl_options_t *popts,
 133                                const dimm_params_t *dimm_params)
 134 {
 135         unsigned int cs_n_en = 0; /* Chip Select enable */
 136         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 137         unsigned int intlv_ctl = 0; /* Interleaving control */
 138         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 139         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 140         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 141         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 142         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 143         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 144         int go_config = 0;
 145
 146         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 147         switch (i) {
 148         case 0:
 149                 if (dimm_params[dimm_number].n_ranks > 0) {
 150                         go_config = 1;
 151                         /* These fields only available in CS0_CONFIG */
 152                         intlv_en = popts->memctl_interleaving;
 153                         intlv_ctl = popts->memctl_interleaving_mode;
 154                 }
 155                 break;
 156         case 1:
 157                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 158                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 159                         go_config = 1;
 160                 break;
 161         case 2:
 162                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 163                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 164                         go_config = 1;
 165                 break;
 166         case 3:
 167                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 168                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 169                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 170                         go_config = 1;
 171                 break;
 172         default:
 173                 break;
 174         }
 175         if (go_config) {
 176                 unsigned int n_banks_per_sdram_device;
 177                 cs_n_en = 1;
 178                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 179                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 180                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 181                 n_banks_per_sdram_device
 182                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 183                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 184                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 185                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 186         }
 187         ddr->cs[i].config = (0
 188                 | ((cs_n_en & 0x1) << 31)
 189                 | ((intlv_en & 0x3) << 29)
 190                 | ((intlv_ctl & 0xf) << 24)
 191                 | ((ap_n_en & 0x1) << 23)
 192
 193                 /* XXX: some implementation only have 1 bit starting at left */
 194                 | ((odt_rd_cfg & 0x7) << 20)
 195
 196                 /* XXX: Some implementation only have 1 bit starting at left */
 197                 | ((odt_wr_cfg & 0x7) << 16)
 198
 199                 | ((ba_bits_cs_n & 0x3) << 14)
 200                 | ((row_bits_cs_n & 0x7) << 8)
 201                 | ((col_bits_cs_n & 0x7) << 0)
 202                 );
 203         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 204 }
 205
 206 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 207 /* FIXME: 8572 */
 208 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 209 {
 210         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 211
 212         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 213         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 214 }
 215
 216 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 217
 218 #if !defined(CONFIG_FSL_DDR1)
 219 /*
 220  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 221  *
 222  * Avoid writing for DDR I.  The new PQ38 DDR controller
 223  * dreams up non-zero default values to be backwards compatible.
 224  */
 225 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 226                                 const memctl_options_t *popts)
 227 {
 228         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 229         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 230         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 231         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 232         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 233
 234         /* Active powerdown exit timing (tXARD and tXARDS). */
 235         unsigned char act_pd_exit_mclk;
 236         /* Precharge powerdown exit timing (tXP). */
 237         unsigned char pre_pd_exit_mclk;
 238         /* ODT powerdown exit timing (tAXPD). */
 239         unsigned char taxpd_mclk;
 240         /* Mode register set cycle time (tMRD). */
 241         unsigned char tmrd_mclk;
 242
 243 #ifdef CONFIG_FSL_DDR3
 244         /*
 245          * (tXARD and tXARDS). Empirical?
 246          * The DDR3 spec has not tXARD,
 247          * we use the tXP instead of it.
 248          * tXP=max(3nCK, 7.5ns) for DDR3.
 249          * spec has not the tAXPD, we use
 250          * tAXPD=1, need design to confirm.
 251          */
 252         int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
 253         unsigned int data_rate = get_ddr_freq(0);
 254         tmrd_mclk = 4;
 255         /* set the turnaround time */
 256         trwt_mclk = 1;
 257         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 258                 twrt_mclk = 1;
 259
 260         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 261                 act_pd_exit_mclk = 1;
 262                 pre_pd_exit_mclk = 1;
 263                 taxpd_mclk = 1;
 264         } else {
 265                 /* act_pd_exit_mclk = tXARD, see above */
 266                 act_pd_exit_mclk = picos_to_mclk(tXP);
 267                 /* Mode register MR0[A12] is '1' - fast exit */
 268                 pre_pd_exit_mclk = act_pd_exit_mclk;
 269                 taxpd_mclk = 1;
 270         }
 271 #else /* CONFIG_FSL_DDR2 */
 272         /*
 273          * (tXARD and tXARDS). Empirical?
 274          * tXARD = 2 for DDR2
 275          * tXP=2
 276          * tAXPD=8
 277          */
 278         act_pd_exit_mclk = 2;
 279         pre_pd_exit_mclk = 2;
 280         taxpd_mclk = 8;
 281         tmrd_mclk = 2;
 282 #endif
 283
 284         if (popts->trwt_override)
 285                 trwt_mclk = popts->trwt;
 286
 287         ddr->timing_cfg_0 = (0
 288                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 289                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 290                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 291                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 292                 | ((act_pd_exit_mclk & 0x7) << 20)  /* ACT_PD_EXIT */
 293                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 294                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 295                 | ((tmrd_mclk & 0xf) << 0)      /* MRS_CYC */
 296                 );
 297         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 298 }
 299 #endif  /* defined(CONFIG_FSL_DDR2) */
 300
 301 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 302 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 303                                const common_timing_params_t *common_dimm,
 304                                unsigned int cas_latency)
 305 {
 306         /* Extended Activate to precharge interval (tRAS) */
 307         unsigned int ext_acttopre = 0;
 308         unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
 309         unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
 310         unsigned int cntl_adj = 0; /* Control Adjust */
 311
 312         /* If the tRAS > 19 MCLK, we use the ext mode */
 313         if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
 314                 ext_acttopre = 1;
 315
 316         ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
 317
 318         /* If the CAS latency more than 8, use the ext mode */
 319         if (cas_latency > 8)
 320                 ext_caslat = 1;
 321
 322         ddr->timing_cfg_3 = (0
 323                 | ((ext_acttopre & 0x1) << 24)
 324                 | ((ext_refrec & 0xF) << 16)
 325                 | ((ext_caslat & 0x1) << 12)
 326                 | ((cntl_adj & 0x7) << 0)
 327                 );
 328         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 329 }
 330
 331 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 332 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 333                                const memctl_options_t *popts,
 334                                const common_timing_params_t *common_dimm,
 335                                unsigned int cas_latency)
 336 {
 337         /* Precharge-to-activate interval (tRP) */
 338         unsigned char pretoact_mclk;
 339         /* Activate to precharge interval (tRAS) */
 340         unsigned char acttopre_mclk;
 341         /*  Activate to read/write interval (tRCD) */
 342         unsigned char acttorw_mclk;
 343         /* CASLAT */
 344         unsigned char caslat_ctrl;
 345         /*  Refresh recovery time (tRFC) ; trfc_low */
 346         unsigned char refrec_ctrl;
 347         /* Last data to precharge minimum interval (tWR) */
 348         unsigned char wrrec_mclk;
 349         /* Activate-to-activate interval (tRRD) */
 350         unsigned char acttoact_mclk;
 351         /* Last write data pair to read command issue interval (tWTR) */
 352         unsigned char wrtord_mclk;
 353         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 354         static const u8 wrrec_table[] = {
 355                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 356
 357         pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
 358         acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
 359         acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
 360
 361         /*
 362          * Translate CAS Latency to a DDR controller field value:
 363          *
 364          *      CAS Lat DDR I   DDR II  Ctrl
 365          *      Clocks  SPD Bit SPD Bit Value
 366          *      ------- ------- ------- -----
 367          *      1.0     0               0001
 368          *      1.5     1               0010
 369          *      2.0     2       2       0011
 370          *      2.5     3               0100
 371          *      3.0     4       3       0101
 372          *      3.5     5               0110
 373          *      4.0             4       0111
 374          *      4.5                     1000
 375          *      5.0             5       1001
 376          */
 377 #if defined(CONFIG_FSL_DDR1)
 378         caslat_ctrl = (cas_latency + 1) & 0x07;
 379 #elif defined(CONFIG_FSL_DDR2)
 380         caslat_ctrl = 2 * cas_latency - 1;
 381 #else
 382         /*
 383          * if the CAS latency more than 8 cycle,
 384          * we need set extend bit for it at
 385          * TIMING_CFG_3[EXT_CASLAT]
 386          */
 387         if (cas_latency > 8)
 388                 cas_latency -= 8;
 389         caslat_ctrl = 2 * cas_latency - 1;
 390 #endif
 391
 392         refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
 393         wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
 394
 395         wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 396         if (popts->OTF_burst_chop_en)
 397                 wrrec_mclk += 2;
 398
 399         acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
 400         /*
 401          * JEDEC has min requirement for tRRD
 402          */
 403 #if defined(CONFIG_FSL_DDR3)
 404         if (acttoact_mclk < 4)
 405                 acttoact_mclk = 4;
 406 #endif
 407         wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
 408         /*
 409          * JEDEC has some min requirements for tWTR
 410          */
 411 #if defined(CONFIG_FSL_DDR2)
 412         if (wrtord_mclk < 2)
 413                 wrtord_mclk = 2;
 414 #elif defined(CONFIG_FSL_DDR3)
 415         if (wrtord_mclk < 4)
 416                 wrtord_mclk = 4;
 417 #endif
 418         if (popts->OTF_burst_chop_en)
 419                 wrtord_mclk += 2;
 420
 421         ddr->timing_cfg_1 = (0
 422                 | ((pretoact_mclk & 0x0F) << 28)
 423                 | ((acttopre_mclk & 0x0F) << 24)
 424                 | ((acttorw_mclk & 0xF) << 20)
 425                 | ((caslat_ctrl & 0xF) << 16)
 426                 | ((refrec_ctrl & 0xF) << 12)
 427                 | ((wrrec_mclk & 0x0F) << 8)
 428                 | ((acttoact_mclk & 0x07) << 4)
 429                 | ((wrtord_mclk & 0x07) << 0)
 430                 );
 431         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 432 }
 433
 434 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 435 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 436                                const memctl_options_t *popts,
 437                                const common_timing_params_t *common_dimm,
 438                                unsigned int cas_latency,
 439                                unsigned int additive_latency)
 440 {
 441         /* Additive latency */
 442         unsigned char add_lat_mclk;
 443         /* CAS-to-preamble override */
 444         unsigned short cpo;
 445         /* Write latency */
 446         unsigned char wr_lat;
 447         /*  Read to precharge (tRTP) */
 448         unsigned char rd_to_pre;
 449         /* Write command to write data strobe timing adjustment */
 450         unsigned char wr_data_delay;
 451         /* Minimum CKE pulse width (tCKE) */
 452         unsigned char cke_pls;
 453         /* Window for four activates (tFAW) */
 454         unsigned short four_act;
 455
 456         /* FIXME add check that this must be less than acttorw_mclk */
 457         add_lat_mclk = additive_latency;
 458         cpo = popts->cpo_override;
 459
 460 #if defined(CONFIG_FSL_DDR1)
 461         /*
 462          * This is a lie.  It should really be 1, but if it is
 463          * set to 1, bits overlap into the old controller's
 464          * otherwise unused ACSM field.  If we leave it 0, then
 465          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 466          */
 467         wr_lat = 0;
 468 #elif defined(CONFIG_FSL_DDR2)
 469         wr_lat = cas_latency - 1;
 470 #else
 471         wr_lat = compute_cas_write_latency();
 472 #endif
 473
 474         rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
 475         /*
 476          * JEDEC has some min requirements for tRTP
 477          */
 478 #if defined(CONFIG_FSL_DDR2)
 479         if (rd_to_pre  < 2)
 480                 rd_to_pre  = 2;
 481 #elif defined(CONFIG_FSL_DDR3)
 482         if (rd_to_pre < 4)
 483                 rd_to_pre = 4;
 484 #endif
 485         if (additive_latency)
 486                 rd_to_pre += additive_latency;
 487         if (popts->OTF_burst_chop_en)
 488                 rd_to_pre += 2; /* according to UM */
 489
 490         wr_data_delay = popts->write_data_delay;
 491         cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
 492         four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
 493
 494         ddr->timing_cfg_2 = (0
 495                 | ((add_lat_mclk & 0xf) << 28)
 496                 | ((cpo & 0x1f) << 23)
 497                 | ((wr_lat & 0xf) << 19)
 498                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 499                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 500                 | ((cke_pls & 0x7) << 6)
 501                 | ((four_act & 0x3f) << 0)
 502                 );
 503         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 504 }
 505
 506 /* DDR SDRAM Register Control Word */
 507 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 508                                const memctl_options_t *popts,
 509                                const common_timing_params_t *common_dimm)
 510 {
 511         if (common_dimm->all_DIMMs_registered
 512                 && !common_dimm->all_DIMMs_unbuffered) {
 513                 if (popts->rcw_override) {
 514                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 515                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 516                 } else {
 517                         ddr->ddr_sdram_rcw_1 =
 518                                 common_dimm->rcw[0] << 28 | \
 519                                 common_dimm->rcw[1] << 24 | \
 520                                 common_dimm->rcw[2] << 20 | \
 521                                 common_dimm->rcw[3] << 16 | \
 522                                 common_dimm->rcw[4] << 12 | \
 523                                 common_dimm->rcw[5] << 8 | \
 524                                 common_dimm->rcw[6] << 4 | \
 525                                 common_dimm->rcw[7];
 526                         ddr->ddr_sdram_rcw_2 =
 527                                 common_dimm->rcw[8] << 28 | \
 528                                 common_dimm->rcw[9] << 24 | \
 529                                 common_dimm->rcw[10] << 20 | \
 530                                 common_dimm->rcw[11] << 16 | \
 531                                 common_dimm->rcw[12] << 12 | \
 532                                 common_dimm->rcw[13] << 8 | \
 533                                 common_dimm->rcw[14] << 4 | \
 534                                 common_dimm->rcw[15];
 535                 }
 536                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 537                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 538         }
 539 }
 540
 541 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 542 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 543                                const memctl_options_t *popts,
 544                                const common_timing_params_t *common_dimm)
 545 {
 546         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 547         unsigned int sren;              /* Self refresh enable (during sleep) */
 548         unsigned int ecc_en;            /* ECC enable. */
 549         unsigned int rd_en;             /* Registered DIMM enable */
 550         unsigned int sdram_type;        /* Type of SDRAM */
 551         unsigned int dyn_pwr;           /* Dynamic power management mode */
 552         unsigned int dbw;               /* DRAM dta bus width */
 553         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 554         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 555         unsigned int threeT_en;         /* Enable 3T timing */
 556         unsigned int twoT_en;           /* Enable 2T timing */
 557         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 558         unsigned int x32_en = 0;        /* x32 enable */
 559         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 560         unsigned int hse;               /* Global half strength override */
 561         unsigned int mem_halt = 0;      /* memory controller halt */
 562         unsigned int bi = 0;            /* Bypass initialization */
 563
 564         mem_en = 1;
 565         sren = popts->self_refresh_in_sleep;
 566         if (common_dimm->all_DIMMs_ECC_capable) {
 567                 /* Allow setting of ECC only if all DIMMs are ECC. */
 568                 ecc_en = popts->ECC_mode;
 569         } else {
 570                 ecc_en = 0;
 571         }
 572
 573         if (common_dimm->all_DIMMs_registered
 574                 && !common_dimm->all_DIMMs_unbuffered) {
 575                 rd_en = 1;
 576                 twoT_en = 0;
 577         } else {
 578                 rd_en = 0;
 579                 twoT_en = popts->twoT_en;
 580         }
 581
 582         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 583
 584         dyn_pwr = popts->dynamic_power;
 585         dbw = popts->data_bus_width;
 586         /* 8-beat burst enable DDR-III case
 587          * we must clear it when use the on-the-fly mode,
 588          * must set it when use the 32-bits bus mode.
 589          */
 590         if (sdram_type == SDRAM_TYPE_DDR3) {
 591                 if (popts->burst_length == DDR_BL8)
 592                         eight_be = 1;
 593                 if (popts->burst_length == DDR_OTF)
 594                         eight_be = 0;
 595                 if (dbw == 0x1)
 596                         eight_be = 1;
 597         }
 598
 599         threeT_en = popts->threeT_en;
 600         ba_intlv_ctl = popts->ba_intlv_ctl;
 601         hse = popts->half_strength_driver_enable;
 602
 603         ddr->ddr_sdram_cfg = (0
 604                         | ((mem_en & 0x1) << 31)
 605                         | ((sren & 0x1) << 30)
 606                         | ((ecc_en & 0x1) << 29)
 607                         | ((rd_en & 0x1) << 28)
 608                         | ((sdram_type & 0x7) << 24)
 609                         | ((dyn_pwr & 0x1) << 21)
 610                         | ((dbw & 0x3) << 19)
 611                         | ((eight_be & 0x1) << 18)
 612                         | ((ncap & 0x1) << 17)
 613                         | ((threeT_en & 0x1) << 16)
 614                         | ((twoT_en & 0x1) << 15)
 615                         | ((ba_intlv_ctl & 0x7F) << 8)
 616                         | ((x32_en & 0x1) << 5)
 617                         | ((pchb8 & 0x1) << 4)
 618                         | ((hse & 0x1) << 3)
 619                         | ((mem_halt & 0x1) << 1)
 620                         | ((bi & 0x1) << 0)
 621                         );
 622         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 623 }
 624
 625 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 626 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 627                                const memctl_options_t *popts,
 628                                const unsigned int unq_mrs_en)
 629 {
 630         unsigned int frc_sr = 0;        /* Force self refresh */
 631         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 632         unsigned int dll_rst_dis;       /* DLL reset disable */
 633         unsigned int dqs_cfg;           /* DQS configuration */
 634         unsigned int odt_cfg = 0;       /* ODT configuration */
 635         unsigned int num_pr;            /* Number of posted refreshes */
 636         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 637         unsigned int ap_en;             /* Address Parity Enable */
 638         unsigned int d_init;            /* DRAM data initialization */
 639         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 640         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 641         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 642         int i;
 643
 644         dll_rst_dis = 1;        /* Make this configurable */
 645         dqs_cfg = popts->DQS_config;
 646         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 647                 if (popts->cs_local_opts[i].odt_rd_cfg
 648                         || popts->cs_local_opts[i].odt_wr_cfg) {
 649                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 650                         break;
 651                 }
 652         }
 653
 654         num_pr = 1;     /* Make this configurable */
 655
 656         /*
 657          * 8572 manual says
 658          *     {TIMING_CFG_1[PRETOACT]
 659          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 660          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 661          *      << DDR_SDRAM_INTERVAL[REFINT]
 662          */
 663 #if defined(CONFIG_FSL_DDR3)
 664         obc_cfg = popts->OTF_burst_chop_en;
 665 #else
 666         obc_cfg = 0;
 667 #endif
 668
 669         if (popts->registered_dimm_en) {
 670                 rcw_en = 1;
 671                 ap_en = popts->ap_en;
 672         } else {
 673                 rcw_en = 0;
 674                 ap_en = 0;
 675         }
 676
 677 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 678         /* Use the DDR controller to auto initialize memory. */
 679         d_init = popts->ECC_init_using_memctl;
 680         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 681         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 682 #else
 683         /* Memory will be initialized via DMA, or not at all. */
 684         d_init = 0;
 685 #endif
 686
 687 #if defined(CONFIG_FSL_DDR3)
 688         md_en = popts->mirrored_dimm;
 689 #endif
 690         qd_en = popts->quad_rank_present ? 1 : 0;
 691         ddr->ddr_sdram_cfg_2 = (0
 692                 | ((frc_sr & 0x1) << 31)
 693                 | ((sr_ie & 0x1) << 30)
 694                 | ((dll_rst_dis & 0x1) << 29)
 695                 | ((dqs_cfg & 0x3) << 26)
 696                 | ((odt_cfg & 0x3) << 21)
 697                 | ((num_pr & 0xf) << 12)
 698                 | (qd_en << 9)
 699                 | (unq_mrs_en << 8)
 700                 | ((obc_cfg & 0x1) << 6)
 701                 | ((ap_en & 0x1) << 5)
 702                 | ((d_init & 0x1) << 4)
 703 #ifdef CONFIG_FSL_DDR3
 704                 | ((rcw_en & 0x1) << 2)
 705 #endif
 706                 | ((md_en & 0x1) << 0)
 707                 );
 708         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 709 }
 710
 711 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 712 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 713                                 const memctl_options_t *popts,
 714                                 const unsigned int unq_mrs_en)
 715 {
 716         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 717         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 718
 719 #if defined(CONFIG_FSL_DDR3)
 720         int i;
 721         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 722         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 723         unsigned int asr = 0;   /* auto self-refresh disable */
 724         unsigned int cwl = compute_cas_write_latency() - 5;
 725         unsigned int pasr = 0;  /* partial array self refresh disable */
 726
 727         if (popts->rtt_override)
 728                 rtt_wr = popts->rtt_wr_override_value;
 729         else
 730                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 731         esdmode2 = (0
 732                 | ((rtt_wr & 0x3) << 9)
 733                 | ((srt & 0x1) << 7)
 734                 | ((asr & 0x1) << 6)
 735                 | ((cwl & 0x7) << 3)
 736                 | ((pasr & 0x7) << 0));
 737 #endif
 738         ddr->ddr_sdram_mode_2 = (0
 739                                  | ((esdmode2 & 0xFFFF) << 16)
 740                                  | ((esdmode3 & 0xFFFF) << 0)
 741                                  );
 742         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 743
 744 #ifdef CONFIG_FSL_DDR3
 745         if (unq_mrs_en) {       /* unique mode registers are supported */
 746                 for (i = 1; i < 4; i++) {
 747                         if (popts->rtt_override)
 748                                 rtt_wr = popts->rtt_wr_override_value;
 749                         else
 750                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 751
 752                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 753                         esdmode2 |= (rtt_wr & 0x3) << 9;
 754                         switch (i) {
 755                         case 1:
 756                                 ddr->ddr_sdram_mode_4 = (0
 757                                         | ((esdmode2 & 0xFFFF) << 16)
 758                                         | ((esdmode3 & 0xFFFF) << 0)
 759                                         );
 760                                 break;
 761                         case 2:
 762                                 ddr->ddr_sdram_mode_6 = (0
 763                                         | ((esdmode2 & 0xFFFF) << 16)
 764                                         | ((esdmode3 & 0xFFFF) << 0)
 765                                         );
 766                                 break;
 767                         case 3:
 768                                 ddr->ddr_sdram_mode_8 = (0
 769                                         | ((esdmode2 & 0xFFFF) << 16)
 770                                         | ((esdmode3 & 0xFFFF) << 0)
 771                                         );
 772                                 break;
 773                         }
 774                 }
 775                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
 776                         ddr->ddr_sdram_mode_4);
 777                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
 778                         ddr->ddr_sdram_mode_6);
 779                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
 780                         ddr->ddr_sdram_mode_8);
 781         }
 782 #endif
 783 }
 784
 785 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
 786 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 787                                const memctl_options_t *popts,
 788                                const common_timing_params_t *common_dimm)
 789 {
 790         unsigned int refint;    /* Refresh interval */
 791         unsigned int bstopre;   /* Precharge interval */
 792
 793         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
 794
 795         bstopre = popts->bstopre;
 796
 797         /* refint field used 0x3FFF in earlier controllers */
 798         ddr->ddr_sdram_interval = (0
 799                                    | ((refint & 0xFFFF) << 16)
 800                                    | ((bstopre & 0x3FFF) << 0)
 801                                    );
 802         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 803 }
 804
 805 #if defined(CONFIG_FSL_DDR3)
 806 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 807 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 808                                const memctl_options_t *popts,
 809                                const common_timing_params_t *common_dimm,
 810                                unsigned int cas_latency,
 811                                unsigned int additive_latency,
 812                                const unsigned int unq_mrs_en)
 813 {
 814         unsigned short esdmode;         /* Extended SDRAM mode */
 815         unsigned short sdmode;          /* SDRAM mode */
 816
 817         /* Mode Register - MR1 */
 818         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
 819         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
 820         unsigned int rtt;
 821         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
 822         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
 823         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
 824         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 825                                                        1=Disable (Test/Debug) */
 826
 827         /* Mode Register - MR0 */
 828         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
 829         unsigned int wr;        /* Write Recovery */
 830         unsigned int dll_rst;   /* DLL Reset */
 831         unsigned int mode;      /* Normal=0 or Test=1 */
 832         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
 833         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
 834         unsigned int bt;
 835         unsigned int bl;        /* BL: Burst Length */
 836
 837         unsigned int wr_mclk;
 838         /*
 839          * DDR_SDRAM_MODE doesn't support 9,11,13,15
 840          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
 841          * for this table
 842          */
 843         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
 844
 845         const unsigned int mclk_ps = get_memory_clk_period_ps();
 846         int i;
 847
 848         if (popts->rtt_override)
 849                 rtt = popts->rtt_override_value;
 850         else
 851                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
 852
 853         if (additive_latency == (cas_latency - 1))
 854                 al = 1;
 855         if (additive_latency == (cas_latency - 2))
 856                 al = 2;
 857
 858         if (popts->quad_rank_present)
 859                 dic = 1;        /* output driver impedance 240/7 ohm */
 860
 861         /*
 862          * The esdmode value will also be used for writing
 863          * MR1 during write leveling for DDR3, although the
 864          * bits specifically related to the write leveling
 865          * scheme will be handled automatically by the DDR
 866          * controller. so we set the wrlvl_en = 0 here.
 867          */
 868         esdmode = (0
 869                 | ((qoff & 0x1) << 12)
 870                 | ((tdqs_en & 0x1) << 11)
 871                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 872                 | ((wrlvl_en & 0x1) << 7)
 873                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 874                 | ((dic & 0x2) << 4)   /* DIC field is split */
 875                 | ((al & 0x3) << 3)
 876                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 877                 | ((dic & 0x1) << 1)   /* DIC field is split */
 878                 | ((dll_en & 0x1) << 0)
 879                 );
 880
 881         /*
 882          * DLL control for precharge PD
 883          * 0=slow exit DLL off (tXPDLL)
 884          * 1=fast exit DLL on (tXP)
 885          */
 886         dll_on = 1;
 887
 888         wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
 889         wr = wr_table[wr_mclk - 5];
 890
 891         dll_rst = 0;    /* dll no reset */
 892         mode = 0;       /* normal mode */
 893
 894         /* look up table to get the cas latency bits */
 895         if (cas_latency >= 5 && cas_latency <= 11) {
 896                 unsigned char cas_latency_table[7] = {
 897                         0x2,    /* 5 clocks */
 898                         0x4,    /* 6 clocks */
 899                         0x6,    /* 7 clocks */
 900                         0x8,    /* 8 clocks */
 901                         0xa,    /* 9 clocks */
 902                         0xc,    /* 10 clocks */
 903                         0xe     /* 11 clocks */
 904                 };
 905                 caslat = cas_latency_table[cas_latency - 5];
 906         }
 907         bt = 0; /* Nibble sequential */
 908
 909         switch (popts->burst_length) {
 910         case DDR_BL8:
 911                 bl = 0;
 912                 break;
 913         case DDR_OTF:
 914                 bl = 1;
 915                 break;
 916         case DDR_BC4:
 917                 bl = 2;
 918                 break;
 919         default:
 920                 printf("Error: invalid burst length of %u specified. "
 921                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
 922                         popts->burst_length);
 923                 bl = 1;
 924                 break;
 925         }
 926
 927         sdmode = (0
 928                   | ((dll_on & 0x1) << 12)
 929                   | ((wr & 0x7) << 9)
 930                   | ((dll_rst & 0x1) << 8)
 931                   | ((mode & 0x1) << 7)
 932                   | (((caslat >> 1) & 0x7) << 4)
 933                   | ((bt & 0x1) << 3)
 934                   | ((bl & 0x3) << 0)
 935                   );
 936
 937         ddr->ddr_sdram_mode = (0
 938                                | ((esdmode & 0xFFFF) << 16)
 939                                | ((sdmode & 0xFFFF) << 0)
 940                                );
 941
 942         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
 943
 944         if (unq_mrs_en) {       /* unique mode registers are supported */
 945                 for (i = 1; i < 4; i++) {
 946                         if (popts->rtt_override)
 947                                 rtt = popts->rtt_override_value;
 948                         else
 949                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
 950
 951                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
 952                         esdmode |= (0
 953                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 954                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 955                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 956                                 );
 957                         switch (i) {
 958                         case 1:
 959                                 ddr->ddr_sdram_mode_3 = (0
 960                                        | ((esdmode & 0xFFFF) << 16)
 961                                        | ((sdmode & 0xFFFF) << 0)
 962                                        );
 963                                 break;
 964                         case 2:
 965                                 ddr->ddr_sdram_mode_5 = (0
 966                                        | ((esdmode & 0xFFFF) << 16)
 967                                        | ((sdmode & 0xFFFF) << 0)
 968                                        );
 969                                 break;
 970                         case 3:
 971                                 ddr->ddr_sdram_mode_7 = (0
 972                                        | ((esdmode & 0xFFFF) << 16)
 973                                        | ((sdmode & 0xFFFF) << 0)
 974                                        );
 975                                 break;
 976                         }
 977                 }
 978                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
 979                         ddr->ddr_sdram_mode_3);
 980                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
 981                         ddr->ddr_sdram_mode_5);
 982                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
 983                         ddr->ddr_sdram_mode_5);
 984         }
 985 }
 986
 987 #else /* !CONFIG_FSL_DDR3 */
 988
 989 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 990 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 991                                const memctl_options_t *popts,
 992                                const common_timing_params_t *common_dimm,
 993                                unsigned int cas_latency,
 994                                unsigned int additive_latency,
 995                                const unsigned int unq_mrs_en)
 996 {
 997         unsigned short esdmode;         /* Extended SDRAM mode */
 998         unsigned short sdmode;          /* SDRAM mode */
 999
1000         /*
1001          * FIXME: This ought to be pre-calculated in a
1002          * technology-specific routine,
1003          * e.g. compute_DDR2_mode_register(), and then the
1004          * sdmode and esdmode passed in as part of common_dimm.
1005          */
1006
1007         /* Extended Mode Register */
1008         unsigned int mrs = 0;           /* Mode Register Set */
1009         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1010         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1011         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1012         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1013                                            0x7=OCD default state */
1014         unsigned int rtt;
1015         unsigned int al;                /* Posted CAS# additive latency (AL) */
1016         unsigned int ods = 0;           /* Output Drive Strength:
1017                                                 0 = Full strength (18ohm)
1018                                                 1 = Reduced strength (4ohm) */
1019         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1020                                                        1=Disable (Test/Debug) */
1021
1022         /* Mode Register (MR) */
1023         unsigned int mr;        /* Mode Register Definition */
1024         unsigned int pd;        /* Power-Down Mode */
1025         unsigned int wr;        /* Write Recovery */
1026         unsigned int dll_res;   /* DLL Reset */
1027         unsigned int mode;      /* Normal=0 or Test=1 */
1028         unsigned int caslat = 0;/* CAS# latency */
1029         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1030         unsigned int bt;
1031         unsigned int bl;        /* BL: Burst Length */
1032
1033 #if defined(CONFIG_FSL_DDR2)
1034         const unsigned int mclk_ps = get_memory_clk_period_ps();
1035 #endif
1036         dqs_en = !popts->DQS_config;
1037         rtt = fsl_ddr_get_rtt();
1038
1039         al = additive_latency;
1040
1041         esdmode = (0
1042                 | ((mrs & 0x3) << 14)
1043                 | ((outputs & 0x1) << 12)
1044                 | ((rdqs_en & 0x1) << 11)
1045                 | ((dqs_en & 0x1) << 10)
1046                 | ((ocd & 0x7) << 7)
1047                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1048                 | ((al & 0x7) << 3)
1049                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1050                 | ((ods & 0x1) << 1)
1051                 | ((dll_en & 0x1) << 0)
1052                 );
1053
1054         mr = 0;          /* FIXME: CHECKME */
1055
1056         /*
1057          * 0 = Fast Exit (Normal)
1058          * 1 = Slow Exit (Low Power)
1059          */
1060         pd = 0;
1061
1062 #if defined(CONFIG_FSL_DDR1)
1063         wr = 0;       /* Historical */
1064 #elif defined(CONFIG_FSL_DDR2)
1065         wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
1066 #endif
1067         dll_res = 0;
1068         mode = 0;
1069
1070 #if defined(CONFIG_FSL_DDR1)
1071         if (1 <= cas_latency && cas_latency <= 4) {
1072                 unsigned char mode_caslat_table[4] = {
1073                         0x5,    /* 1.5 clocks */
1074                         0x2,    /* 2.0 clocks */
1075                         0x6,    /* 2.5 clocks */
1076                         0x3     /* 3.0 clocks */
1077                 };
1078                 caslat = mode_caslat_table[cas_latency - 1];
1079         } else {
1080                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1081         }
1082 #elif defined(CONFIG_FSL_DDR2)
1083         caslat = cas_latency;
1084 #endif
1085         bt = 0;
1086
1087         switch (popts->burst_length) {
1088         case DDR_BL4:
1089                 bl = 2;
1090                 break;
1091         case DDR_BL8:
1092                 bl = 3;
1093                 break;
1094         default:
1095                 printf("Error: invalid burst length of %u specified. "
1096                         " Defaulting to 4 beats.\n",
1097                         popts->burst_length);
1098                 bl = 2;
1099                 break;
1100         }
1101
1102         sdmode = (0
1103                   | ((mr & 0x3) << 14)
1104                   | ((pd & 0x1) << 12)
1105                   | ((wr & 0x7) << 9)
1106                   | ((dll_res & 0x1) << 8)
1107                   | ((mode & 0x1) << 7)
1108                   | ((caslat & 0x7) << 4)
1109                   | ((bt & 0x1) << 3)
1110                   | ((bl & 0x7) << 0)
1111                   );
1112
1113         ddr->ddr_sdram_mode = (0
1114                                | ((esdmode & 0xFFFF) << 16)
1115                                | ((sdmode & 0xFFFF) << 0)
1116                                );
1117         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1118 }
1119 #endif
1120
1121 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1122 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1123 {
1124         unsigned int init_value;        /* Initialization value */
1125
1126         init_value = 0xDEADBEEF;
1127         ddr->ddr_data_init = init_value;
1128 }
1129
1130 /*
1131  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1132  * The old controller on the 8540/60 doesn't have this register.
1133  * Hope it's OK to set it (to 0) anyway.
1134  */
1135 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1136                                          const memctl_options_t *popts)
1137 {
1138         unsigned int clk_adjust;        /* Clock adjust */
1139
1140         clk_adjust = popts->clk_adjust;
1141         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1142         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1143 }
1144
1145 /* DDR Initialization Address (DDR_INIT_ADDR) */
1146 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1147 {
1148         unsigned int init_addr = 0;     /* Initialization address */
1149
1150         ddr->ddr_init_addr = init_addr;
1151 }
1152
1153 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1154 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1155 {
1156         unsigned int uia = 0;   /* Use initialization address */
1157         unsigned int init_ext_addr = 0; /* Initialization address */
1158
1159         ddr->ddr_init_ext_addr = (0
1160                                   | ((uia & 0x1) << 31)
1161                                   | (init_ext_addr & 0xF)
1162                                   );
1163 }
1164
1165 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1166 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1167                                 const memctl_options_t *popts)
1168 {
1169         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1170         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1171         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1172         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1173         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1174
1175 #if defined(CONFIG_FSL_DDR3)
1176         if (popts->burst_length == DDR_BL8) {
1177                 /* We set BL/2 for fixed BL8 */
1178                 rrt = 0;        /* BL/2 clocks */
1179                 wwt = 0;        /* BL/2 clocks */
1180         } else {
1181                 /* We need to set BL/2 + 2 to BC4 and OTF */
1182                 rrt = 2;        /* BL/2 + 2 clocks */
1183                 wwt = 2;        /* BL/2 + 2 clocks */
1184         }
1185         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1186 #endif
1187         ddr->timing_cfg_4 = (0
1188                              | ((rwt & 0xf) << 28)
1189                              | ((wrt & 0xf) << 24)
1190                              | ((rrt & 0xf) << 20)
1191                              | ((wwt & 0xf) << 16)
1192                              | (dll_lock & 0x3)
1193                              );
1194         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1195 }
1196
1197 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1198 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1199 {
1200         unsigned int rodt_on = 0;       /* Read to ODT on */
1201         unsigned int rodt_off = 0;      /* Read to ODT off */
1202         unsigned int wodt_on = 0;       /* Write to ODT on */
1203         unsigned int wodt_off = 0;      /* Write to ODT off */
1204
1205 #if defined(CONFIG_FSL_DDR3)
1206         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1207         rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1208         rodt_off = 4;   /*  4 clocks */
1209         wodt_on = 1;    /*  1 clocks */
1210         wodt_off = 4;   /*  4 clocks */
1211 #endif
1212
1213         ddr->timing_cfg_5 = (0
1214                              | ((rodt_on & 0x1f) << 24)
1215                              | ((rodt_off & 0x7) << 20)
1216                              | ((wodt_on & 0x1f) << 12)
1217                              | ((wodt_off & 0x7) << 8)
1218                              );
1219         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1220 }
1221
1222 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1223 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1224 {
1225         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1226         /* Normal Operation Full Calibration Time (tZQoper) */
1227         unsigned int zqoper = 0;
1228         /* Normal Operation Short Calibration Time (tZQCS) */
1229         unsigned int zqcs = 0;
1230
1231         if (zq_en) {
1232                 zqinit = 9;     /* 512 clocks */
1233                 zqoper = 8;     /* 256 clocks */
1234                 zqcs = 6;       /* 64 clocks */
1235         }
1236
1237         ddr->ddr_zq_cntl = (0
1238                             | ((zq_en & 0x1) << 31)
1239                             | ((zqinit & 0xF) << 24)
1240                             | ((zqoper & 0xF) << 16)
1241                             | ((zqcs & 0xF) << 8)
1242                             );
1243         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1244 }
1245
1246 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1247 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1248                                 const memctl_options_t *popts)
1249 {
1250         /*
1251          * First DQS pulse rising edge after margining mode
1252          * is programmed (tWL_MRD)
1253          */
1254         unsigned int wrlvl_mrd = 0;
1255         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1256         unsigned int wrlvl_odten = 0;
1257         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1258         unsigned int wrlvl_dqsen = 0;
1259         /* WRLVL_SMPL: Write leveling sample time */
1260         unsigned int wrlvl_smpl = 0;
1261         /* WRLVL_WLR: Write leveling repeition time */
1262         unsigned int wrlvl_wlr = 0;
1263         /* WRLVL_START: Write leveling start time */
1264         unsigned int wrlvl_start = 0;
1265
1266         /* suggest enable write leveling for DDR3 due to fly-by topology */
1267         if (wrlvl_en) {
1268                 /* tWL_MRD min = 40 nCK, we set it 64 */
1269                 wrlvl_mrd = 0x6;
1270                 /* tWL_ODTEN 128 */
1271                 wrlvl_odten = 0x7;
1272                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1273                 wrlvl_dqsen = 0x5;
1274                 /*
1275                  * Write leveling sample time at least need 6 clocks
1276                  * higher than tWLO to allow enough time for progagation
1277                  * delay and sampling the prime data bits.
1278                  */
1279                 wrlvl_smpl = 0xf;
1280                 /*
1281                  * Write leveling repetition time
1282                  * at least tWLO + 6 clocks clocks
1283                  * we set it 64
1284                  */
1285                 wrlvl_wlr = 0x6;
1286                 /*
1287                  * Write leveling start time
1288                  * The value use for the DQS_ADJUST for the first sample
1289                  * when write leveling is enabled. It probably needs to be
1290                  * overriden per platform.
1291                  */
1292                 wrlvl_start = 0x8;
1293                 /*
1294                  * Override the write leveling sample and start time
1295                  * according to specific board
1296                  */
1297                 if (popts->wrlvl_override) {
1298                         wrlvl_smpl = popts->wrlvl_sample;
1299                         wrlvl_start = popts->wrlvl_start;
1300                 }
1301         }
1302
1303         ddr->ddr_wrlvl_cntl = (0
1304                                | ((wrlvl_en & 0x1) << 31)
1305                                | ((wrlvl_mrd & 0x7) << 24)
1306                                | ((wrlvl_odten & 0x7) << 20)
1307                                | ((wrlvl_dqsen & 0x7) << 16)
1308                                | ((wrlvl_smpl & 0xf) << 12)
1309                                | ((wrlvl_wlr & 0x7) << 8)
1310                                | ((wrlvl_start & 0x1F) << 0)
1311                                );
1312         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1313 }
1314
1315 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1316 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1317 {
1318         /* Self Refresh Idle Threshold */
1319         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1320 }
1321
1322 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1323 {
1324         if (popts->addr_hash) {
1325                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
1326                 puts("Address hashing enabled.\n");
1327         }
1328 }
1329
1330 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1331 {
1332         ddr->ddr_cdr1 = popts->ddr_cdr1;
1333         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1334 }
1335
1336 unsigned int
1337 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1338 {
1339         unsigned int res = 0;
1340
1341         /*
1342          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1343          * not set at the same time.
1344          */
1345         if (ddr->ddr_sdram_cfg & 0x10000000
1346             && ddr->ddr_sdram_cfg & 0x00008000) {
1347                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1348                                 " should not be set at the same time.\n");
1349                 res++;
1350         }
1351
1352         return res;
1353 }
1354
1355 unsigned int
1356 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1357                                fsl_ddr_cfg_regs_t *ddr,
1358                                const common_timing_params_t *common_dimm,
1359                                const dimm_params_t *dimm_params,
1360                                unsigned int dbw_cap_adj,
1361                                unsigned int size_only)
1362 {
1363         unsigned int i;
1364         unsigned int cas_latency;
1365         unsigned int additive_latency;
1366         unsigned int sr_it;
1367         unsigned int zq_en;
1368         unsigned int wrlvl_en;
1369         unsigned int ip_rev = 0;
1370         unsigned int unq_mrs_en = 0;
1371         int cs_en = 1;
1372
1373         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1374
1375         if (common_dimm == NULL) {
1376                 printf("Error: subset DIMM params struct null pointer\n");
1377                 return 1;
1378         }
1379
1380         /*
1381          * Process overrides first.
1382          *
1383          * FIXME: somehow add dereated caslat to this
1384          */
1385         cas_latency = (popts->cas_latency_override)
1386                 ? popts->cas_latency_override_value
1387                 : common_dimm->lowest_common_SPD_caslat;
1388
1389         additive_latency = (popts->additive_latency_override)
1390                 ? popts->additive_latency_override_value
1391                 : common_dimm->additive_latency;
1392
1393         sr_it = (popts->auto_self_refresh_en)
1394                 ? popts->sr_it
1395                 : 0;
1396         /* ZQ calibration */
1397         zq_en = (popts->zq_en) ? 1 : 0;
1398         /* write leveling */
1399         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1400
1401         /* Chip Select Memory Bounds (CSn_BNDS) */
1402         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1403                 unsigned long long ea = 0, sa = 0;
1404                 unsigned int cs_per_dimm
1405                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1406                 unsigned int dimm_number
1407                         = i / cs_per_dimm;
1408                 unsigned long long rank_density
1409                         = dimm_params[dimm_number].rank_density;
1410
1411                 if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) ||
1412                         ((i == 2) && (popts->ba_intlv_ctl & 0x04)) ||
1413                         ((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) {
1414                         /*
1415                          * Don't set up boundaries for unused CS
1416                          * cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1417                          * cs2 for cs0_cs1_cs2_cs3
1418                          * cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1419                          * But we need to set the ODT_RD_CFG and
1420                          * ODT_WR_CFG for CS1_CONFIG here.
1421                          */
1422                         set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1423                         continue;
1424                 }
1425                 if (dimm_params[dimm_number].n_ranks == 0) {
1426                         debug("Skipping setup of CS%u "
1427                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1428                         continue;
1429                 }
1430                 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
1431                         /*
1432                          * This works superbank 2CS
1433                          * There are 2 or more memory controllers configured
1434                          * identically, memory is interleaved between them,
1435                          * and each controller uses rank interleaving within
1436                          * itself. Therefore the starting and ending address
1437                          * on each controller is twice the amount present on
1438                          * each controller. If any CS is not included in the
1439                          * interleaving, the memory on that CS is not accssible
1440                          * and the total memory size is reduced. The CS is also
1441                          * disabled.
1442                          */
1443                         unsigned long long ctlr_density = 0;
1444                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1445                         case FSL_DDR_CS0_CS1:
1446                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1447                                 ctlr_density = dimm_params[0].rank_density * 2;
1448                                 if (i > 1)
1449                                         cs_en = 0;
1450                                 break;
1451                         case FSL_DDR_CS2_CS3:
1452                                 ctlr_density = dimm_params[0].rank_density;
1453                                 if (i > 0)
1454                                         cs_en = 0;
1455                                 break;
1456                         case FSL_DDR_CS0_CS1_CS2_CS3:
1457                                 /*
1458                                  * The four CS interleaving should have been verified by
1459                                  * populate_memctl_options()
1460                                  */
1461                                 ctlr_density = dimm_params[0].rank_density * 4;
1462                                 break;
1463                         default:
1464                                 break;
1465                         }
1466                         ea = (CONFIG_NUM_DDR_CONTROLLERS *
1467                                 (ctlr_density >> dbw_cap_adj)) - 1;
1468                 }
1469                 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
1470                         /*
1471                          * If memory interleaving between controllers is NOT
1472                          * enabled, the starting address for each memory
1473                          * controller is distinct.  However, because rank
1474                          * interleaving is enabled, the starting and ending
1475                          * addresses of the total memory on that memory
1476                          * controller needs to be programmed into its
1477                          * respective CS0_BNDS.
1478                          */
1479                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1480                         case FSL_DDR_CS0_CS1_CS2_CS3:
1481                                 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
1482                                  * needs to be set.
1483                                  */
1484                                 sa = common_dimm->base_address;
1485                                 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
1486                                 break;
1487                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1488                                 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
1489                                  * and CS2_CNDS need to be set.
1490                                  */
1491                                 if ((i == 2) && (dimm_number == 0)) {
1492                                         sa = dimm_params[dimm_number].base_address +
1493                                               2 * (rank_density >> dbw_cap_adj);
1494                                         ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1;
1495                                 } else {
1496                                         sa = dimm_params[dimm_number].base_address;
1497                                         ea = sa + (2 * (rank_density >>
1498                                                 dbw_cap_adj)) - 1;
1499                                 }
1500                                 break;
1501                         case FSL_DDR_CS0_CS1:
1502                                 /* CS0+CS1 interleaving, CS0_CNDS needs
1503                                  * to be set
1504                                  */
1505                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1506                                         sa = dimm_params[dimm_number].base_address;
1507                                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1508                                         sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1509                                         ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1510                                 } else {
1511                                         sa = 0;
1512                                         ea = 0;
1513                                 }
1514                                 if (i == 0)
1515                                         ea += (rank_density >> dbw_cap_adj);
1516                                 break;
1517                         case FSL_DDR_CS2_CS3:
1518                                 /* CS2+CS3 interleaving*/
1519                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1520                                         sa = dimm_params[dimm_number].base_address;
1521                                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1522                                         sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1523                                         ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1524                                 } else {
1525                                         sa = 0;
1526                                         ea = 0;
1527                                 }
1528                                 if (i == 2)
1529                                         ea += (rank_density >> dbw_cap_adj);
1530                                 break;
1531                         default:  /* No bank(chip-select) interleaving */
1532                                 break;
1533                         }
1534                 }
1535                 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1536                         /*
1537                          * Only the rank on CS0 of each memory controller may
1538                          * be used if memory controller interleaving is used
1539                          * without rank interleaving within each memory
1540                          * controller.  However, the ending address programmed
1541                          * into each CS0 must be the sum of the amount of
1542                          * memory in the two CS0 ranks.
1543                          */
1544                         if (i == 0) {
1545                                 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1546                         }
1547
1548                 }
1549                 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1550                         /*
1551                          * No rank interleaving and no memory controller
1552                          * interleaving.
1553                          */
1554                         sa = dimm_params[dimm_number].base_address;
1555                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1556                         if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1557                                 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1558                                 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1559                         } else {
1560                                 sa = 0;
1561                                 ea = 0;
1562                         }
1563                 }
1564
1565                 sa >>= 24;
1566                 ea >>= 24;
1567
1568                 ddr->cs[i].bnds = (0
1569                         | ((sa & 0xFFF) << 16)  /* starting address MSB */
1570                         | ((ea & 0xFFF) << 0)   /* ending address MSB */
1571                         );
1572
1573                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1574                 if (cs_en) {
1575                         set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1576                         set_csn_config_2(i, ddr);
1577                 } else
1578                         printf("CS%d is disabled.\n", i);
1579         }
1580
1581         /*
1582          * In the case we only need to compute the ddr sdram size, we only need
1583          * to set csn registers, so return from here.
1584          */
1585         if (size_only)
1586                 return 0;
1587
1588         set_ddr_eor(ddr, popts);
1589
1590 #if !defined(CONFIG_FSL_DDR1)
1591         set_timing_cfg_0(ddr, popts);
1592 #endif
1593
1594         set_timing_cfg_3(ddr, common_dimm, cas_latency);
1595         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1596         set_timing_cfg_2(ddr, popts, common_dimm,
1597                                 cas_latency, additive_latency);
1598
1599         set_ddr_cdr1(ddr, popts);
1600         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1601         ip_rev = fsl_ddr_get_version();
1602         if (ip_rev > 0x40400)
1603                 unq_mrs_en = 1;
1604
1605         set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1606         set_ddr_sdram_mode(ddr, popts, common_dimm,
1607                                 cas_latency, additive_latency, unq_mrs_en);
1608         set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
1609         set_ddr_sdram_interval(ddr, popts, common_dimm);
1610         set_ddr_data_init(ddr);
1611         set_ddr_sdram_clk_cntl(ddr, popts);
1612         set_ddr_init_addr(ddr);
1613         set_ddr_init_ext_addr(ddr);
1614         set_timing_cfg_4(ddr, popts);
1615         set_timing_cfg_5(ddr, cas_latency);
1616
1617         set_ddr_zq_cntl(ddr, zq_en);
1618         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1619
1620         set_ddr_sr_cntr(ddr, sr_it);
1621
1622         set_ddr_sdram_rcw(ddr, popts, common_dimm);
1623
1624         return check_fsl_memctl_config_regs(ddr);
1625 }