2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
11 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
12 * Based on code from spd_sdram.c
13 * Author: James Yang [at freescale.com]
17 #include <asm/fsl_ddr_sdram.h>
22 #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
23 #elif defined(CONFIG_MPC86xx)
24 #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
26 #error "Undefined _DDR_ADDR"
29 u32 fsl_ddr_get_version(void)
32 u32 ver_major_minor_errata;
34 ddr = (void *)_DDR_ADDR;
35 ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
36 ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
38 return ver_major_minor_errata;
41 unsigned int picos_to_mclk(unsigned int picos);
44 * Determine Rtt value.
46 * This should likely be either board or controller specific.
48 * Rtt(nominal) - DDR2:
53 * Rtt(nominal) - DDR3:
61 * FIXME: Apparently 8641 needs a value of 2
62 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
64 * FIXME: There was some effort down this line earlier:
67 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
68 * if (popts->dimmslot[i].num_valid_cs
69 * && (popts->cs_local_opts[2*i].odt_rd_cfg
70 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
76 static inline int fsl_ddr_get_rtt(void)
80 #if defined(CONFIG_FSL_DDR1)
82 #elif defined(CONFIG_FSL_DDR2)
92 * compute the CAS write latency according to DDR3 spec
93 * CWL = 5 if tCK >= 2.5ns
94 * 6 if 2.5ns > tCK >= 1.875ns
95 * 7 if 1.875ns > tCK >= 1.5ns
96 * 8 if 1.5ns > tCK >= 1.25ns
97 * 9 if 1.25ns > tCK >= 1.07ns
98 * 10 if 1.07ns > tCK >= 0.935ns
99 * 11 if 0.935ns > tCK >= 0.833ns
100 * 12 if 0.833ns > tCK >= 0.75ns
102 static inline unsigned int compute_cas_write_latency(void)
105 const unsigned int mclk_ps = get_memory_clk_period_ps();
109 else if (mclk_ps >= 1875)
111 else if (mclk_ps >= 1500)
113 else if (mclk_ps >= 1250)
115 else if (mclk_ps >= 1070)
117 else if (mclk_ps >= 935)
119 else if (mclk_ps >= 833)
121 else if (mclk_ps >= 750)
125 printf("Warning: CWL is out of range\n");
130 /* Chip Select Configuration (CSn_CONFIG) */
131 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
132 const memctl_options_t *popts,
133 const dimm_params_t *dimm_params)
135 unsigned int cs_n_en = 0; /* Chip Select enable */
136 unsigned int intlv_en = 0; /* Memory controller interleave enable */
137 unsigned int intlv_ctl = 0; /* Interleaving control */
138 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
139 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
140 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
141 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
142 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
143 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
146 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
149 if (dimm_params[dimm_number].n_ranks > 0) {
151 /* These fields only available in CS0_CONFIG */
152 intlv_en = popts->memctl_interleaving;
153 intlv_ctl = popts->memctl_interleaving_mode;
157 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
158 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
162 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
163 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
167 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
168 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
169 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
176 unsigned int n_banks_per_sdram_device;
178 ap_n_en = popts->cs_local_opts[i].auto_precharge;
179 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
180 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
181 n_banks_per_sdram_device
182 = dimm_params[dimm_number].n_banks_per_sdram_device;
183 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
184 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
185 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
187 ddr->cs[i].config = (0
188 | ((cs_n_en & 0x1) << 31)
189 | ((intlv_en & 0x3) << 29)
190 | ((intlv_ctl & 0xf) << 24)
191 | ((ap_n_en & 0x1) << 23)
193 /* XXX: some implementation only have 1 bit starting at left */
194 | ((odt_rd_cfg & 0x7) << 20)
196 /* XXX: Some implementation only have 1 bit starting at left */
197 | ((odt_wr_cfg & 0x7) << 16)
199 | ((ba_bits_cs_n & 0x3) << 14)
200 | ((row_bits_cs_n & 0x7) << 8)
201 | ((col_bits_cs_n & 0x7) << 0)
203 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
206 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
208 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
210 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
212 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
213 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
216 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
218 #if !defined(CONFIG_FSL_DDR1)
220 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
222 * Avoid writing for DDR I. The new PQ38 DDR controller
223 * dreams up non-zero default values to be backwards compatible.
225 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
226 const memctl_options_t *popts)
228 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
229 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
230 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
231 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
232 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
234 /* Active powerdown exit timing (tXARD and tXARDS). */
235 unsigned char act_pd_exit_mclk;
236 /* Precharge powerdown exit timing (tXP). */
237 unsigned char pre_pd_exit_mclk;
238 /* ODT powerdown exit timing (tAXPD). */
239 unsigned char taxpd_mclk;
240 /* Mode register set cycle time (tMRD). */
241 unsigned char tmrd_mclk;
243 #ifdef CONFIG_FSL_DDR3
245 * (tXARD and tXARDS). Empirical?
246 * The DDR3 spec has not tXARD,
247 * we use the tXP instead of it.
248 * tXP=max(3nCK, 7.5ns) for DDR3.
249 * spec has not the tAXPD, we use
250 * tAXPD=1, need design to confirm.
252 int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
253 unsigned int data_rate = get_ddr_freq(0);
255 /* set the turnaround time */
257 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
260 if (popts->dynamic_power == 0) { /* powerdown is not used */
261 act_pd_exit_mclk = 1;
262 pre_pd_exit_mclk = 1;
265 /* act_pd_exit_mclk = tXARD, see above */
266 act_pd_exit_mclk = picos_to_mclk(tXP);
267 /* Mode register MR0[A12] is '1' - fast exit */
268 pre_pd_exit_mclk = act_pd_exit_mclk;
271 #else /* CONFIG_FSL_DDR2 */
273 * (tXARD and tXARDS). Empirical?
278 act_pd_exit_mclk = 2;
279 pre_pd_exit_mclk = 2;
284 if (popts->trwt_override)
285 trwt_mclk = popts->trwt;
287 ddr->timing_cfg_0 = (0
288 | ((trwt_mclk & 0x3) << 30) /* RWT */
289 | ((twrt_mclk & 0x3) << 28) /* WRT */
290 | ((trrt_mclk & 0x3) << 26) /* RRT */
291 | ((twwt_mclk & 0x3) << 24) /* WWT */
292 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
293 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
294 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
295 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
297 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
299 #endif /* defined(CONFIG_FSL_DDR2) */
301 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
302 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
303 const common_timing_params_t *common_dimm,
304 unsigned int cas_latency)
306 /* Extended Activate to precharge interval (tRAS) */
307 unsigned int ext_acttopre = 0;
308 unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
309 unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
310 unsigned int cntl_adj = 0; /* Control Adjust */
312 /* If the tRAS > 19 MCLK, we use the ext mode */
313 if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
316 ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
318 /* If the CAS latency more than 8, use the ext mode */
322 ddr->timing_cfg_3 = (0
323 | ((ext_acttopre & 0x1) << 24)
324 | ((ext_refrec & 0xF) << 16)
325 | ((ext_caslat & 0x1) << 12)
326 | ((cntl_adj & 0x7) << 0)
328 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
331 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
332 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
333 const memctl_options_t *popts,
334 const common_timing_params_t *common_dimm,
335 unsigned int cas_latency)
337 /* Precharge-to-activate interval (tRP) */
338 unsigned char pretoact_mclk;
339 /* Activate to precharge interval (tRAS) */
340 unsigned char acttopre_mclk;
341 /* Activate to read/write interval (tRCD) */
342 unsigned char acttorw_mclk;
344 unsigned char caslat_ctrl;
345 /* Refresh recovery time (tRFC) ; trfc_low */
346 unsigned char refrec_ctrl;
347 /* Last data to precharge minimum interval (tWR) */
348 unsigned char wrrec_mclk;
349 /* Activate-to-activate interval (tRRD) */
350 unsigned char acttoact_mclk;
351 /* Last write data pair to read command issue interval (tWTR) */
352 unsigned char wrtord_mclk;
353 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
354 static const u8 wrrec_table[] = {
355 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
357 pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
358 acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
359 acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
362 * Translate CAS Latency to a DDR controller field value:
364 * CAS Lat DDR I DDR II Ctrl
365 * Clocks SPD Bit SPD Bit Value
366 * ------- ------- ------- -----
377 #if defined(CONFIG_FSL_DDR1)
378 caslat_ctrl = (cas_latency + 1) & 0x07;
379 #elif defined(CONFIG_FSL_DDR2)
380 caslat_ctrl = 2 * cas_latency - 1;
383 * if the CAS latency more than 8 cycle,
384 * we need set extend bit for it at
385 * TIMING_CFG_3[EXT_CASLAT]
389 caslat_ctrl = 2 * cas_latency - 1;
392 refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
393 wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
395 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
396 if (popts->OTF_burst_chop_en)
399 acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
401 * JEDEC has min requirement for tRRD
403 #if defined(CONFIG_FSL_DDR3)
404 if (acttoact_mclk < 4)
407 wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
409 * JEDEC has some min requirements for tWTR
411 #if defined(CONFIG_FSL_DDR2)
414 #elif defined(CONFIG_FSL_DDR3)
418 if (popts->OTF_burst_chop_en)
421 ddr->timing_cfg_1 = (0
422 | ((pretoact_mclk & 0x0F) << 28)
423 | ((acttopre_mclk & 0x0F) << 24)
424 | ((acttorw_mclk & 0xF) << 20)
425 | ((caslat_ctrl & 0xF) << 16)
426 | ((refrec_ctrl & 0xF) << 12)
427 | ((wrrec_mclk & 0x0F) << 8)
428 | ((acttoact_mclk & 0x07) << 4)
429 | ((wrtord_mclk & 0x07) << 0)
431 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
434 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
435 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
436 const memctl_options_t *popts,
437 const common_timing_params_t *common_dimm,
438 unsigned int cas_latency,
439 unsigned int additive_latency)
441 /* Additive latency */
442 unsigned char add_lat_mclk;
443 /* CAS-to-preamble override */
446 unsigned char wr_lat;
447 /* Read to precharge (tRTP) */
448 unsigned char rd_to_pre;
449 /* Write command to write data strobe timing adjustment */
450 unsigned char wr_data_delay;
451 /* Minimum CKE pulse width (tCKE) */
452 unsigned char cke_pls;
453 /* Window for four activates (tFAW) */
454 unsigned short four_act;
456 /* FIXME add check that this must be less than acttorw_mclk */
457 add_lat_mclk = additive_latency;
458 cpo = popts->cpo_override;
460 #if defined(CONFIG_FSL_DDR1)
462 * This is a lie. It should really be 1, but if it is
463 * set to 1, bits overlap into the old controller's
464 * otherwise unused ACSM field. If we leave it 0, then
465 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
468 #elif defined(CONFIG_FSL_DDR2)
469 wr_lat = cas_latency - 1;
471 wr_lat = compute_cas_write_latency();
474 rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
476 * JEDEC has some min requirements for tRTP
478 #if defined(CONFIG_FSL_DDR2)
481 #elif defined(CONFIG_FSL_DDR3)
485 if (additive_latency)
486 rd_to_pre += additive_latency;
487 if (popts->OTF_burst_chop_en)
488 rd_to_pre += 2; /* according to UM */
490 wr_data_delay = popts->write_data_delay;
491 cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
492 four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
494 ddr->timing_cfg_2 = (0
495 | ((add_lat_mclk & 0xf) << 28)
496 | ((cpo & 0x1f) << 23)
497 | ((wr_lat & 0xf) << 19)
498 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
499 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
500 | ((cke_pls & 0x7) << 6)
501 | ((four_act & 0x3f) << 0)
503 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
506 /* DDR SDRAM Register Control Word */
507 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
508 const memctl_options_t *popts,
509 const common_timing_params_t *common_dimm)
511 if (common_dimm->all_DIMMs_registered
512 && !common_dimm->all_DIMMs_unbuffered) {
513 if (popts->rcw_override) {
514 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
515 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
517 ddr->ddr_sdram_rcw_1 =
518 common_dimm->rcw[0] << 28 | \
519 common_dimm->rcw[1] << 24 | \
520 common_dimm->rcw[2] << 20 | \
521 common_dimm->rcw[3] << 16 | \
522 common_dimm->rcw[4] << 12 | \
523 common_dimm->rcw[5] << 8 | \
524 common_dimm->rcw[6] << 4 | \
526 ddr->ddr_sdram_rcw_2 =
527 common_dimm->rcw[8] << 28 | \
528 common_dimm->rcw[9] << 24 | \
529 common_dimm->rcw[10] << 20 | \
530 common_dimm->rcw[11] << 16 | \
531 common_dimm->rcw[12] << 12 | \
532 common_dimm->rcw[13] << 8 | \
533 common_dimm->rcw[14] << 4 | \
534 common_dimm->rcw[15];
536 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
537 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
541 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
542 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
543 const memctl_options_t *popts,
544 const common_timing_params_t *common_dimm)
546 unsigned int mem_en; /* DDR SDRAM interface logic enable */
547 unsigned int sren; /* Self refresh enable (during sleep) */
548 unsigned int ecc_en; /* ECC enable. */
549 unsigned int rd_en; /* Registered DIMM enable */
550 unsigned int sdram_type; /* Type of SDRAM */
551 unsigned int dyn_pwr; /* Dynamic power management mode */
552 unsigned int dbw; /* DRAM dta bus width */
553 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
554 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
555 unsigned int threeT_en; /* Enable 3T timing */
556 unsigned int twoT_en; /* Enable 2T timing */
557 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
558 unsigned int x32_en = 0; /* x32 enable */
559 unsigned int pchb8 = 0; /* precharge bit 8 enable */
560 unsigned int hse; /* Global half strength override */
561 unsigned int mem_halt = 0; /* memory controller halt */
562 unsigned int bi = 0; /* Bypass initialization */
565 sren = popts->self_refresh_in_sleep;
566 if (common_dimm->all_DIMMs_ECC_capable) {
567 /* Allow setting of ECC only if all DIMMs are ECC. */
568 ecc_en = popts->ECC_mode;
573 if (common_dimm->all_DIMMs_registered
574 && !common_dimm->all_DIMMs_unbuffered) {
579 twoT_en = popts->twoT_en;
582 sdram_type = CONFIG_FSL_SDRAM_TYPE;
584 dyn_pwr = popts->dynamic_power;
585 dbw = popts->data_bus_width;
586 /* 8-beat burst enable DDR-III case
587 * we must clear it when use the on-the-fly mode,
588 * must set it when use the 32-bits bus mode.
590 if (sdram_type == SDRAM_TYPE_DDR3) {
591 if (popts->burst_length == DDR_BL8)
593 if (popts->burst_length == DDR_OTF)
599 threeT_en = popts->threeT_en;
600 ba_intlv_ctl = popts->ba_intlv_ctl;
601 hse = popts->half_strength_driver_enable;
603 ddr->ddr_sdram_cfg = (0
604 | ((mem_en & 0x1) << 31)
605 | ((sren & 0x1) << 30)
606 | ((ecc_en & 0x1) << 29)
607 | ((rd_en & 0x1) << 28)
608 | ((sdram_type & 0x7) << 24)
609 | ((dyn_pwr & 0x1) << 21)
610 | ((dbw & 0x3) << 19)
611 | ((eight_be & 0x1) << 18)
612 | ((ncap & 0x1) << 17)
613 | ((threeT_en & 0x1) << 16)
614 | ((twoT_en & 0x1) << 15)
615 | ((ba_intlv_ctl & 0x7F) << 8)
616 | ((x32_en & 0x1) << 5)
617 | ((pchb8 & 0x1) << 4)
619 | ((mem_halt & 0x1) << 1)
622 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
625 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
626 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
627 const memctl_options_t *popts,
628 const unsigned int unq_mrs_en)
630 unsigned int frc_sr = 0; /* Force self refresh */
631 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
632 unsigned int dll_rst_dis; /* DLL reset disable */
633 unsigned int dqs_cfg; /* DQS configuration */
634 unsigned int odt_cfg = 0; /* ODT configuration */
635 unsigned int num_pr; /* Number of posted refreshes */
636 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
637 unsigned int ap_en; /* Address Parity Enable */
638 unsigned int d_init; /* DRAM data initialization */
639 unsigned int rcw_en = 0; /* Register Control Word Enable */
640 unsigned int md_en = 0; /* Mirrored DIMM Enable */
641 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
644 dll_rst_dis = 1; /* Make this configurable */
645 dqs_cfg = popts->DQS_config;
646 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
647 if (popts->cs_local_opts[i].odt_rd_cfg
648 || popts->cs_local_opts[i].odt_wr_cfg) {
649 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
654 num_pr = 1; /* Make this configurable */
658 * {TIMING_CFG_1[PRETOACT]
659 * + [DDR_SDRAM_CFG_2[NUM_PR]
660 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
661 * << DDR_SDRAM_INTERVAL[REFINT]
663 #if defined(CONFIG_FSL_DDR3)
664 obc_cfg = popts->OTF_burst_chop_en;
669 if (popts->registered_dimm_en) {
671 ap_en = popts->ap_en;
677 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
678 /* Use the DDR controller to auto initialize memory. */
679 d_init = popts->ECC_init_using_memctl;
680 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
681 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
683 /* Memory will be initialized via DMA, or not at all. */
687 #if defined(CONFIG_FSL_DDR3)
688 md_en = popts->mirrored_dimm;
690 qd_en = popts->quad_rank_present ? 1 : 0;
691 ddr->ddr_sdram_cfg_2 = (0
692 | ((frc_sr & 0x1) << 31)
693 | ((sr_ie & 0x1) << 30)
694 | ((dll_rst_dis & 0x1) << 29)
695 | ((dqs_cfg & 0x3) << 26)
696 | ((odt_cfg & 0x3) << 21)
697 | ((num_pr & 0xf) << 12)
700 | ((obc_cfg & 0x1) << 6)
701 | ((ap_en & 0x1) << 5)
702 | ((d_init & 0x1) << 4)
703 #ifdef CONFIG_FSL_DDR3
704 | ((rcw_en & 0x1) << 2)
706 | ((md_en & 0x1) << 0)
708 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
711 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
712 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
713 const memctl_options_t *popts,
714 const unsigned int unq_mrs_en)
716 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
717 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
719 #if defined(CONFIG_FSL_DDR3)
721 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
722 unsigned int srt = 0; /* self-refresh temerature, normal range */
723 unsigned int asr = 0; /* auto self-refresh disable */
724 unsigned int cwl = compute_cas_write_latency() - 5;
725 unsigned int pasr = 0; /* partial array self refresh disable */
727 if (popts->rtt_override)
728 rtt_wr = popts->rtt_wr_override_value;
730 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
732 | ((rtt_wr & 0x3) << 9)
736 | ((pasr & 0x7) << 0));
738 ddr->ddr_sdram_mode_2 = (0
739 | ((esdmode2 & 0xFFFF) << 16)
740 | ((esdmode3 & 0xFFFF) << 0)
742 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
744 #ifdef CONFIG_FSL_DDR3
745 if (unq_mrs_en) { /* unique mode registers are supported */
746 for (i = 1; i < 4; i++) {
747 if (popts->rtt_override)
748 rtt_wr = popts->rtt_wr_override_value;
750 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
752 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
753 esdmode2 |= (rtt_wr & 0x3) << 9;
756 ddr->ddr_sdram_mode_4 = (0
757 | ((esdmode2 & 0xFFFF) << 16)
758 | ((esdmode3 & 0xFFFF) << 0)
762 ddr->ddr_sdram_mode_6 = (0
763 | ((esdmode2 & 0xFFFF) << 16)
764 | ((esdmode3 & 0xFFFF) << 0)
768 ddr->ddr_sdram_mode_8 = (0
769 | ((esdmode2 & 0xFFFF) << 16)
770 | ((esdmode3 & 0xFFFF) << 0)
775 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
776 ddr->ddr_sdram_mode_4);
777 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
778 ddr->ddr_sdram_mode_6);
779 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
780 ddr->ddr_sdram_mode_8);
785 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
786 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
787 const memctl_options_t *popts,
788 const common_timing_params_t *common_dimm)
790 unsigned int refint; /* Refresh interval */
791 unsigned int bstopre; /* Precharge interval */
793 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
795 bstopre = popts->bstopre;
797 /* refint field used 0x3FFF in earlier controllers */
798 ddr->ddr_sdram_interval = (0
799 | ((refint & 0xFFFF) << 16)
800 | ((bstopre & 0x3FFF) << 0)
802 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
805 #if defined(CONFIG_FSL_DDR3)
806 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
807 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
808 const memctl_options_t *popts,
809 const common_timing_params_t *common_dimm,
810 unsigned int cas_latency,
811 unsigned int additive_latency,
812 const unsigned int unq_mrs_en)
814 unsigned short esdmode; /* Extended SDRAM mode */
815 unsigned short sdmode; /* SDRAM mode */
817 /* Mode Register - MR1 */
818 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
819 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
821 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
822 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
823 unsigned int dic = 0; /* Output driver impedance, 40ohm */
824 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
825 1=Disable (Test/Debug) */
827 /* Mode Register - MR0 */
828 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
829 unsigned int wr; /* Write Recovery */
830 unsigned int dll_rst; /* DLL Reset */
831 unsigned int mode; /* Normal=0 or Test=1 */
832 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
833 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
835 unsigned int bl; /* BL: Burst Length */
837 unsigned int wr_mclk;
839 * DDR_SDRAM_MODE doesn't support 9,11,13,15
840 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
843 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
845 const unsigned int mclk_ps = get_memory_clk_period_ps();
848 if (popts->rtt_override)
849 rtt = popts->rtt_override_value;
851 rtt = popts->cs_local_opts[0].odt_rtt_norm;
853 if (additive_latency == (cas_latency - 1))
855 if (additive_latency == (cas_latency - 2))
858 if (popts->quad_rank_present)
859 dic = 1; /* output driver impedance 240/7 ohm */
862 * The esdmode value will also be used for writing
863 * MR1 during write leveling for DDR3, although the
864 * bits specifically related to the write leveling
865 * scheme will be handled automatically by the DDR
866 * controller. so we set the wrlvl_en = 0 here.
869 | ((qoff & 0x1) << 12)
870 | ((tdqs_en & 0x1) << 11)
871 | ((rtt & 0x4) << 7) /* rtt field is split */
872 | ((wrlvl_en & 0x1) << 7)
873 | ((rtt & 0x2) << 5) /* rtt field is split */
874 | ((dic & 0x2) << 4) /* DIC field is split */
876 | ((rtt & 0x1) << 2) /* rtt field is split */
877 | ((dic & 0x1) << 1) /* DIC field is split */
878 | ((dll_en & 0x1) << 0)
882 * DLL control for precharge PD
883 * 0=slow exit DLL off (tXPDLL)
884 * 1=fast exit DLL on (tXP)
888 wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
889 wr = wr_table[wr_mclk - 5];
891 dll_rst = 0; /* dll no reset */
892 mode = 0; /* normal mode */
894 /* look up table to get the cas latency bits */
895 if (cas_latency >= 5 && cas_latency <= 11) {
896 unsigned char cas_latency_table[7] = {
905 caslat = cas_latency_table[cas_latency - 5];
907 bt = 0; /* Nibble sequential */
909 switch (popts->burst_length) {
920 printf("Error: invalid burst length of %u specified. "
921 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
922 popts->burst_length);
928 | ((dll_on & 0x1) << 12)
930 | ((dll_rst & 0x1) << 8)
931 | ((mode & 0x1) << 7)
932 | (((caslat >> 1) & 0x7) << 4)
937 ddr->ddr_sdram_mode = (0
938 | ((esdmode & 0xFFFF) << 16)
939 | ((sdmode & 0xFFFF) << 0)
942 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
944 if (unq_mrs_en) { /* unique mode registers are supported */
945 for (i = 1; i < 4; i++) {
946 if (popts->rtt_override)
947 rtt = popts->rtt_override_value;
949 rtt = popts->cs_local_opts[i].odt_rtt_norm;
951 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
953 | ((rtt & 0x4) << 7) /* rtt field is split */
954 | ((rtt & 0x2) << 5) /* rtt field is split */
955 | ((rtt & 0x1) << 2) /* rtt field is split */
959 ddr->ddr_sdram_mode_3 = (0
960 | ((esdmode & 0xFFFF) << 16)
961 | ((sdmode & 0xFFFF) << 0)
965 ddr->ddr_sdram_mode_5 = (0
966 | ((esdmode & 0xFFFF) << 16)
967 | ((sdmode & 0xFFFF) << 0)
971 ddr->ddr_sdram_mode_7 = (0
972 | ((esdmode & 0xFFFF) << 16)
973 | ((sdmode & 0xFFFF) << 0)
978 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
979 ddr->ddr_sdram_mode_3);
980 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
981 ddr->ddr_sdram_mode_5);
982 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
983 ddr->ddr_sdram_mode_5);
987 #else /* !CONFIG_FSL_DDR3 */
989 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
990 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
991 const memctl_options_t *popts,
992 const common_timing_params_t *common_dimm,
993 unsigned int cas_latency,
994 unsigned int additive_latency,
995 const unsigned int unq_mrs_en)
997 unsigned short esdmode; /* Extended SDRAM mode */
998 unsigned short sdmode; /* SDRAM mode */
1001 * FIXME: This ought to be pre-calculated in a
1002 * technology-specific routine,
1003 * e.g. compute_DDR2_mode_register(), and then the
1004 * sdmode and esdmode passed in as part of common_dimm.
1007 /* Extended Mode Register */
1008 unsigned int mrs = 0; /* Mode Register Set */
1009 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1010 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1011 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1012 unsigned int ocd = 0; /* 0x0=OCD not supported,
1013 0x7=OCD default state */
1015 unsigned int al; /* Posted CAS# additive latency (AL) */
1016 unsigned int ods = 0; /* Output Drive Strength:
1017 0 = Full strength (18ohm)
1018 1 = Reduced strength (4ohm) */
1019 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1020 1=Disable (Test/Debug) */
1022 /* Mode Register (MR) */
1023 unsigned int mr; /* Mode Register Definition */
1024 unsigned int pd; /* Power-Down Mode */
1025 unsigned int wr; /* Write Recovery */
1026 unsigned int dll_res; /* DLL Reset */
1027 unsigned int mode; /* Normal=0 or Test=1 */
1028 unsigned int caslat = 0;/* CAS# latency */
1029 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1031 unsigned int bl; /* BL: Burst Length */
1033 #if defined(CONFIG_FSL_DDR2)
1034 const unsigned int mclk_ps = get_memory_clk_period_ps();
1036 dqs_en = !popts->DQS_config;
1037 rtt = fsl_ddr_get_rtt();
1039 al = additive_latency;
1042 | ((mrs & 0x3) << 14)
1043 | ((outputs & 0x1) << 12)
1044 | ((rdqs_en & 0x1) << 11)
1045 | ((dqs_en & 0x1) << 10)
1046 | ((ocd & 0x7) << 7)
1047 | ((rtt & 0x2) << 5) /* rtt field is split */
1049 | ((rtt & 0x1) << 2) /* rtt field is split */
1050 | ((ods & 0x1) << 1)
1051 | ((dll_en & 0x1) << 0)
1054 mr = 0; /* FIXME: CHECKME */
1057 * 0 = Fast Exit (Normal)
1058 * 1 = Slow Exit (Low Power)
1062 #if defined(CONFIG_FSL_DDR1)
1063 wr = 0; /* Historical */
1064 #elif defined(CONFIG_FSL_DDR2)
1065 wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
1070 #if defined(CONFIG_FSL_DDR1)
1071 if (1 <= cas_latency && cas_latency <= 4) {
1072 unsigned char mode_caslat_table[4] = {
1073 0x5, /* 1.5 clocks */
1074 0x2, /* 2.0 clocks */
1075 0x6, /* 2.5 clocks */
1076 0x3 /* 3.0 clocks */
1078 caslat = mode_caslat_table[cas_latency - 1];
1080 printf("Warning: unknown cas_latency %d\n", cas_latency);
1082 #elif defined(CONFIG_FSL_DDR2)
1083 caslat = cas_latency;
1087 switch (popts->burst_length) {
1095 printf("Error: invalid burst length of %u specified. "
1096 " Defaulting to 4 beats.\n",
1097 popts->burst_length);
1103 | ((mr & 0x3) << 14)
1104 | ((pd & 0x1) << 12)
1106 | ((dll_res & 0x1) << 8)
1107 | ((mode & 0x1) << 7)
1108 | ((caslat & 0x7) << 4)
1113 ddr->ddr_sdram_mode = (0
1114 | ((esdmode & 0xFFFF) << 16)
1115 | ((sdmode & 0xFFFF) << 0)
1117 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1121 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1122 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1124 unsigned int init_value; /* Initialization value */
1126 init_value = 0xDEADBEEF;
1127 ddr->ddr_data_init = init_value;
1131 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1132 * The old controller on the 8540/60 doesn't have this register.
1133 * Hope it's OK to set it (to 0) anyway.
1135 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1136 const memctl_options_t *popts)
1138 unsigned int clk_adjust; /* Clock adjust */
1140 clk_adjust = popts->clk_adjust;
1141 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1142 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1145 /* DDR Initialization Address (DDR_INIT_ADDR) */
1146 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1148 unsigned int init_addr = 0; /* Initialization address */
1150 ddr->ddr_init_addr = init_addr;
1153 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1154 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1156 unsigned int uia = 0; /* Use initialization address */
1157 unsigned int init_ext_addr = 0; /* Initialization address */
1159 ddr->ddr_init_ext_addr = (0
1160 | ((uia & 0x1) << 31)
1161 | (init_ext_addr & 0xF)
1165 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1166 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1167 const memctl_options_t *popts)
1169 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1170 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1171 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1172 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1173 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1175 #if defined(CONFIG_FSL_DDR3)
1176 if (popts->burst_length == DDR_BL8) {
1177 /* We set BL/2 for fixed BL8 */
1178 rrt = 0; /* BL/2 clocks */
1179 wwt = 0; /* BL/2 clocks */
1181 /* We need to set BL/2 + 2 to BC4 and OTF */
1182 rrt = 2; /* BL/2 + 2 clocks */
1183 wwt = 2; /* BL/2 + 2 clocks */
1185 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1187 ddr->timing_cfg_4 = (0
1188 | ((rwt & 0xf) << 28)
1189 | ((wrt & 0xf) << 24)
1190 | ((rrt & 0xf) << 20)
1191 | ((wwt & 0xf) << 16)
1194 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1197 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1198 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1200 unsigned int rodt_on = 0; /* Read to ODT on */
1201 unsigned int rodt_off = 0; /* Read to ODT off */
1202 unsigned int wodt_on = 0; /* Write to ODT on */
1203 unsigned int wodt_off = 0; /* Write to ODT off */
1205 #if defined(CONFIG_FSL_DDR3)
1206 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1207 rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1208 rodt_off = 4; /* 4 clocks */
1209 wodt_on = 1; /* 1 clocks */
1210 wodt_off = 4; /* 4 clocks */
1213 ddr->timing_cfg_5 = (0
1214 | ((rodt_on & 0x1f) << 24)
1215 | ((rodt_off & 0x7) << 20)
1216 | ((wodt_on & 0x1f) << 12)
1217 | ((wodt_off & 0x7) << 8)
1219 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1222 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1223 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1225 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1226 /* Normal Operation Full Calibration Time (tZQoper) */
1227 unsigned int zqoper = 0;
1228 /* Normal Operation Short Calibration Time (tZQCS) */
1229 unsigned int zqcs = 0;
1232 zqinit = 9; /* 512 clocks */
1233 zqoper = 8; /* 256 clocks */
1234 zqcs = 6; /* 64 clocks */
1237 ddr->ddr_zq_cntl = (0
1238 | ((zq_en & 0x1) << 31)
1239 | ((zqinit & 0xF) << 24)
1240 | ((zqoper & 0xF) << 16)
1241 | ((zqcs & 0xF) << 8)
1243 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1246 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1247 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1248 const memctl_options_t *popts)
1251 * First DQS pulse rising edge after margining mode
1252 * is programmed (tWL_MRD)
1254 unsigned int wrlvl_mrd = 0;
1255 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1256 unsigned int wrlvl_odten = 0;
1257 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1258 unsigned int wrlvl_dqsen = 0;
1259 /* WRLVL_SMPL: Write leveling sample time */
1260 unsigned int wrlvl_smpl = 0;
1261 /* WRLVL_WLR: Write leveling repeition time */
1262 unsigned int wrlvl_wlr = 0;
1263 /* WRLVL_START: Write leveling start time */
1264 unsigned int wrlvl_start = 0;
1266 /* suggest enable write leveling for DDR3 due to fly-by topology */
1268 /* tWL_MRD min = 40 nCK, we set it 64 */
1272 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1275 * Write leveling sample time at least need 6 clocks
1276 * higher than tWLO to allow enough time for progagation
1277 * delay and sampling the prime data bits.
1281 * Write leveling repetition time
1282 * at least tWLO + 6 clocks clocks
1287 * Write leveling start time
1288 * The value use for the DQS_ADJUST for the first sample
1289 * when write leveling is enabled. It probably needs to be
1290 * overriden per platform.
1294 * Override the write leveling sample and start time
1295 * according to specific board
1297 if (popts->wrlvl_override) {
1298 wrlvl_smpl = popts->wrlvl_sample;
1299 wrlvl_start = popts->wrlvl_start;
1303 ddr->ddr_wrlvl_cntl = (0
1304 | ((wrlvl_en & 0x1) << 31)
1305 | ((wrlvl_mrd & 0x7) << 24)
1306 | ((wrlvl_odten & 0x7) << 20)
1307 | ((wrlvl_dqsen & 0x7) << 16)
1308 | ((wrlvl_smpl & 0xf) << 12)
1309 | ((wrlvl_wlr & 0x7) << 8)
1310 | ((wrlvl_start & 0x1F) << 0)
1312 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1315 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1316 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1318 /* Self Refresh Idle Threshold */
1319 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1322 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1324 if (popts->addr_hash) {
1325 ddr->ddr_eor = 0x40000000; /* address hash enable */
1326 puts("Address hashing enabled.\n");
1330 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1332 ddr->ddr_cdr1 = popts->ddr_cdr1;
1333 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1337 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1339 unsigned int res = 0;
1342 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1343 * not set at the same time.
1345 if (ddr->ddr_sdram_cfg & 0x10000000
1346 && ddr->ddr_sdram_cfg & 0x00008000) {
1347 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1348 " should not be set at the same time.\n");
1356 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1357 fsl_ddr_cfg_regs_t *ddr,
1358 const common_timing_params_t *common_dimm,
1359 const dimm_params_t *dimm_params,
1360 unsigned int dbw_cap_adj,
1361 unsigned int size_only)
1364 unsigned int cas_latency;
1365 unsigned int additive_latency;
1368 unsigned int wrlvl_en;
1369 unsigned int ip_rev = 0;
1370 unsigned int unq_mrs_en = 0;
1373 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1375 if (common_dimm == NULL) {
1376 printf("Error: subset DIMM params struct null pointer\n");
1381 * Process overrides first.
1383 * FIXME: somehow add dereated caslat to this
1385 cas_latency = (popts->cas_latency_override)
1386 ? popts->cas_latency_override_value
1387 : common_dimm->lowest_common_SPD_caslat;
1389 additive_latency = (popts->additive_latency_override)
1390 ? popts->additive_latency_override_value
1391 : common_dimm->additive_latency;
1393 sr_it = (popts->auto_self_refresh_en)
1396 /* ZQ calibration */
1397 zq_en = (popts->zq_en) ? 1 : 0;
1398 /* write leveling */
1399 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1401 /* Chip Select Memory Bounds (CSn_BNDS) */
1402 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1403 unsigned long long ea = 0, sa = 0;
1404 unsigned int cs_per_dimm
1405 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1406 unsigned int dimm_number
1408 unsigned long long rank_density
1409 = dimm_params[dimm_number].rank_density;
1411 if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) ||
1412 ((i == 2) && (popts->ba_intlv_ctl & 0x04)) ||
1413 ((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) {
1415 * Don't set up boundaries for unused CS
1416 * cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1417 * cs2 for cs0_cs1_cs2_cs3
1418 * cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1419 * But we need to set the ODT_RD_CFG and
1420 * ODT_WR_CFG for CS1_CONFIG here.
1422 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1425 if (dimm_params[dimm_number].n_ranks == 0) {
1426 debug("Skipping setup of CS%u "
1427 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1430 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
1432 * This works superbank 2CS
1433 * There are 2 or more memory controllers configured
1434 * identically, memory is interleaved between them,
1435 * and each controller uses rank interleaving within
1436 * itself. Therefore the starting and ending address
1437 * on each controller is twice the amount present on
1438 * each controller. If any CS is not included in the
1439 * interleaving, the memory on that CS is not accssible
1440 * and the total memory size is reduced. The CS is also
1443 unsigned long long ctlr_density = 0;
1444 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1445 case FSL_DDR_CS0_CS1:
1446 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1447 ctlr_density = dimm_params[0].rank_density * 2;
1451 case FSL_DDR_CS2_CS3:
1452 ctlr_density = dimm_params[0].rank_density;
1456 case FSL_DDR_CS0_CS1_CS2_CS3:
1458 * The four CS interleaving should have been verified by
1459 * populate_memctl_options()
1461 ctlr_density = dimm_params[0].rank_density * 4;
1466 ea = (CONFIG_NUM_DDR_CONTROLLERS *
1467 (ctlr_density >> dbw_cap_adj)) - 1;
1469 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
1471 * If memory interleaving between controllers is NOT
1472 * enabled, the starting address for each memory
1473 * controller is distinct. However, because rank
1474 * interleaving is enabled, the starting and ending
1475 * addresses of the total memory on that memory
1476 * controller needs to be programmed into its
1477 * respective CS0_BNDS.
1479 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1480 case FSL_DDR_CS0_CS1_CS2_CS3:
1481 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
1484 sa = common_dimm->base_address;
1485 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
1487 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1488 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
1489 * and CS2_CNDS need to be set.
1491 if ((i == 2) && (dimm_number == 0)) {
1492 sa = dimm_params[dimm_number].base_address +
1493 2 * (rank_density >> dbw_cap_adj);
1494 ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1;
1496 sa = dimm_params[dimm_number].base_address;
1497 ea = sa + (2 * (rank_density >>
1501 case FSL_DDR_CS0_CS1:
1502 /* CS0+CS1 interleaving, CS0_CNDS needs
1505 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1506 sa = dimm_params[dimm_number].base_address;
1507 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1508 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1509 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1515 ea += (rank_density >> dbw_cap_adj);
1517 case FSL_DDR_CS2_CS3:
1518 /* CS2+CS3 interleaving*/
1519 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1520 sa = dimm_params[dimm_number].base_address;
1521 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1522 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1523 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1529 ea += (rank_density >> dbw_cap_adj);
1531 default: /* No bank(chip-select) interleaving */
1535 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1537 * Only the rank on CS0 of each memory controller may
1538 * be used if memory controller interleaving is used
1539 * without rank interleaving within each memory
1540 * controller. However, the ending address programmed
1541 * into each CS0 must be the sum of the amount of
1542 * memory in the two CS0 ranks.
1545 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1549 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1551 * No rank interleaving and no memory controller
1554 sa = dimm_params[dimm_number].base_address;
1555 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1556 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1557 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1558 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1568 ddr->cs[i].bnds = (0
1569 | ((sa & 0xFFF) << 16) /* starting address MSB */
1570 | ((ea & 0xFFF) << 0) /* ending address MSB */
1573 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1575 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1576 set_csn_config_2(i, ddr);
1578 printf("CS%d is disabled.\n", i);
1582 * In the case we only need to compute the ddr sdram size, we only need
1583 * to set csn registers, so return from here.
1588 set_ddr_eor(ddr, popts);
1590 #if !defined(CONFIG_FSL_DDR1)
1591 set_timing_cfg_0(ddr, popts);
1594 set_timing_cfg_3(ddr, common_dimm, cas_latency);
1595 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1596 set_timing_cfg_2(ddr, popts, common_dimm,
1597 cas_latency, additive_latency);
1599 set_ddr_cdr1(ddr, popts);
1600 set_ddr_sdram_cfg(ddr, popts, common_dimm);
1601 ip_rev = fsl_ddr_get_version();
1602 if (ip_rev > 0x40400)
1605 set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1606 set_ddr_sdram_mode(ddr, popts, common_dimm,
1607 cas_latency, additive_latency, unq_mrs_en);
1608 set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
1609 set_ddr_sdram_interval(ddr, popts, common_dimm);
1610 set_ddr_data_init(ddr);
1611 set_ddr_sdram_clk_cntl(ddr, popts);
1612 set_ddr_init_addr(ddr);
1613 set_ddr_init_ext_addr(ddr);
1614 set_timing_cfg_4(ddr, popts);
1615 set_timing_cfg_5(ddr, cas_latency);
1617 set_ddr_zq_cntl(ddr, zq_en);
1618 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1620 set_ddr_sr_cntr(ddr, sr_it);
1622 set_ddr_sdram_rcw(ddr, popts, common_dimm);
1624 return check_fsl_memctl_config_regs(ddr);