2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
11 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
12 * Based on code from spd_sdram.c
13 * Author: James Yang [at freescale.com]
17 #include <asm/fsl_ddr_sdram.h>
22 #define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR
23 #elif defined(CONFIG_MPC85xx)
24 #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
25 #elif defined(CONFIG_MPC86xx)
26 #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
28 #error "Undefined _DDR_ADDR"
31 u32 fsl_ddr_get_version(void)
34 u32 ver_major_minor_errata;
36 ddr = (void *)_DDR_ADDR;
37 ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
38 ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
40 return ver_major_minor_errata;
43 unsigned int picos_to_mclk(unsigned int picos);
46 * Determine Rtt value.
48 * This should likely be either board or controller specific.
50 * Rtt(nominal) - DDR2:
55 * Rtt(nominal) - DDR3:
63 * FIXME: Apparently 8641 needs a value of 2
64 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
66 * FIXME: There was some effort down this line earlier:
69 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
70 * if (popts->dimmslot[i].num_valid_cs
71 * && (popts->cs_local_opts[2*i].odt_rd_cfg
72 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
78 static inline int fsl_ddr_get_rtt(void)
82 #if defined(CONFIG_FSL_DDR1)
84 #elif defined(CONFIG_FSL_DDR2)
94 * compute the CAS write latency according to DDR3 spec
95 * CWL = 5 if tCK >= 2.5ns
96 * 6 if 2.5ns > tCK >= 1.875ns
97 * 7 if 1.875ns > tCK >= 1.5ns
98 * 8 if 1.5ns > tCK >= 1.25ns
99 * 9 if 1.25ns > tCK >= 1.07ns
100 * 10 if 1.07ns > tCK >= 0.935ns
101 * 11 if 0.935ns > tCK >= 0.833ns
102 * 12 if 0.833ns > tCK >= 0.75ns
104 static inline unsigned int compute_cas_write_latency(void)
107 const unsigned int mclk_ps = get_memory_clk_period_ps();
111 else if (mclk_ps >= 1875)
113 else if (mclk_ps >= 1500)
115 else if (mclk_ps >= 1250)
117 else if (mclk_ps >= 1070)
119 else if (mclk_ps >= 935)
121 else if (mclk_ps >= 833)
123 else if (mclk_ps >= 750)
127 printf("Warning: CWL is out of range\n");
132 /* Chip Select Configuration (CSn_CONFIG) */
133 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
134 const memctl_options_t *popts,
135 const dimm_params_t *dimm_params)
137 unsigned int cs_n_en = 0; /* Chip Select enable */
138 unsigned int intlv_en = 0; /* Memory controller interleave enable */
139 unsigned int intlv_ctl = 0; /* Interleaving control */
140 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
141 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
142 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
143 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
144 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
145 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
148 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
151 if (dimm_params[dimm_number].n_ranks > 0) {
153 /* These fields only available in CS0_CONFIG */
154 intlv_en = popts->memctl_interleaving;
155 intlv_ctl = popts->memctl_interleaving_mode;
159 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
160 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
164 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
165 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
169 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
170 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
171 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
178 unsigned int n_banks_per_sdram_device;
180 ap_n_en = popts->cs_local_opts[i].auto_precharge;
181 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
182 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
183 n_banks_per_sdram_device
184 = dimm_params[dimm_number].n_banks_per_sdram_device;
185 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
186 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
187 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
189 ddr->cs[i].config = (0
190 | ((cs_n_en & 0x1) << 31)
191 | ((intlv_en & 0x3) << 29)
192 | ((intlv_ctl & 0xf) << 24)
193 | ((ap_n_en & 0x1) << 23)
195 /* XXX: some implementation only have 1 bit starting at left */
196 | ((odt_rd_cfg & 0x7) << 20)
198 /* XXX: Some implementation only have 1 bit starting at left */
199 | ((odt_wr_cfg & 0x7) << 16)
201 | ((ba_bits_cs_n & 0x3) << 14)
202 | ((row_bits_cs_n & 0x7) << 8)
203 | ((col_bits_cs_n & 0x7) << 0)
205 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
208 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
210 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
212 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
214 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
215 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
218 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
220 #if !defined(CONFIG_FSL_DDR1)
222 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
224 * Avoid writing for DDR I. The new PQ38 DDR controller
225 * dreams up non-zero default values to be backwards compatible.
227 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
228 const memctl_options_t *popts)
230 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
231 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
232 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
233 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
234 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
236 /* Active powerdown exit timing (tXARD and tXARDS). */
237 unsigned char act_pd_exit_mclk;
238 /* Precharge powerdown exit timing (tXP). */
239 unsigned char pre_pd_exit_mclk;
240 /* ODT powerdown exit timing (tAXPD). */
241 unsigned char taxpd_mclk;
242 /* Mode register set cycle time (tMRD). */
243 unsigned char tmrd_mclk;
245 #ifdef CONFIG_FSL_DDR3
247 * (tXARD and tXARDS). Empirical?
248 * The DDR3 spec has not tXARD,
249 * we use the tXP instead of it.
250 * tXP=max(3nCK, 7.5ns) for DDR3.
251 * spec has not the tAXPD, we use
252 * tAXPD=1, need design to confirm.
254 int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
255 unsigned int data_rate = get_ddr_freq(0);
257 /* set the turnaround time */
259 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
262 if (popts->dynamic_power == 0) { /* powerdown is not used */
263 act_pd_exit_mclk = 1;
264 pre_pd_exit_mclk = 1;
267 /* act_pd_exit_mclk = tXARD, see above */
268 act_pd_exit_mclk = picos_to_mclk(tXP);
269 /* Mode register MR0[A12] is '1' - fast exit */
270 pre_pd_exit_mclk = act_pd_exit_mclk;
273 #else /* CONFIG_FSL_DDR2 */
275 * (tXARD and tXARDS). Empirical?
280 act_pd_exit_mclk = 2;
281 pre_pd_exit_mclk = 2;
286 if (popts->trwt_override)
287 trwt_mclk = popts->trwt;
289 ddr->timing_cfg_0 = (0
290 | ((trwt_mclk & 0x3) << 30) /* RWT */
291 | ((twrt_mclk & 0x3) << 28) /* WRT */
292 | ((trrt_mclk & 0x3) << 26) /* RRT */
293 | ((twwt_mclk & 0x3) << 24) /* WWT */
294 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
295 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
296 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
297 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
299 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
301 #endif /* defined(CONFIG_FSL_DDR2) */
303 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
304 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
305 const common_timing_params_t *common_dimm,
306 unsigned int cas_latency)
308 /* Extended Activate to precharge interval (tRAS) */
309 unsigned int ext_acttopre = 0;
310 unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
311 unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
312 unsigned int cntl_adj = 0; /* Control Adjust */
314 /* If the tRAS > 19 MCLK, we use the ext mode */
315 if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
318 ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
320 /* If the CAS latency more than 8, use the ext mode */
324 ddr->timing_cfg_3 = (0
325 | ((ext_acttopre & 0x1) << 24)
326 | ((ext_refrec & 0xF) << 16)
327 | ((ext_caslat & 0x1) << 12)
328 | ((cntl_adj & 0x7) << 0)
330 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
333 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
334 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
335 const memctl_options_t *popts,
336 const common_timing_params_t *common_dimm,
337 unsigned int cas_latency)
339 /* Precharge-to-activate interval (tRP) */
340 unsigned char pretoact_mclk;
341 /* Activate to precharge interval (tRAS) */
342 unsigned char acttopre_mclk;
343 /* Activate to read/write interval (tRCD) */
344 unsigned char acttorw_mclk;
346 unsigned char caslat_ctrl;
347 /* Refresh recovery time (tRFC) ; trfc_low */
348 unsigned char refrec_ctrl;
349 /* Last data to precharge minimum interval (tWR) */
350 unsigned char wrrec_mclk;
351 /* Activate-to-activate interval (tRRD) */
352 unsigned char acttoact_mclk;
353 /* Last write data pair to read command issue interval (tWTR) */
354 unsigned char wrtord_mclk;
355 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
356 static const u8 wrrec_table[] = {
357 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
359 pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
360 acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
361 acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
364 * Translate CAS Latency to a DDR controller field value:
366 * CAS Lat DDR I DDR II Ctrl
367 * Clocks SPD Bit SPD Bit Value
368 * ------- ------- ------- -----
379 #if defined(CONFIG_FSL_DDR1)
380 caslat_ctrl = (cas_latency + 1) & 0x07;
381 #elif defined(CONFIG_FSL_DDR2)
382 caslat_ctrl = 2 * cas_latency - 1;
385 * if the CAS latency more than 8 cycle,
386 * we need set extend bit for it at
387 * TIMING_CFG_3[EXT_CASLAT]
391 caslat_ctrl = 2 * cas_latency - 1;
394 refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
395 wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
397 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
398 if (popts->OTF_burst_chop_en)
401 acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
403 * JEDEC has min requirement for tRRD
405 #if defined(CONFIG_FSL_DDR3)
406 if (acttoact_mclk < 4)
409 wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
411 * JEDEC has some min requirements for tWTR
413 #if defined(CONFIG_FSL_DDR2)
416 #elif defined(CONFIG_FSL_DDR3)
420 if (popts->OTF_burst_chop_en)
423 ddr->timing_cfg_1 = (0
424 | ((pretoact_mclk & 0x0F) << 28)
425 | ((acttopre_mclk & 0x0F) << 24)
426 | ((acttorw_mclk & 0xF) << 20)
427 | ((caslat_ctrl & 0xF) << 16)
428 | ((refrec_ctrl & 0xF) << 12)
429 | ((wrrec_mclk & 0x0F) << 8)
430 | ((acttoact_mclk & 0x07) << 4)
431 | ((wrtord_mclk & 0x07) << 0)
433 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
436 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
437 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
438 const memctl_options_t *popts,
439 const common_timing_params_t *common_dimm,
440 unsigned int cas_latency,
441 unsigned int additive_latency)
443 /* Additive latency */
444 unsigned char add_lat_mclk;
445 /* CAS-to-preamble override */
448 unsigned char wr_lat;
449 /* Read to precharge (tRTP) */
450 unsigned char rd_to_pre;
451 /* Write command to write data strobe timing adjustment */
452 unsigned char wr_data_delay;
453 /* Minimum CKE pulse width (tCKE) */
454 unsigned char cke_pls;
455 /* Window for four activates (tFAW) */
456 unsigned short four_act;
458 /* FIXME add check that this must be less than acttorw_mclk */
459 add_lat_mclk = additive_latency;
460 cpo = popts->cpo_override;
462 #if defined(CONFIG_FSL_DDR1)
464 * This is a lie. It should really be 1, but if it is
465 * set to 1, bits overlap into the old controller's
466 * otherwise unused ACSM field. If we leave it 0, then
467 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
470 #elif defined(CONFIG_FSL_DDR2)
471 wr_lat = cas_latency - 1;
473 wr_lat = compute_cas_write_latency();
476 rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
478 * JEDEC has some min requirements for tRTP
480 #if defined(CONFIG_FSL_DDR2)
483 #elif defined(CONFIG_FSL_DDR3)
487 if (additive_latency)
488 rd_to_pre += additive_latency;
489 if (popts->OTF_burst_chop_en)
490 rd_to_pre += 2; /* according to UM */
492 wr_data_delay = popts->write_data_delay;
493 cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
494 four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
496 ddr->timing_cfg_2 = (0
497 | ((add_lat_mclk & 0xf) << 28)
498 | ((cpo & 0x1f) << 23)
499 | ((wr_lat & 0xf) << 19)
500 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
501 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
502 | ((cke_pls & 0x7) << 6)
503 | ((four_act & 0x3f) << 0)
505 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
508 /* DDR SDRAM Register Control Word */
509 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
510 const memctl_options_t *popts,
511 const common_timing_params_t *common_dimm)
513 if (common_dimm->all_DIMMs_registered
514 && !common_dimm->all_DIMMs_unbuffered) {
515 if (popts->rcw_override) {
516 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
517 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
519 ddr->ddr_sdram_rcw_1 =
520 common_dimm->rcw[0] << 28 | \
521 common_dimm->rcw[1] << 24 | \
522 common_dimm->rcw[2] << 20 | \
523 common_dimm->rcw[3] << 16 | \
524 common_dimm->rcw[4] << 12 | \
525 common_dimm->rcw[5] << 8 | \
526 common_dimm->rcw[6] << 4 | \
528 ddr->ddr_sdram_rcw_2 =
529 common_dimm->rcw[8] << 28 | \
530 common_dimm->rcw[9] << 24 | \
531 common_dimm->rcw[10] << 20 | \
532 common_dimm->rcw[11] << 16 | \
533 common_dimm->rcw[12] << 12 | \
534 common_dimm->rcw[13] << 8 | \
535 common_dimm->rcw[14] << 4 | \
536 common_dimm->rcw[15];
538 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
539 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
543 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
544 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
545 const memctl_options_t *popts,
546 const common_timing_params_t *common_dimm)
548 unsigned int mem_en; /* DDR SDRAM interface logic enable */
549 unsigned int sren; /* Self refresh enable (during sleep) */
550 unsigned int ecc_en; /* ECC enable. */
551 unsigned int rd_en; /* Registered DIMM enable */
552 unsigned int sdram_type; /* Type of SDRAM */
553 unsigned int dyn_pwr; /* Dynamic power management mode */
554 unsigned int dbw; /* DRAM dta bus width */
555 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
556 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
557 unsigned int threeT_en; /* Enable 3T timing */
558 unsigned int twoT_en; /* Enable 2T timing */
559 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
560 unsigned int x32_en = 0; /* x32 enable */
561 unsigned int pchb8 = 0; /* precharge bit 8 enable */
562 unsigned int hse; /* Global half strength override */
563 unsigned int mem_halt = 0; /* memory controller halt */
564 unsigned int bi = 0; /* Bypass initialization */
567 sren = popts->self_refresh_in_sleep;
568 if (common_dimm->all_DIMMs_ECC_capable) {
569 /* Allow setting of ECC only if all DIMMs are ECC. */
570 ecc_en = popts->ECC_mode;
575 if (common_dimm->all_DIMMs_registered
576 && !common_dimm->all_DIMMs_unbuffered) {
581 twoT_en = popts->twoT_en;
584 sdram_type = CONFIG_FSL_SDRAM_TYPE;
586 dyn_pwr = popts->dynamic_power;
587 dbw = popts->data_bus_width;
588 /* 8-beat burst enable DDR-III case
589 * we must clear it when use the on-the-fly mode,
590 * must set it when use the 32-bits bus mode.
592 if (sdram_type == SDRAM_TYPE_DDR3) {
593 if (popts->burst_length == DDR_BL8)
595 if (popts->burst_length == DDR_OTF)
601 threeT_en = popts->threeT_en;
602 ba_intlv_ctl = popts->ba_intlv_ctl;
603 hse = popts->half_strength_driver_enable;
605 ddr->ddr_sdram_cfg = (0
606 | ((mem_en & 0x1) << 31)
607 | ((sren & 0x1) << 30)
608 | ((ecc_en & 0x1) << 29)
609 | ((rd_en & 0x1) << 28)
610 | ((sdram_type & 0x7) << 24)
611 | ((dyn_pwr & 0x1) << 21)
612 | ((dbw & 0x3) << 19)
613 | ((eight_be & 0x1) << 18)
614 | ((ncap & 0x1) << 17)
615 | ((threeT_en & 0x1) << 16)
616 | ((twoT_en & 0x1) << 15)
617 | ((ba_intlv_ctl & 0x7F) << 8)
618 | ((x32_en & 0x1) << 5)
619 | ((pchb8 & 0x1) << 4)
621 | ((mem_halt & 0x1) << 1)
624 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
627 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
628 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
629 const memctl_options_t *popts,
630 const unsigned int unq_mrs_en)
632 unsigned int frc_sr = 0; /* Force self refresh */
633 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
634 unsigned int dll_rst_dis; /* DLL reset disable */
635 unsigned int dqs_cfg; /* DQS configuration */
636 unsigned int odt_cfg = 0; /* ODT configuration */
637 unsigned int num_pr; /* Number of posted refreshes */
638 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
639 unsigned int ap_en; /* Address Parity Enable */
640 unsigned int d_init; /* DRAM data initialization */
641 unsigned int rcw_en = 0; /* Register Control Word Enable */
642 unsigned int md_en = 0; /* Mirrored DIMM Enable */
643 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
646 dll_rst_dis = 1; /* Make this configurable */
647 dqs_cfg = popts->DQS_config;
648 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
649 if (popts->cs_local_opts[i].odt_rd_cfg
650 || popts->cs_local_opts[i].odt_wr_cfg) {
651 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
656 num_pr = 1; /* Make this configurable */
660 * {TIMING_CFG_1[PRETOACT]
661 * + [DDR_SDRAM_CFG_2[NUM_PR]
662 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
663 * << DDR_SDRAM_INTERVAL[REFINT]
665 #if defined(CONFIG_FSL_DDR3)
666 obc_cfg = popts->OTF_burst_chop_en;
671 if (popts->registered_dimm_en) {
673 ap_en = popts->ap_en;
679 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
680 /* Use the DDR controller to auto initialize memory. */
681 d_init = popts->ECC_init_using_memctl;
682 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
683 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
685 /* Memory will be initialized via DMA, or not at all. */
689 #if defined(CONFIG_FSL_DDR3)
690 md_en = popts->mirrored_dimm;
692 qd_en = popts->quad_rank_present ? 1 : 0;
693 ddr->ddr_sdram_cfg_2 = (0
694 | ((frc_sr & 0x1) << 31)
695 | ((sr_ie & 0x1) << 30)
696 | ((dll_rst_dis & 0x1) << 29)
697 | ((dqs_cfg & 0x3) << 26)
698 | ((odt_cfg & 0x3) << 21)
699 | ((num_pr & 0xf) << 12)
702 | ((obc_cfg & 0x1) << 6)
703 | ((ap_en & 0x1) << 5)
704 | ((d_init & 0x1) << 4)
705 #ifdef CONFIG_FSL_DDR3
706 | ((rcw_en & 0x1) << 2)
708 | ((md_en & 0x1) << 0)
710 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
713 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
714 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
715 const memctl_options_t *popts,
716 const unsigned int unq_mrs_en)
718 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
719 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
721 #if defined(CONFIG_FSL_DDR3)
723 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
724 unsigned int srt = 0; /* self-refresh temerature, normal range */
725 unsigned int asr = 0; /* auto self-refresh disable */
726 unsigned int cwl = compute_cas_write_latency() - 5;
727 unsigned int pasr = 0; /* partial array self refresh disable */
729 if (popts->rtt_override)
730 rtt_wr = popts->rtt_wr_override_value;
732 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
734 | ((rtt_wr & 0x3) << 9)
738 | ((pasr & 0x7) << 0));
740 ddr->ddr_sdram_mode_2 = (0
741 | ((esdmode2 & 0xFFFF) << 16)
742 | ((esdmode3 & 0xFFFF) << 0)
744 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
746 #ifdef CONFIG_FSL_DDR3
747 if (unq_mrs_en) { /* unique mode registers are supported */
748 for (i = 1; i < 4; i++) {
749 if (popts->rtt_override)
750 rtt_wr = popts->rtt_wr_override_value;
752 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
754 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
755 esdmode2 |= (rtt_wr & 0x3) << 9;
758 ddr->ddr_sdram_mode_4 = (0
759 | ((esdmode2 & 0xFFFF) << 16)
760 | ((esdmode3 & 0xFFFF) << 0)
764 ddr->ddr_sdram_mode_6 = (0
765 | ((esdmode2 & 0xFFFF) << 16)
766 | ((esdmode3 & 0xFFFF) << 0)
770 ddr->ddr_sdram_mode_8 = (0
771 | ((esdmode2 & 0xFFFF) << 16)
772 | ((esdmode3 & 0xFFFF) << 0)
777 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
778 ddr->ddr_sdram_mode_4);
779 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
780 ddr->ddr_sdram_mode_6);
781 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
782 ddr->ddr_sdram_mode_8);
787 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
788 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
789 const memctl_options_t *popts,
790 const common_timing_params_t *common_dimm)
792 unsigned int refint; /* Refresh interval */
793 unsigned int bstopre; /* Precharge interval */
795 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
797 bstopre = popts->bstopre;
799 /* refint field used 0x3FFF in earlier controllers */
800 ddr->ddr_sdram_interval = (0
801 | ((refint & 0xFFFF) << 16)
802 | ((bstopre & 0x3FFF) << 0)
804 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
807 #if defined(CONFIG_FSL_DDR3)
808 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
809 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
810 const memctl_options_t *popts,
811 const common_timing_params_t *common_dimm,
812 unsigned int cas_latency,
813 unsigned int additive_latency,
814 const unsigned int unq_mrs_en)
816 unsigned short esdmode; /* Extended SDRAM mode */
817 unsigned short sdmode; /* SDRAM mode */
819 /* Mode Register - MR1 */
820 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
821 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
823 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
824 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
825 unsigned int dic = 0; /* Output driver impedance, 40ohm */
826 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
827 1=Disable (Test/Debug) */
829 /* Mode Register - MR0 */
830 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
831 unsigned int wr; /* Write Recovery */
832 unsigned int dll_rst; /* DLL Reset */
833 unsigned int mode; /* Normal=0 or Test=1 */
834 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
835 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
837 unsigned int bl; /* BL: Burst Length */
839 unsigned int wr_mclk;
841 * DDR_SDRAM_MODE doesn't support 9,11,13,15
842 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
845 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
847 const unsigned int mclk_ps = get_memory_clk_period_ps();
850 if (popts->rtt_override)
851 rtt = popts->rtt_override_value;
853 rtt = popts->cs_local_opts[0].odt_rtt_norm;
855 if (additive_latency == (cas_latency - 1))
857 if (additive_latency == (cas_latency - 2))
860 if (popts->quad_rank_present)
861 dic = 1; /* output driver impedance 240/7 ohm */
864 * The esdmode value will also be used for writing
865 * MR1 during write leveling for DDR3, although the
866 * bits specifically related to the write leveling
867 * scheme will be handled automatically by the DDR
868 * controller. so we set the wrlvl_en = 0 here.
871 | ((qoff & 0x1) << 12)
872 | ((tdqs_en & 0x1) << 11)
873 | ((rtt & 0x4) << 7) /* rtt field is split */
874 | ((wrlvl_en & 0x1) << 7)
875 | ((rtt & 0x2) << 5) /* rtt field is split */
876 | ((dic & 0x2) << 4) /* DIC field is split */
878 | ((rtt & 0x1) << 2) /* rtt field is split */
879 | ((dic & 0x1) << 1) /* DIC field is split */
880 | ((dll_en & 0x1) << 0)
884 * DLL control for precharge PD
885 * 0=slow exit DLL off (tXPDLL)
886 * 1=fast exit DLL on (tXP)
890 wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
891 wr = wr_table[wr_mclk - 5];
893 dll_rst = 0; /* dll no reset */
894 mode = 0; /* normal mode */
896 /* look up table to get the cas latency bits */
897 if (cas_latency >= 5 && cas_latency <= 11) {
898 unsigned char cas_latency_table[7] = {
907 caslat = cas_latency_table[cas_latency - 5];
909 bt = 0; /* Nibble sequential */
911 switch (popts->burst_length) {
922 printf("Error: invalid burst length of %u specified. "
923 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
924 popts->burst_length);
930 | ((dll_on & 0x1) << 12)
932 | ((dll_rst & 0x1) << 8)
933 | ((mode & 0x1) << 7)
934 | (((caslat >> 1) & 0x7) << 4)
939 ddr->ddr_sdram_mode = (0
940 | ((esdmode & 0xFFFF) << 16)
941 | ((sdmode & 0xFFFF) << 0)
944 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
946 if (unq_mrs_en) { /* unique mode registers are supported */
947 for (i = 1; i < 4; i++) {
948 if (popts->rtt_override)
949 rtt = popts->rtt_override_value;
951 rtt = popts->cs_local_opts[i].odt_rtt_norm;
953 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
955 | ((rtt & 0x4) << 7) /* rtt field is split */
956 | ((rtt & 0x2) << 5) /* rtt field is split */
957 | ((rtt & 0x1) << 2) /* rtt field is split */
961 ddr->ddr_sdram_mode_3 = (0
962 | ((esdmode & 0xFFFF) << 16)
963 | ((sdmode & 0xFFFF) << 0)
967 ddr->ddr_sdram_mode_5 = (0
968 | ((esdmode & 0xFFFF) << 16)
969 | ((sdmode & 0xFFFF) << 0)
973 ddr->ddr_sdram_mode_7 = (0
974 | ((esdmode & 0xFFFF) << 16)
975 | ((sdmode & 0xFFFF) << 0)
980 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
981 ddr->ddr_sdram_mode_3);
982 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
983 ddr->ddr_sdram_mode_5);
984 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
985 ddr->ddr_sdram_mode_5);
989 #else /* !CONFIG_FSL_DDR3 */
991 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
992 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
993 const memctl_options_t *popts,
994 const common_timing_params_t *common_dimm,
995 unsigned int cas_latency,
996 unsigned int additive_latency,
997 const unsigned int unq_mrs_en)
999 unsigned short esdmode; /* Extended SDRAM mode */
1000 unsigned short sdmode; /* SDRAM mode */
1003 * FIXME: This ought to be pre-calculated in a
1004 * technology-specific routine,
1005 * e.g. compute_DDR2_mode_register(), and then the
1006 * sdmode and esdmode passed in as part of common_dimm.
1009 /* Extended Mode Register */
1010 unsigned int mrs = 0; /* Mode Register Set */
1011 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1012 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1013 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1014 unsigned int ocd = 0; /* 0x0=OCD not supported,
1015 0x7=OCD default state */
1017 unsigned int al; /* Posted CAS# additive latency (AL) */
1018 unsigned int ods = 0; /* Output Drive Strength:
1019 0 = Full strength (18ohm)
1020 1 = Reduced strength (4ohm) */
1021 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1022 1=Disable (Test/Debug) */
1024 /* Mode Register (MR) */
1025 unsigned int mr; /* Mode Register Definition */
1026 unsigned int pd; /* Power-Down Mode */
1027 unsigned int wr; /* Write Recovery */
1028 unsigned int dll_res; /* DLL Reset */
1029 unsigned int mode; /* Normal=0 or Test=1 */
1030 unsigned int caslat = 0;/* CAS# latency */
1031 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1033 unsigned int bl; /* BL: Burst Length */
1035 #if defined(CONFIG_FSL_DDR2)
1036 const unsigned int mclk_ps = get_memory_clk_period_ps();
1038 dqs_en = !popts->DQS_config;
1039 rtt = fsl_ddr_get_rtt();
1041 al = additive_latency;
1044 | ((mrs & 0x3) << 14)
1045 | ((outputs & 0x1) << 12)
1046 | ((rdqs_en & 0x1) << 11)
1047 | ((dqs_en & 0x1) << 10)
1048 | ((ocd & 0x7) << 7)
1049 | ((rtt & 0x2) << 5) /* rtt field is split */
1051 | ((rtt & 0x1) << 2) /* rtt field is split */
1052 | ((ods & 0x1) << 1)
1053 | ((dll_en & 0x1) << 0)
1056 mr = 0; /* FIXME: CHECKME */
1059 * 0 = Fast Exit (Normal)
1060 * 1 = Slow Exit (Low Power)
1064 #if defined(CONFIG_FSL_DDR1)
1065 wr = 0; /* Historical */
1066 #elif defined(CONFIG_FSL_DDR2)
1067 wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
1072 #if defined(CONFIG_FSL_DDR1)
1073 if (1 <= cas_latency && cas_latency <= 4) {
1074 unsigned char mode_caslat_table[4] = {
1075 0x5, /* 1.5 clocks */
1076 0x2, /* 2.0 clocks */
1077 0x6, /* 2.5 clocks */
1078 0x3 /* 3.0 clocks */
1080 caslat = mode_caslat_table[cas_latency - 1];
1082 printf("Warning: unknown cas_latency %d\n", cas_latency);
1084 #elif defined(CONFIG_FSL_DDR2)
1085 caslat = cas_latency;
1089 switch (popts->burst_length) {
1097 printf("Error: invalid burst length of %u specified. "
1098 " Defaulting to 4 beats.\n",
1099 popts->burst_length);
1105 | ((mr & 0x3) << 14)
1106 | ((pd & 0x1) << 12)
1108 | ((dll_res & 0x1) << 8)
1109 | ((mode & 0x1) << 7)
1110 | ((caslat & 0x7) << 4)
1115 ddr->ddr_sdram_mode = (0
1116 | ((esdmode & 0xFFFF) << 16)
1117 | ((sdmode & 0xFFFF) << 0)
1119 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1123 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1124 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1126 unsigned int init_value; /* Initialization value */
1128 init_value = 0xDEADBEEF;
1129 ddr->ddr_data_init = init_value;
1133 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1134 * The old controller on the 8540/60 doesn't have this register.
1135 * Hope it's OK to set it (to 0) anyway.
1137 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1138 const memctl_options_t *popts)
1140 unsigned int clk_adjust; /* Clock adjust */
1142 clk_adjust = popts->clk_adjust;
1143 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1144 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1147 /* DDR Initialization Address (DDR_INIT_ADDR) */
1148 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1150 unsigned int init_addr = 0; /* Initialization address */
1152 ddr->ddr_init_addr = init_addr;
1155 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1156 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1158 unsigned int uia = 0; /* Use initialization address */
1159 unsigned int init_ext_addr = 0; /* Initialization address */
1161 ddr->ddr_init_ext_addr = (0
1162 | ((uia & 0x1) << 31)
1163 | (init_ext_addr & 0xF)
1167 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1168 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1169 const memctl_options_t *popts)
1171 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1172 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1173 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1174 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1175 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1177 #if defined(CONFIG_FSL_DDR3)
1178 if (popts->burst_length == DDR_BL8) {
1179 /* We set BL/2 for fixed BL8 */
1180 rrt = 0; /* BL/2 clocks */
1181 wwt = 0; /* BL/2 clocks */
1183 /* We need to set BL/2 + 2 to BC4 and OTF */
1184 rrt = 2; /* BL/2 + 2 clocks */
1185 wwt = 2; /* BL/2 + 2 clocks */
1187 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1189 ddr->timing_cfg_4 = (0
1190 | ((rwt & 0xf) << 28)
1191 | ((wrt & 0xf) << 24)
1192 | ((rrt & 0xf) << 20)
1193 | ((wwt & 0xf) << 16)
1196 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1199 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1200 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1202 unsigned int rodt_on = 0; /* Read to ODT on */
1203 unsigned int rodt_off = 0; /* Read to ODT off */
1204 unsigned int wodt_on = 0; /* Write to ODT on */
1205 unsigned int wodt_off = 0; /* Write to ODT off */
1207 #if defined(CONFIG_FSL_DDR3)
1208 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1209 rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1210 rodt_off = 4; /* 4 clocks */
1211 wodt_on = 1; /* 1 clocks */
1212 wodt_off = 4; /* 4 clocks */
1215 ddr->timing_cfg_5 = (0
1216 | ((rodt_on & 0x1f) << 24)
1217 | ((rodt_off & 0x7) << 20)
1218 | ((wodt_on & 0x1f) << 12)
1219 | ((wodt_off & 0x7) << 8)
1221 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1224 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1225 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1227 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1228 /* Normal Operation Full Calibration Time (tZQoper) */
1229 unsigned int zqoper = 0;
1230 /* Normal Operation Short Calibration Time (tZQCS) */
1231 unsigned int zqcs = 0;
1234 zqinit = 9; /* 512 clocks */
1235 zqoper = 8; /* 256 clocks */
1236 zqcs = 6; /* 64 clocks */
1239 ddr->ddr_zq_cntl = (0
1240 | ((zq_en & 0x1) << 31)
1241 | ((zqinit & 0xF) << 24)
1242 | ((zqoper & 0xF) << 16)
1243 | ((zqcs & 0xF) << 8)
1245 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1248 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1249 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1250 const memctl_options_t *popts)
1253 * First DQS pulse rising edge after margining mode
1254 * is programmed (tWL_MRD)
1256 unsigned int wrlvl_mrd = 0;
1257 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1258 unsigned int wrlvl_odten = 0;
1259 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1260 unsigned int wrlvl_dqsen = 0;
1261 /* WRLVL_SMPL: Write leveling sample time */
1262 unsigned int wrlvl_smpl = 0;
1263 /* WRLVL_WLR: Write leveling repeition time */
1264 unsigned int wrlvl_wlr = 0;
1265 /* WRLVL_START: Write leveling start time */
1266 unsigned int wrlvl_start = 0;
1268 /* suggest enable write leveling for DDR3 due to fly-by topology */
1270 /* tWL_MRD min = 40 nCK, we set it 64 */
1274 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1277 * Write leveling sample time at least need 6 clocks
1278 * higher than tWLO to allow enough time for progagation
1279 * delay and sampling the prime data bits.
1283 * Write leveling repetition time
1284 * at least tWLO + 6 clocks clocks
1289 * Write leveling start time
1290 * The value use for the DQS_ADJUST for the first sample
1291 * when write leveling is enabled. It probably needs to be
1292 * overriden per platform.
1296 * Override the write leveling sample and start time
1297 * according to specific board
1299 if (popts->wrlvl_override) {
1300 wrlvl_smpl = popts->wrlvl_sample;
1301 wrlvl_start = popts->wrlvl_start;
1305 ddr->ddr_wrlvl_cntl = (0
1306 | ((wrlvl_en & 0x1) << 31)
1307 | ((wrlvl_mrd & 0x7) << 24)
1308 | ((wrlvl_odten & 0x7) << 20)
1309 | ((wrlvl_dqsen & 0x7) << 16)
1310 | ((wrlvl_smpl & 0xf) << 12)
1311 | ((wrlvl_wlr & 0x7) << 8)
1312 | ((wrlvl_start & 0x1F) << 0)
1314 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1317 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1318 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1320 /* Self Refresh Idle Threshold */
1321 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1324 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1326 if (popts->addr_hash) {
1327 ddr->ddr_eor = 0x40000000; /* address hash enable */
1328 puts("Address hashing enabled.\n");
1332 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1334 ddr->ddr_cdr1 = popts->ddr_cdr1;
1335 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1339 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1341 unsigned int res = 0;
1344 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1345 * not set at the same time.
1347 if (ddr->ddr_sdram_cfg & 0x10000000
1348 && ddr->ddr_sdram_cfg & 0x00008000) {
1349 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1350 " should not be set at the same time.\n");
1358 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1359 fsl_ddr_cfg_regs_t *ddr,
1360 const common_timing_params_t *common_dimm,
1361 const dimm_params_t *dimm_params,
1362 unsigned int dbw_cap_adj,
1363 unsigned int size_only)
1366 unsigned int cas_latency;
1367 unsigned int additive_latency;
1370 unsigned int wrlvl_en;
1371 unsigned int ip_rev = 0;
1372 unsigned int unq_mrs_en = 0;
1375 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1377 if (common_dimm == NULL) {
1378 printf("Error: subset DIMM params struct null pointer\n");
1383 * Process overrides first.
1385 * FIXME: somehow add dereated caslat to this
1387 cas_latency = (popts->cas_latency_override)
1388 ? popts->cas_latency_override_value
1389 : common_dimm->lowest_common_SPD_caslat;
1391 additive_latency = (popts->additive_latency_override)
1392 ? popts->additive_latency_override_value
1393 : common_dimm->additive_latency;
1395 sr_it = (popts->auto_self_refresh_en)
1398 /* ZQ calibration */
1399 zq_en = (popts->zq_en) ? 1 : 0;
1400 /* write leveling */
1401 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1403 /* Chip Select Memory Bounds (CSn_BNDS) */
1404 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1405 unsigned long long ea = 0, sa = 0;
1406 unsigned int cs_per_dimm
1407 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1408 unsigned int dimm_number
1410 unsigned long long rank_density
1411 = dimm_params[dimm_number].rank_density;
1413 if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) ||
1414 ((i == 2) && (popts->ba_intlv_ctl & 0x04)) ||
1415 ((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) {
1417 * Don't set up boundaries for unused CS
1418 * cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1419 * cs2 for cs0_cs1_cs2_cs3
1420 * cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1421 * But we need to set the ODT_RD_CFG and
1422 * ODT_WR_CFG for CS1_CONFIG here.
1424 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1427 if (dimm_params[dimm_number].n_ranks == 0) {
1428 debug("Skipping setup of CS%u "
1429 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1432 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
1434 * This works superbank 2CS
1435 * There are 2 or more memory controllers configured
1436 * identically, memory is interleaved between them,
1437 * and each controller uses rank interleaving within
1438 * itself. Therefore the starting and ending address
1439 * on each controller is twice the amount present on
1440 * each controller. If any CS is not included in the
1441 * interleaving, the memory on that CS is not accssible
1442 * and the total memory size is reduced. The CS is also
1445 unsigned long long ctlr_density = 0;
1446 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1447 case FSL_DDR_CS0_CS1:
1448 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1449 ctlr_density = dimm_params[0].rank_density * 2;
1453 case FSL_DDR_CS2_CS3:
1454 ctlr_density = dimm_params[0].rank_density;
1458 case FSL_DDR_CS0_CS1_CS2_CS3:
1460 * The four CS interleaving should have been verified by
1461 * populate_memctl_options()
1463 ctlr_density = dimm_params[0].rank_density * 4;
1468 ea = (CONFIG_NUM_DDR_CONTROLLERS *
1469 (ctlr_density >> dbw_cap_adj)) - 1;
1471 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
1473 * If memory interleaving between controllers is NOT
1474 * enabled, the starting address for each memory
1475 * controller is distinct. However, because rank
1476 * interleaving is enabled, the starting and ending
1477 * addresses of the total memory on that memory
1478 * controller needs to be programmed into its
1479 * respective CS0_BNDS.
1481 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1482 case FSL_DDR_CS0_CS1_CS2_CS3:
1483 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
1486 sa = common_dimm->base_address;
1487 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
1489 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1490 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
1491 * and CS2_CNDS need to be set.
1493 if ((i == 2) && (dimm_number == 0)) {
1494 sa = dimm_params[dimm_number].base_address +
1495 2 * (rank_density >> dbw_cap_adj);
1496 ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1;
1498 sa = dimm_params[dimm_number].base_address;
1499 ea = sa + (2 * (rank_density >>
1503 case FSL_DDR_CS0_CS1:
1504 /* CS0+CS1 interleaving, CS0_CNDS needs
1507 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1508 sa = dimm_params[dimm_number].base_address;
1509 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1510 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1511 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1517 ea += (rank_density >> dbw_cap_adj);
1519 case FSL_DDR_CS2_CS3:
1520 /* CS2+CS3 interleaving*/
1521 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1522 sa = dimm_params[dimm_number].base_address;
1523 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1524 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1525 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1531 ea += (rank_density >> dbw_cap_adj);
1533 default: /* No bank(chip-select) interleaving */
1537 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1539 * Only the rank on CS0 of each memory controller may
1540 * be used if memory controller interleaving is used
1541 * without rank interleaving within each memory
1542 * controller. However, the ending address programmed
1543 * into each CS0 must be the sum of the amount of
1544 * memory in the two CS0 ranks.
1547 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1551 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1553 * No rank interleaving and no memory controller
1556 sa = dimm_params[dimm_number].base_address;
1557 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1558 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1559 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1560 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1570 ddr->cs[i].bnds = (0
1571 | ((sa & 0xFFF) << 16) /* starting address MSB */
1572 | ((ea & 0xFFF) << 0) /* ending address MSB */
1575 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1577 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1578 set_csn_config_2(i, ddr);
1580 printf("CS%d is disabled.\n", i);
1584 * In the case we only need to compute the ddr sdram size, we only need
1585 * to set csn registers, so return from here.
1590 set_ddr_eor(ddr, popts);
1592 #if !defined(CONFIG_FSL_DDR1)
1593 set_timing_cfg_0(ddr, popts);
1596 set_timing_cfg_3(ddr, common_dimm, cas_latency);
1597 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1598 set_timing_cfg_2(ddr, popts, common_dimm,
1599 cas_latency, additive_latency);
1601 set_ddr_cdr1(ddr, popts);
1602 set_ddr_sdram_cfg(ddr, popts, common_dimm);
1603 ip_rev = fsl_ddr_get_version();
1604 if (ip_rev > 0x40400)
1607 set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1608 set_ddr_sdram_mode(ddr, popts, common_dimm,
1609 cas_latency, additive_latency, unq_mrs_en);
1610 set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
1611 set_ddr_sdram_interval(ddr, popts, common_dimm);
1612 set_ddr_data_init(ddr);
1613 set_ddr_sdram_clk_cntl(ddr, popts);
1614 set_ddr_init_addr(ddr);
1615 set_ddr_init_ext_addr(ddr);
1616 set_timing_cfg_4(ddr, popts);
1617 set_timing_cfg_5(ddr, cas_latency);
1619 set_ddr_zq_cntl(ddr, zq_en);
1620 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1622 set_ddr_sr_cntr(ddr, sr_it);
1624 set_ddr_sdram_rcw(ddr, popts, common_dimm);
1626 return check_fsl_memctl_config_regs(ddr);