2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
11 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
12 * Based on code from spd_sdram.c
13 * Author: James Yang [at freescale.com]
17 #include <asm/fsl_ddr_sdram.h>
22 #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
23 #elif defined(CONFIG_MPC86xx)
24 #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
26 #error "Undefined _DDR_ADDR"
29 u32 fsl_ddr_get_version(void)
32 u32 ver_major_minor_errata;
34 ddr = (void *)_DDR_ADDR;
35 ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
36 ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
38 return ver_major_minor_errata;
41 unsigned int picos_to_mclk(unsigned int picos);
44 * Determine Rtt value.
46 * This should likely be either board or controller specific.
48 * Rtt(nominal) - DDR2:
53 * Rtt(nominal) - DDR3:
61 * FIXME: Apparently 8641 needs a value of 2
62 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
64 * FIXME: There was some effort down this line earlier:
67 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
68 * if (popts->dimmslot[i].num_valid_cs
69 * && (popts->cs_local_opts[2*i].odt_rd_cfg
70 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
76 static inline int fsl_ddr_get_rtt(void)
80 #if defined(CONFIG_FSL_DDR1)
82 #elif defined(CONFIG_FSL_DDR2)
92 * compute the CAS write latency according to DDR3 spec
93 * CWL = 5 if tCK >= 2.5ns
94 * 6 if 2.5ns > tCK >= 1.875ns
95 * 7 if 1.875ns > tCK >= 1.5ns
96 * 8 if 1.5ns > tCK >= 1.25ns
98 static inline unsigned int compute_cas_write_latency(void)
101 const unsigned int mclk_ps = get_memory_clk_period_ps();
105 else if (mclk_ps >= 1875)
107 else if (mclk_ps >= 1500)
109 else if (mclk_ps >= 1250)
116 /* Chip Select Configuration (CSn_CONFIG) */
117 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
118 const memctl_options_t *popts,
119 const dimm_params_t *dimm_params)
121 unsigned int cs_n_en = 0; /* Chip Select enable */
122 unsigned int intlv_en = 0; /* Memory controller interleave enable */
123 unsigned int intlv_ctl = 0; /* Interleaving control */
124 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
125 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
126 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
127 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
128 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
129 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
132 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
135 if (dimm_params[dimm_number].n_ranks > 0) {
137 /* These fields only available in CS0_CONFIG */
138 intlv_en = popts->memctl_interleaving;
139 intlv_ctl = popts->memctl_interleaving_mode;
143 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
144 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
148 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
149 (dimm_number > 1 && dimm_params[dimm_number].n_ranks > 0))
153 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
154 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
155 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
162 unsigned int n_banks_per_sdram_device;
164 ap_n_en = popts->cs_local_opts[i].auto_precharge;
165 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
166 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
167 n_banks_per_sdram_device
168 = dimm_params[dimm_number].n_banks_per_sdram_device;
169 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
170 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
171 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
173 ddr->cs[i].config = (0
174 | ((cs_n_en & 0x1) << 31)
175 | ((intlv_en & 0x3) << 29)
176 | ((intlv_ctl & 0xf) << 24)
177 | ((ap_n_en & 0x1) << 23)
179 /* XXX: some implementation only have 1 bit starting at left */
180 | ((odt_rd_cfg & 0x7) << 20)
182 /* XXX: Some implementation only have 1 bit starting at left */
183 | ((odt_wr_cfg & 0x7) << 16)
185 | ((ba_bits_cs_n & 0x3) << 14)
186 | ((row_bits_cs_n & 0x7) << 8)
187 | ((col_bits_cs_n & 0x7) << 0)
189 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
192 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
194 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
196 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
198 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
199 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
202 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
204 #if !defined(CONFIG_FSL_DDR1)
206 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
208 * Avoid writing for DDR I. The new PQ38 DDR controller
209 * dreams up non-zero default values to be backwards compatible.
211 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
212 const memctl_options_t *popts)
214 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
215 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
216 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
217 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
218 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
220 /* Active powerdown exit timing (tXARD and tXARDS). */
221 unsigned char act_pd_exit_mclk;
222 /* Precharge powerdown exit timing (tXP). */
223 unsigned char pre_pd_exit_mclk;
224 /* ODT powerdown exit timing (tAXPD). */
225 unsigned char taxpd_mclk;
226 /* Mode register set cycle time (tMRD). */
227 unsigned char tmrd_mclk;
229 #ifdef CONFIG_FSL_DDR3
231 * (tXARD and tXARDS). Empirical?
232 * The DDR3 spec has not tXARD,
233 * we use the tXP instead of it.
234 * tXP=max(3nCK, 7.5ns) for DDR3.
235 * spec has not the tAXPD, we use
236 * tAXPD=1, need design to confirm.
238 int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
240 /* set the turnaround time */
243 if (popts->dynamic_power == 0) { /* powerdown is not used */
244 act_pd_exit_mclk = 1;
245 pre_pd_exit_mclk = 1;
248 /* act_pd_exit_mclk = tXARD, see above */
249 act_pd_exit_mclk = picos_to_mclk(tXP);
250 /* Mode register MR0[A12] is '1' - fast exit */
251 pre_pd_exit_mclk = act_pd_exit_mclk;
254 #else /* CONFIG_FSL_DDR2 */
256 * (tXARD and tXARDS). Empirical?
261 act_pd_exit_mclk = 2;
262 pre_pd_exit_mclk = 2;
267 ddr->timing_cfg_0 = (0
268 | ((trwt_mclk & 0x3) << 30) /* RWT */
269 | ((twrt_mclk & 0x3) << 28) /* WRT */
270 | ((trrt_mclk & 0x3) << 26) /* RRT */
271 | ((twwt_mclk & 0x3) << 24) /* WWT */
272 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
273 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
274 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
275 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
277 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
279 #endif /* defined(CONFIG_FSL_DDR2) */
281 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
282 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
283 const common_timing_params_t *common_dimm,
284 unsigned int cas_latency)
286 /* Extended Activate to precharge interval (tRAS) */
287 unsigned int ext_acttopre = 0;
288 unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
289 unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
290 unsigned int cntl_adj = 0; /* Control Adjust */
292 /* If the tRAS > 19 MCLK, we use the ext mode */
293 if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
296 ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
298 /* If the CAS latency more than 8, use the ext mode */
302 ddr->timing_cfg_3 = (0
303 | ((ext_acttopre & 0x1) << 24)
304 | ((ext_refrec & 0xF) << 16)
305 | ((ext_caslat & 0x1) << 12)
306 | ((cntl_adj & 0x7) << 0)
308 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
311 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
312 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
313 const memctl_options_t *popts,
314 const common_timing_params_t *common_dimm,
315 unsigned int cas_latency)
317 /* Precharge-to-activate interval (tRP) */
318 unsigned char pretoact_mclk;
319 /* Activate to precharge interval (tRAS) */
320 unsigned char acttopre_mclk;
321 /* Activate to read/write interval (tRCD) */
322 unsigned char acttorw_mclk;
324 unsigned char caslat_ctrl;
325 /* Refresh recovery time (tRFC) ; trfc_low */
326 unsigned char refrec_ctrl;
327 /* Last data to precharge minimum interval (tWR) */
328 unsigned char wrrec_mclk;
329 /* Activate-to-activate interval (tRRD) */
330 unsigned char acttoact_mclk;
331 /* Last write data pair to read command issue interval (tWTR) */
332 unsigned char wrtord_mclk;
334 pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
335 acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
336 acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
339 * Translate CAS Latency to a DDR controller field value:
341 * CAS Lat DDR I DDR II Ctrl
342 * Clocks SPD Bit SPD Bit Value
343 * ------- ------- ------- -----
354 #if defined(CONFIG_FSL_DDR1)
355 caslat_ctrl = (cas_latency + 1) & 0x07;
356 #elif defined(CONFIG_FSL_DDR2)
357 caslat_ctrl = 2 * cas_latency - 1;
360 * if the CAS latency more than 8 cycle,
361 * we need set extend bit for it at
362 * TIMING_CFG_3[EXT_CASLAT]
366 caslat_ctrl = 2 * cas_latency - 1;
369 refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
370 wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
371 if (popts->OTF_burst_chop_en)
374 acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
376 * JEDEC has min requirement for tRRD
378 #if defined(CONFIG_FSL_DDR3)
379 if (acttoact_mclk < 4)
382 wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
384 * JEDEC has some min requirements for tWTR
386 #if defined(CONFIG_FSL_DDR2)
389 #elif defined(CONFIG_FSL_DDR3)
393 if (popts->OTF_burst_chop_en)
396 ddr->timing_cfg_1 = (0
397 | ((pretoact_mclk & 0x0F) << 28)
398 | ((acttopre_mclk & 0x0F) << 24)
399 | ((acttorw_mclk & 0xF) << 20)
400 | ((caslat_ctrl & 0xF) << 16)
401 | ((refrec_ctrl & 0xF) << 12)
402 | ((wrrec_mclk & 0x0F) << 8)
403 | ((acttoact_mclk & 0x07) << 4)
404 | ((wrtord_mclk & 0x07) << 0)
406 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
409 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
410 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
411 const memctl_options_t *popts,
412 const common_timing_params_t *common_dimm,
413 unsigned int cas_latency,
414 unsigned int additive_latency)
416 /* Additive latency */
417 unsigned char add_lat_mclk;
418 /* CAS-to-preamble override */
421 unsigned char wr_lat;
422 /* Read to precharge (tRTP) */
423 unsigned char rd_to_pre;
424 /* Write command to write data strobe timing adjustment */
425 unsigned char wr_data_delay;
426 /* Minimum CKE pulse width (tCKE) */
427 unsigned char cke_pls;
428 /* Window for four activates (tFAW) */
429 unsigned short four_act;
431 /* FIXME add check that this must be less than acttorw_mclk */
432 add_lat_mclk = additive_latency;
433 cpo = popts->cpo_override;
435 #if defined(CONFIG_FSL_DDR1)
437 * This is a lie. It should really be 1, but if it is
438 * set to 1, bits overlap into the old controller's
439 * otherwise unused ACSM field. If we leave it 0, then
440 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
443 #elif defined(CONFIG_FSL_DDR2)
444 wr_lat = cas_latency - 1;
446 wr_lat = compute_cas_write_latency();
449 rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
451 * JEDEC has some min requirements for tRTP
453 #if defined(CONFIG_FSL_DDR2)
456 #elif defined(CONFIG_FSL_DDR3)
460 if (additive_latency)
461 rd_to_pre += additive_latency;
462 if (popts->OTF_burst_chop_en)
463 rd_to_pre += 2; /* according to UM */
465 wr_data_delay = popts->write_data_delay;
466 cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
467 four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
469 ddr->timing_cfg_2 = (0
470 | ((add_lat_mclk & 0xf) << 28)
471 | ((cpo & 0x1f) << 23)
472 | ((wr_lat & 0xf) << 19)
473 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
474 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
475 | ((cke_pls & 0x7) << 6)
476 | ((four_act & 0x3f) << 0)
478 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
481 /* DDR SDRAM Register Control Word */
482 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
483 const memctl_options_t *popts,
484 const common_timing_params_t *common_dimm)
486 if (common_dimm->all_DIMMs_registered
487 && !common_dimm->all_DIMMs_unbuffered) {
488 if (popts->rcw_override) {
489 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
490 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
492 ddr->ddr_sdram_rcw_1 =
493 common_dimm->rcw[0] << 28 | \
494 common_dimm->rcw[1] << 24 | \
495 common_dimm->rcw[2] << 20 | \
496 common_dimm->rcw[3] << 16 | \
497 common_dimm->rcw[4] << 12 | \
498 common_dimm->rcw[5] << 8 | \
499 common_dimm->rcw[6] << 4 | \
501 ddr->ddr_sdram_rcw_2 =
502 common_dimm->rcw[8] << 28 | \
503 common_dimm->rcw[9] << 24 | \
504 common_dimm->rcw[10] << 20 | \
505 common_dimm->rcw[11] << 16 | \
506 common_dimm->rcw[12] << 12 | \
507 common_dimm->rcw[13] << 8 | \
508 common_dimm->rcw[14] << 4 | \
509 common_dimm->rcw[15];
511 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
512 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
516 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
517 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
518 const memctl_options_t *popts,
519 const common_timing_params_t *common_dimm)
521 unsigned int mem_en; /* DDR SDRAM interface logic enable */
522 unsigned int sren; /* Self refresh enable (during sleep) */
523 unsigned int ecc_en; /* ECC enable. */
524 unsigned int rd_en; /* Registered DIMM enable */
525 unsigned int sdram_type; /* Type of SDRAM */
526 unsigned int dyn_pwr; /* Dynamic power management mode */
527 unsigned int dbw; /* DRAM dta bus width */
528 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
529 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
530 unsigned int threeT_en; /* Enable 3T timing */
531 unsigned int twoT_en; /* Enable 2T timing */
532 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
533 unsigned int x32_en = 0; /* x32 enable */
534 unsigned int pchb8 = 0; /* precharge bit 8 enable */
535 unsigned int hse; /* Global half strength override */
536 unsigned int mem_halt = 0; /* memory controller halt */
537 unsigned int bi = 0; /* Bypass initialization */
540 sren = popts->self_refresh_in_sleep;
541 if (common_dimm->all_DIMMs_ECC_capable) {
542 /* Allow setting of ECC only if all DIMMs are ECC. */
543 ecc_en = popts->ECC_mode;
548 if (common_dimm->all_DIMMs_registered
549 && !common_dimm->all_DIMMs_unbuffered) {
554 twoT_en = popts->twoT_en;
557 sdram_type = CONFIG_FSL_SDRAM_TYPE;
559 dyn_pwr = popts->dynamic_power;
560 dbw = popts->data_bus_width;
561 /* 8-beat burst enable DDR-III case
562 * we must clear it when use the on-the-fly mode,
563 * must set it when use the 32-bits bus mode.
565 if (sdram_type == SDRAM_TYPE_DDR3) {
566 if (popts->burst_length == DDR_BL8)
568 if (popts->burst_length == DDR_OTF)
574 threeT_en = popts->threeT_en;
575 ba_intlv_ctl = popts->ba_intlv_ctl;
576 hse = popts->half_strength_driver_enable;
578 ddr->ddr_sdram_cfg = (0
579 | ((mem_en & 0x1) << 31)
580 | ((sren & 0x1) << 30)
581 | ((ecc_en & 0x1) << 29)
582 | ((rd_en & 0x1) << 28)
583 | ((sdram_type & 0x7) << 24)
584 | ((dyn_pwr & 0x1) << 21)
585 | ((dbw & 0x3) << 19)
586 | ((eight_be & 0x1) << 18)
587 | ((ncap & 0x1) << 17)
588 | ((threeT_en & 0x1) << 16)
589 | ((twoT_en & 0x1) << 15)
590 | ((ba_intlv_ctl & 0x7F) << 8)
591 | ((x32_en & 0x1) << 5)
592 | ((pchb8 & 0x1) << 4)
594 | ((mem_halt & 0x1) << 1)
597 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
600 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
601 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
602 const memctl_options_t *popts,
603 const unsigned int unq_mrs_en)
605 unsigned int frc_sr = 0; /* Force self refresh */
606 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
607 unsigned int dll_rst_dis; /* DLL reset disable */
608 unsigned int dqs_cfg; /* DQS configuration */
609 unsigned int odt_cfg; /* ODT configuration */
610 unsigned int num_pr; /* Number of posted refreshes */
611 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
612 unsigned int ap_en; /* Address Parity Enable */
613 unsigned int d_init; /* DRAM data initialization */
614 unsigned int rcw_en = 0; /* Register Control Word Enable */
615 unsigned int md_en = 0; /* Mirrored DIMM Enable */
616 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
618 dll_rst_dis = 1; /* Make this configurable */
619 dqs_cfg = popts->DQS_config;
620 if (popts->cs_local_opts[0].odt_rd_cfg
621 || popts->cs_local_opts[0].odt_wr_cfg) {
628 num_pr = 1; /* Make this configurable */
632 * {TIMING_CFG_1[PRETOACT]
633 * + [DDR_SDRAM_CFG_2[NUM_PR]
634 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
635 * << DDR_SDRAM_INTERVAL[REFINT]
637 #if defined(CONFIG_FSL_DDR3)
638 obc_cfg = popts->OTF_burst_chop_en;
643 if (popts->registered_dimm_en) {
645 ap_en = popts->ap_en;
651 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
652 /* Use the DDR controller to auto initialize memory. */
653 d_init = popts->ECC_init_using_memctl;
654 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
655 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
657 /* Memory will be initialized via DMA, or not at all. */
661 #if defined(CONFIG_FSL_DDR3)
662 md_en = popts->mirrored_dimm;
664 qd_en = popts->quad_rank_present ? 1 : 0;
665 ddr->ddr_sdram_cfg_2 = (0
666 | ((frc_sr & 0x1) << 31)
667 | ((sr_ie & 0x1) << 30)
668 | ((dll_rst_dis & 0x1) << 29)
669 | ((dqs_cfg & 0x3) << 26)
670 | ((odt_cfg & 0x3) << 21)
671 | ((num_pr & 0xf) << 12)
674 | ((obc_cfg & 0x1) << 6)
675 | ((ap_en & 0x1) << 5)
676 | ((d_init & 0x1) << 4)
677 | ((rcw_en & 0x1) << 2)
678 | ((md_en & 0x1) << 0)
680 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
683 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
684 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
685 const memctl_options_t *popts,
686 const unsigned int unq_mrs_en)
688 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
689 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
692 #if defined(CONFIG_FSL_DDR3)
693 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
694 unsigned int srt = 0; /* self-refresh temerature, normal range */
695 unsigned int asr = 0; /* auto self-refresh disable */
696 unsigned int cwl = compute_cas_write_latency() - 5;
697 unsigned int pasr = 0; /* partial array self refresh disable */
699 if (popts->rtt_override)
700 rtt_wr = popts->rtt_wr_override_value;
702 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
704 | ((rtt_wr & 0x3) << 9)
708 | ((pasr & 0x7) << 0));
710 ddr->ddr_sdram_mode_2 = (0
711 | ((esdmode2 & 0xFFFF) << 16)
712 | ((esdmode3 & 0xFFFF) << 0)
714 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
716 #ifdef CONFIG_FSL_DDR3
717 if (unq_mrs_en) { /* unique mode registers are supported */
718 for (i = 1; i < 4; i++) {
719 if (popts->rtt_override)
720 rtt_wr = popts->rtt_wr_override_value;
722 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
724 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
725 esdmode2 |= (rtt_wr & 0x3) << 9;
728 ddr->ddr_sdram_mode_4 = (0
729 | ((esdmode2 & 0xFFFF) << 16)
730 | ((esdmode3 & 0xFFFF) << 0)
734 ddr->ddr_sdram_mode_6 = (0
735 | ((esdmode2 & 0xFFFF) << 16)
736 | ((esdmode3 & 0xFFFF) << 0)
740 ddr->ddr_sdram_mode_8 = (0
741 | ((esdmode2 & 0xFFFF) << 16)
742 | ((esdmode3 & 0xFFFF) << 0)
747 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
748 ddr->ddr_sdram_mode_4);
749 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
750 ddr->ddr_sdram_mode_6);
751 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
752 ddr->ddr_sdram_mode_8);
757 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
758 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
759 const memctl_options_t *popts,
760 const common_timing_params_t *common_dimm)
762 unsigned int refint; /* Refresh interval */
763 unsigned int bstopre; /* Precharge interval */
765 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
767 bstopre = popts->bstopre;
769 /* refint field used 0x3FFF in earlier controllers */
770 ddr->ddr_sdram_interval = (0
771 | ((refint & 0xFFFF) << 16)
772 | ((bstopre & 0x3FFF) << 0)
774 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
777 #if defined(CONFIG_FSL_DDR3)
778 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
779 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
780 const memctl_options_t *popts,
781 const common_timing_params_t *common_dimm,
782 unsigned int cas_latency,
783 unsigned int additive_latency,
784 const unsigned int unq_mrs_en)
786 unsigned short esdmode; /* Extended SDRAM mode */
787 unsigned short sdmode; /* SDRAM mode */
789 /* Mode Register - MR1 */
790 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
791 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
793 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
794 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
795 unsigned int dic = 0; /* Output driver impedance, 40ohm */
796 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
797 1=Disable (Test/Debug) */
799 /* Mode Register - MR0 */
800 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
801 unsigned int wr; /* Write Recovery */
802 unsigned int dll_rst; /* DLL Reset */
803 unsigned int mode; /* Normal=0 or Test=1 */
804 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
805 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
807 unsigned int bl; /* BL: Burst Length */
809 unsigned int wr_mclk;
811 const unsigned int mclk_ps = get_memory_clk_period_ps();
814 if (popts->rtt_override)
815 rtt = popts->rtt_override_value;
817 rtt = popts->cs_local_opts[0].odt_rtt_norm;
819 if (additive_latency == (cas_latency - 1))
821 if (additive_latency == (cas_latency - 2))
824 if (popts->quad_rank_present)
825 dic = 1; /* output driver impedance 240/7 ohm */
828 * The esdmode value will also be used for writing
829 * MR1 during write leveling for DDR3, although the
830 * bits specifically related to the write leveling
831 * scheme will be handled automatically by the DDR
832 * controller. so we set the wrlvl_en = 0 here.
835 | ((qoff & 0x1) << 12)
836 | ((tdqs_en & 0x1) << 11)
837 | ((rtt & 0x4) << 7) /* rtt field is split */
838 | ((wrlvl_en & 0x1) << 7)
839 | ((rtt & 0x2) << 5) /* rtt field is split */
840 | ((dic & 0x2) << 4) /* DIC field is split */
842 | ((rtt & 0x1) << 2) /* rtt field is split */
843 | ((dic & 0x1) << 1) /* DIC field is split */
844 | ((dll_en & 0x1) << 0)
848 * DLL control for precharge PD
849 * 0=slow exit DLL off (tXPDLL)
850 * 1=fast exit DLL on (tXP)
853 wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
856 else if (wr_mclk >= 9)
860 dll_rst = 0; /* dll no reset */
861 mode = 0; /* normal mode */
863 /* look up table to get the cas latency bits */
864 if (cas_latency >= 5 && cas_latency <= 11) {
865 unsigned char cas_latency_table[7] = {
874 caslat = cas_latency_table[cas_latency - 5];
876 bt = 0; /* Nibble sequential */
878 switch (popts->burst_length) {
889 printf("Error: invalid burst length of %u specified. "
890 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
891 popts->burst_length);
897 | ((dll_on & 0x1) << 12)
899 | ((dll_rst & 0x1) << 8)
900 | ((mode & 0x1) << 7)
901 | (((caslat >> 1) & 0x7) << 4)
906 ddr->ddr_sdram_mode = (0
907 | ((esdmode & 0xFFFF) << 16)
908 | ((sdmode & 0xFFFF) << 0)
911 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
913 if (unq_mrs_en) { /* unique mode registers are supported */
914 for (i = 1; i < 4; i++) {
915 if (popts->rtt_override)
916 rtt = popts->rtt_override_value;
918 rtt = popts->cs_local_opts[i].odt_rtt_norm;
920 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
922 | ((rtt & 0x4) << 7) /* rtt field is split */
923 | ((rtt & 0x2) << 5) /* rtt field is split */
924 | ((rtt & 0x1) << 2) /* rtt field is split */
928 ddr->ddr_sdram_mode_3 = (0
929 | ((esdmode & 0xFFFF) << 16)
930 | ((sdmode & 0xFFFF) << 0)
934 ddr->ddr_sdram_mode_5 = (0
935 | ((esdmode & 0xFFFF) << 16)
936 | ((sdmode & 0xFFFF) << 0)
940 ddr->ddr_sdram_mode_7 = (0
941 | ((esdmode & 0xFFFF) << 16)
942 | ((sdmode & 0xFFFF) << 0)
947 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
948 ddr->ddr_sdram_mode_3);
949 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
950 ddr->ddr_sdram_mode_5);
951 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
952 ddr->ddr_sdram_mode_5);
956 #else /* !CONFIG_FSL_DDR3 */
958 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
959 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
960 const memctl_options_t *popts,
961 const common_timing_params_t *common_dimm,
962 unsigned int cas_latency,
963 unsigned int additive_latency,
964 const unsigned int unq_mrs_en)
966 unsigned short esdmode; /* Extended SDRAM mode */
967 unsigned short sdmode; /* SDRAM mode */
970 * FIXME: This ought to be pre-calculated in a
971 * technology-specific routine,
972 * e.g. compute_DDR2_mode_register(), and then the
973 * sdmode and esdmode passed in as part of common_dimm.
976 /* Extended Mode Register */
977 unsigned int mrs = 0; /* Mode Register Set */
978 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
979 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
980 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
981 unsigned int ocd = 0; /* 0x0=OCD not supported,
982 0x7=OCD default state */
984 unsigned int al; /* Posted CAS# additive latency (AL) */
985 unsigned int ods = 0; /* Output Drive Strength:
986 0 = Full strength (18ohm)
987 1 = Reduced strength (4ohm) */
988 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
989 1=Disable (Test/Debug) */
991 /* Mode Register (MR) */
992 unsigned int mr; /* Mode Register Definition */
993 unsigned int pd; /* Power-Down Mode */
994 unsigned int wr; /* Write Recovery */
995 unsigned int dll_res; /* DLL Reset */
996 unsigned int mode; /* Normal=0 or Test=1 */
997 unsigned int caslat = 0;/* CAS# latency */
998 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1000 unsigned int bl; /* BL: Burst Length */
1002 #if defined(CONFIG_FSL_DDR2)
1003 const unsigned int mclk_ps = get_memory_clk_period_ps();
1006 rtt = fsl_ddr_get_rtt();
1008 al = additive_latency;
1011 | ((mrs & 0x3) << 14)
1012 | ((outputs & 0x1) << 12)
1013 | ((rdqs_en & 0x1) << 11)
1014 | ((dqs_en & 0x1) << 10)
1015 | ((ocd & 0x7) << 7)
1016 | ((rtt & 0x2) << 5) /* rtt field is split */
1018 | ((rtt & 0x1) << 2) /* rtt field is split */
1019 | ((ods & 0x1) << 1)
1020 | ((dll_en & 0x1) << 0)
1023 mr = 0; /* FIXME: CHECKME */
1026 * 0 = Fast Exit (Normal)
1027 * 1 = Slow Exit (Low Power)
1031 #if defined(CONFIG_FSL_DDR1)
1032 wr = 0; /* Historical */
1033 #elif defined(CONFIG_FSL_DDR2)
1034 wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
1039 #if defined(CONFIG_FSL_DDR1)
1040 if (1 <= cas_latency && cas_latency <= 4) {
1041 unsigned char mode_caslat_table[4] = {
1042 0x5, /* 1.5 clocks */
1043 0x2, /* 2.0 clocks */
1044 0x6, /* 2.5 clocks */
1045 0x3 /* 3.0 clocks */
1047 caslat = mode_caslat_table[cas_latency - 1];
1049 printf("Warning: unknown cas_latency %d\n", cas_latency);
1051 #elif defined(CONFIG_FSL_DDR2)
1052 caslat = cas_latency;
1056 switch (popts->burst_length) {
1064 printf("Error: invalid burst length of %u specified. "
1065 " Defaulting to 4 beats.\n",
1066 popts->burst_length);
1072 | ((mr & 0x3) << 14)
1073 | ((pd & 0x1) << 12)
1075 | ((dll_res & 0x1) << 8)
1076 | ((mode & 0x1) << 7)
1077 | ((caslat & 0x7) << 4)
1082 ddr->ddr_sdram_mode = (0
1083 | ((esdmode & 0xFFFF) << 16)
1084 | ((sdmode & 0xFFFF) << 0)
1086 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1090 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1091 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1093 unsigned int init_value; /* Initialization value */
1095 init_value = 0xDEADBEEF;
1096 ddr->ddr_data_init = init_value;
1100 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1101 * The old controller on the 8540/60 doesn't have this register.
1102 * Hope it's OK to set it (to 0) anyway.
1104 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1105 const memctl_options_t *popts)
1107 unsigned int clk_adjust; /* Clock adjust */
1109 clk_adjust = popts->clk_adjust;
1110 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1111 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1114 /* DDR Initialization Address (DDR_INIT_ADDR) */
1115 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1117 unsigned int init_addr = 0; /* Initialization address */
1119 ddr->ddr_init_addr = init_addr;
1122 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1123 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1125 unsigned int uia = 0; /* Use initialization address */
1126 unsigned int init_ext_addr = 0; /* Initialization address */
1128 ddr->ddr_init_ext_addr = (0
1129 | ((uia & 0x1) << 31)
1130 | (init_ext_addr & 0xF)
1134 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1135 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1136 const memctl_options_t *popts)
1138 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1139 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1140 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1141 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1142 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1144 #if defined(CONFIG_FSL_DDR3)
1145 if (popts->burst_length == DDR_BL8) {
1146 /* We set BL/2 for fixed BL8 */
1147 rrt = 0; /* BL/2 clocks */
1148 wwt = 0; /* BL/2 clocks */
1150 /* We need to set BL/2 + 2 to BC4 and OTF */
1151 rrt = 2; /* BL/2 + 2 clocks */
1152 wwt = 2; /* BL/2 + 2 clocks */
1154 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1156 ddr->timing_cfg_4 = (0
1157 | ((rwt & 0xf) << 28)
1158 | ((wrt & 0xf) << 24)
1159 | ((rrt & 0xf) << 20)
1160 | ((wwt & 0xf) << 16)
1163 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1166 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1167 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1169 unsigned int rodt_on = 0; /* Read to ODT on */
1170 unsigned int rodt_off = 0; /* Read to ODT off */
1171 unsigned int wodt_on = 0; /* Write to ODT on */
1172 unsigned int wodt_off = 0; /* Write to ODT off */
1174 #if defined(CONFIG_FSL_DDR3)
1175 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1176 rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1177 rodt_off = 4; /* 4 clocks */
1178 wodt_on = 1; /* 1 clocks */
1179 wodt_off = 4; /* 4 clocks */
1182 ddr->timing_cfg_5 = (0
1183 | ((rodt_on & 0x1f) << 24)
1184 | ((rodt_off & 0x7) << 20)
1185 | ((wodt_on & 0x1f) << 12)
1186 | ((wodt_off & 0x7) << 8)
1188 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1191 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1192 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1194 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1195 /* Normal Operation Full Calibration Time (tZQoper) */
1196 unsigned int zqoper = 0;
1197 /* Normal Operation Short Calibration Time (tZQCS) */
1198 unsigned int zqcs = 0;
1201 zqinit = 9; /* 512 clocks */
1202 zqoper = 8; /* 256 clocks */
1203 zqcs = 6; /* 64 clocks */
1206 ddr->ddr_zq_cntl = (0
1207 | ((zq_en & 0x1) << 31)
1208 | ((zqinit & 0xF) << 24)
1209 | ((zqoper & 0xF) << 16)
1210 | ((zqcs & 0xF) << 8)
1212 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1215 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1216 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1217 const memctl_options_t *popts)
1220 * First DQS pulse rising edge after margining mode
1221 * is programmed (tWL_MRD)
1223 unsigned int wrlvl_mrd = 0;
1224 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1225 unsigned int wrlvl_odten = 0;
1226 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1227 unsigned int wrlvl_dqsen = 0;
1228 /* WRLVL_SMPL: Write leveling sample time */
1229 unsigned int wrlvl_smpl = 0;
1230 /* WRLVL_WLR: Write leveling repeition time */
1231 unsigned int wrlvl_wlr = 0;
1232 /* WRLVL_START: Write leveling start time */
1233 unsigned int wrlvl_start = 0;
1235 /* suggest enable write leveling for DDR3 due to fly-by topology */
1237 /* tWL_MRD min = 40 nCK, we set it 64 */
1241 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1244 * Write leveling sample time at least need 6 clocks
1245 * higher than tWLO to allow enough time for progagation
1246 * delay and sampling the prime data bits.
1250 * Write leveling repetition time
1251 * at least tWLO + 6 clocks clocks
1256 * Write leveling start time
1257 * The value use for the DQS_ADJUST for the first sample
1258 * when write leveling is enabled. It probably needs to be
1259 * overriden per platform.
1263 * Override the write leveling sample and start time
1264 * according to specific board
1266 if (popts->wrlvl_override) {
1267 wrlvl_smpl = popts->wrlvl_sample;
1268 wrlvl_start = popts->wrlvl_start;
1272 ddr->ddr_wrlvl_cntl = (0
1273 | ((wrlvl_en & 0x1) << 31)
1274 | ((wrlvl_mrd & 0x7) << 24)
1275 | ((wrlvl_odten & 0x7) << 20)
1276 | ((wrlvl_dqsen & 0x7) << 16)
1277 | ((wrlvl_smpl & 0xf) << 12)
1278 | ((wrlvl_wlr & 0x7) << 8)
1279 | ((wrlvl_start & 0x1F) << 0)
1281 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1284 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1285 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1287 /* Self Refresh Idle Threshold */
1288 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1291 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1293 if (popts->addr_hash) {
1294 ddr->ddr_eor = 0x40000000; /* address hash enable */
1295 puts("Addess hashing enabled.\n");
1299 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1301 ddr->ddr_cdr1 = popts->ddr_cdr1;
1302 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1306 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1308 unsigned int res = 0;
1311 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1312 * not set at the same time.
1314 if (ddr->ddr_sdram_cfg & 0x10000000
1315 && ddr->ddr_sdram_cfg & 0x00008000) {
1316 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1317 " should not be set at the same time.\n");
1325 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1326 fsl_ddr_cfg_regs_t *ddr,
1327 const common_timing_params_t *common_dimm,
1328 const dimm_params_t *dimm_params,
1329 unsigned int dbw_cap_adj,
1330 unsigned int size_only)
1333 unsigned int cas_latency;
1334 unsigned int additive_latency;
1337 unsigned int wrlvl_en;
1338 unsigned int ip_rev = 0;
1339 unsigned int unq_mrs_en = 0;
1342 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1344 if (common_dimm == NULL) {
1345 printf("Error: subset DIMM params struct null pointer\n");
1350 * Process overrides first.
1352 * FIXME: somehow add dereated caslat to this
1354 cas_latency = (popts->cas_latency_override)
1355 ? popts->cas_latency_override_value
1356 : common_dimm->lowest_common_SPD_caslat;
1358 additive_latency = (popts->additive_latency_override)
1359 ? popts->additive_latency_override_value
1360 : common_dimm->additive_latency;
1362 sr_it = (popts->auto_self_refresh_en)
1365 /* ZQ calibration */
1366 zq_en = (popts->zq_en) ? 1 : 0;
1367 /* write leveling */
1368 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1370 /* Chip Select Memory Bounds (CSn_BNDS) */
1371 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1372 unsigned long long ea = 0, sa = 0;
1373 unsigned int cs_per_dimm
1374 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1375 unsigned int dimm_number
1377 unsigned long long rank_density
1378 = dimm_params[dimm_number].rank_density;
1380 if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) ||
1381 ((i == 2) && (popts->ba_intlv_ctl & 0x04)) ||
1382 ((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) {
1384 * Don't set up boundaries for unused CS
1385 * cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1386 * cs2 for cs0_cs1_cs2_cs3
1387 * cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1388 * But we need to set the ODT_RD_CFG and
1389 * ODT_WR_CFG for CS1_CONFIG here.
1391 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1394 if (dimm_params[dimm_number].n_ranks == 0) {
1395 debug("Skipping setup of CS%u "
1396 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1399 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
1401 * This works superbank 2CS
1402 * There are 2 or more memory controllers configured
1403 * identically, memory is interleaved between them,
1404 * and each controller uses rank interleaving within
1405 * itself. Therefore the starting and ending address
1406 * on each controller is twice the amount present on
1407 * each controller. If any CS is not included in the
1408 * interleaving, the memory on that CS is not accssible
1409 * and the total memory size is reduced. The CS is also
1412 unsigned long long ctlr_density = 0;
1413 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1414 case FSL_DDR_CS0_CS1:
1415 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1416 ctlr_density = dimm_params[0].rank_density * 2;
1420 case FSL_DDR_CS2_CS3:
1421 ctlr_density = dimm_params[0].rank_density;
1425 case FSL_DDR_CS0_CS1_CS2_CS3:
1427 * The four CS interleaving should have been verified by
1428 * populate_memctl_options()
1430 ctlr_density = dimm_params[0].rank_density * 4;
1435 ea = (CONFIG_NUM_DDR_CONTROLLERS *
1436 (ctlr_density >> dbw_cap_adj)) - 1;
1438 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
1440 * If memory interleaving between controllers is NOT
1441 * enabled, the starting address for each memory
1442 * controller is distinct. However, because rank
1443 * interleaving is enabled, the starting and ending
1444 * addresses of the total memory on that memory
1445 * controller needs to be programmed into its
1446 * respective CS0_BNDS.
1448 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1449 case FSL_DDR_CS0_CS1_CS2_CS3:
1450 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
1453 sa = common_dimm->base_address;
1454 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
1456 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1457 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
1458 * and CS2_CNDS need to be set.
1460 if ((i == 2) && (dimm_number == 0)) {
1461 sa = dimm_params[dimm_number].base_address +
1462 2 * (rank_density >> dbw_cap_adj);
1463 ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1;
1465 sa = dimm_params[dimm_number].base_address;
1466 ea = sa + (2 * (rank_density >>
1470 case FSL_DDR_CS0_CS1:
1471 /* CS0+CS1 interleaving, CS0_CNDS needs
1474 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1475 sa = dimm_params[dimm_number].base_address;
1476 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1477 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1478 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1484 ea += (rank_density >> dbw_cap_adj);
1486 case FSL_DDR_CS2_CS3:
1487 /* CS2+CS3 interleaving*/
1488 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1489 sa = dimm_params[dimm_number].base_address;
1490 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1491 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1492 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1498 ea += (rank_density >> dbw_cap_adj);
1500 default: /* No bank(chip-select) interleaving */
1504 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1506 * Only the rank on CS0 of each memory controller may
1507 * be used if memory controller interleaving is used
1508 * without rank interleaving within each memory
1509 * controller. However, the ending address programmed
1510 * into each CS0 must be the sum of the amount of
1511 * memory in the two CS0 ranks.
1514 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1518 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1520 * No rank interleaving and no memory controller
1523 sa = dimm_params[dimm_number].base_address;
1524 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1525 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1526 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1527 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1537 ddr->cs[i].bnds = (0
1538 | ((sa & 0xFFF) << 16) /* starting address MSB */
1539 | ((ea & 0xFFF) << 0) /* ending address MSB */
1542 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1544 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1545 set_csn_config_2(i, ddr);
1547 printf("CS%d is disabled.\n", i);
1551 * In the case we only need to compute the ddr sdram size, we only need
1552 * to set csn registers, so return from here.
1557 set_ddr_eor(ddr, popts);
1559 #if !defined(CONFIG_FSL_DDR1)
1560 set_timing_cfg_0(ddr, popts);
1563 set_timing_cfg_3(ddr, common_dimm, cas_latency);
1564 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1565 set_timing_cfg_2(ddr, popts, common_dimm,
1566 cas_latency, additive_latency);
1568 set_ddr_cdr1(ddr, popts);
1569 set_ddr_sdram_cfg(ddr, popts, common_dimm);
1570 ip_rev = fsl_ddr_get_version();
1571 if (ip_rev > 0x40400)
1574 set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1575 set_ddr_sdram_mode(ddr, popts, common_dimm,
1576 cas_latency, additive_latency, unq_mrs_en);
1577 set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
1578 set_ddr_sdram_interval(ddr, popts, common_dimm);
1579 set_ddr_data_init(ddr);
1580 set_ddr_sdram_clk_cntl(ddr, popts);
1581 set_ddr_init_addr(ddr);
1582 set_ddr_init_ext_addr(ddr);
1583 set_timing_cfg_4(ddr, popts);
1584 set_timing_cfg_5(ddr, cas_latency);
1586 set_ddr_zq_cntl(ddr, zq_en);
1587 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1589 set_ddr_sr_cntr(ddr, sr_it);
1591 set_ddr_sdram_rcw(ddr, popts, common_dimm);
1593 return check_fsl_memctl_config_regs(ddr);