git.sur5r.net Git - u-boot/blob - arch/powerpc/cpu/mpc8xxx/ddr/ddr.h

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #ifndef FSL_DDR_MAIN_H
  10 #define FSL_DDR_MAIN_H
  11
  12 #include <asm/fsl_ddr_sdram.h>
  13 #include <asm/fsl_ddr_dimm_params.h>
  14
  15 #include "common_timing_params.h"
  16
  17 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
  18 /*
  19  * Bind the main DDR setup driver's generic names
  20  * to this specific DDR technology.
  21  */
  22 static __inline__ int
  23 compute_dimm_parameters(const generic_spd_eeprom_t *spd,
  24                         dimm_params_t *pdimm,
  25                         unsigned int dimm_number)
  26 {
  27         return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
  28 }
  29 #endif
  30
  31 /*
  32  * Data Structures
  33  *
  34  * All data structures have to be on the stack
  35  */
  36 #define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
  37 #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
  38
  39 typedef struct {
  40         generic_spd_eeprom_t
  41            spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  42         struct dimm_params_s
  43            dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  44         memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
  45         common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
  46         fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
  47 } fsl_ddr_info_t;
  48
  49 /* Compute steps */
  50 #define STEP_GET_SPD                 (1 << 0)
  51 #define STEP_COMPUTE_DIMM_PARMS      (1 << 1)
  52 #define STEP_COMPUTE_COMMON_PARMS    (1 << 2)
  53 #define STEP_GATHER_OPTS             (1 << 3)
  54 #define STEP_ASSIGN_ADDRESSES        (1 << 4)
  55 #define STEP_COMPUTE_REGS            (1 << 5)
  56 #define STEP_PROGRAM_REGS            (1 << 6)
  57 #define STEP_ALL                     0xFFF
  58
  59 extern unsigned long long
  60 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
  61                                        unsigned int size_only);
  62
  63 extern const char * step_to_string(unsigned int step);
  64
  65 extern unsigned int
  66 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
  67                                fsl_ddr_cfg_regs_t *ddr,
  68                                const common_timing_params_t *common_dimm,
  69                                const dimm_params_t *dimm_parameters,
  70                                unsigned int dbw_capacity_adjust,
  71                                unsigned int size_only);
  72 extern unsigned int
  73 compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
  74                                       common_timing_params_t *outpdimm,
  75                                       unsigned int number_of_dimms);
  76 extern unsigned int populate_memctl_options(int all_DIMMs_registered,
  77                                 memctl_options_t *popts,
  78                                 dimm_params_t *pdimm,
  79                                 unsigned int ctrl_num);
  80 extern void check_interleaving_options(fsl_ddr_info_t *pinfo);
  81
  82 extern unsigned int mclk_to_picos(unsigned int mclk);
  83 extern unsigned int get_memory_clk_period_ps(void);
  84 extern unsigned int picos_to_mclk(unsigned int picos);
  85
  86 /* board specific function */
  87 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  88                         unsigned int controller_number,
  89                         unsigned int dimm_number);
  90 #endif