2 * Copyright 2010-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 or any later versionas published by the Free Software Foundation.
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
13 * York Sun [at freescale.com]
17 #include <linux/ctype.h>
18 #include <asm/types.h>
20 #include <asm/fsl_ddr_sdram.h>
23 /* Option parameter Structures */
24 struct options_string {
25 const char *option_name;
31 static unsigned int picos_to_mhz(unsigned int picos)
33 return 1000000 / picos;
36 static void print_option_table(const struct options_string *table,
42 unsigned long long *ptr_l;
44 for (i = 0; i < table_size; i++) {
45 switch (table[i].size) {
47 ptr = (unsigned int *) (base + table[i].offset);
48 if (table[i].printhex) {
49 printf("%s = 0x%08X\n",
50 table[i].option_name, *ptr);
53 table[i].option_name, *ptr);
57 ptr_l = (unsigned long long *) (base + table[i].offset);
59 table[i].option_name, *ptr_l);
62 printf("Unrecognized size!\n");
68 static int handle_option_table(const struct options_string *table,
75 unsigned int value, *ptr;
76 unsigned long long value_l, *ptr_l;
78 for (i = 0; i < table_size; i++) {
79 if (strcmp(table[i].option_name, opt) != 0)
81 switch (table[i].size) {
83 value = simple_strtoul(val, NULL, 0);
84 ptr = base + table[i].offset;
88 value_l = simple_strtoull(val, NULL, 0);
89 ptr_l = base + table[i].offset;
93 printf("Unrecognized size!\n");
102 static void fsl_ddr_generic_edit(void *pdata,
104 unsigned int element_size,
105 unsigned int element_num,
108 char *pcdata = (char *)pdata; /* BIG ENDIAN ONLY */
110 pcdata += element_num * element_size;
111 if ((pcdata + element_size) > (char *) pend) {
112 printf("trying to write past end of data\n");
116 switch (element_size) {
118 __raw_writeb(value, pcdata);
121 __raw_writew(value, pcdata);
124 __raw_writel(value, pcdata);
127 printf("unexpected element size %u\n", element_size);
132 static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
133 unsigned int ctrl_num,
134 unsigned int dimm_num,
135 unsigned int element_num,
138 generic_spd_eeprom_t *pspd;
140 pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
141 fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
144 #define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
145 sizeof((common_timing_params_t *)0)->x, 0}
147 static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
148 unsigned int ctrl_num,
149 const char *optname_str,
150 const char *value_str)
152 common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
154 static const struct options_string options[] = {
155 COMMON_TIMING(tCKmin_X_ps),
156 COMMON_TIMING(tCKmax_ps),
157 COMMON_TIMING(tCKmax_max_ps),
158 COMMON_TIMING(tRCD_ps),
159 COMMON_TIMING(tRP_ps),
160 COMMON_TIMING(tRAS_ps),
161 COMMON_TIMING(tWR_ps),
162 COMMON_TIMING(tWTR_ps),
163 COMMON_TIMING(tRFC_ps),
164 COMMON_TIMING(tRRD_ps),
165 COMMON_TIMING(tRC_ps),
166 COMMON_TIMING(refresh_rate_ps),
167 COMMON_TIMING(tIS_ps),
168 COMMON_TIMING(tIH_ps),
169 COMMON_TIMING(tDS_ps),
170 COMMON_TIMING(tDH_ps),
171 COMMON_TIMING(tRTP_ps),
172 COMMON_TIMING(tDQSQ_max_ps),
173 COMMON_TIMING(tQHS_ps),
174 COMMON_TIMING(ndimms_present),
175 COMMON_TIMING(lowest_common_SPD_caslat),
176 COMMON_TIMING(highest_common_derated_caslat),
177 COMMON_TIMING(additive_latency),
178 COMMON_TIMING(all_DIMMs_burst_lengths_bitmask),
179 COMMON_TIMING(all_DIMMs_registered),
180 COMMON_TIMING(all_DIMMs_unbuffered),
181 COMMON_TIMING(all_DIMMs_ECC_capable),
182 COMMON_TIMING(total_mem),
183 COMMON_TIMING(base_address),
185 static const unsigned int n_opts = ARRAY_SIZE(options);
187 if (handle_option_table(options, n_opts, p, optname_str, value_str))
190 printf("Error: couldn't find option string %s\n", optname_str);
193 #define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
194 sizeof((dimm_params_t *)0)->x, 0}
196 static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
197 unsigned int ctrl_num,
198 unsigned int dimm_num,
199 const char *optname_str,
200 const char *value_str)
202 dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
204 static const struct options_string options[] = {
206 DIMM_PARM(data_width),
207 DIMM_PARM(primary_sdram_width),
208 DIMM_PARM(ec_sdram_width),
209 DIMM_PARM(registered_dimm),
211 DIMM_PARM(n_row_addr),
212 DIMM_PARM(n_col_addr),
213 DIMM_PARM(edc_config),
214 DIMM_PARM(n_banks_per_sdram_device),
215 DIMM_PARM(burst_lengths_bitmask),
216 DIMM_PARM(row_density),
218 DIMM_PARM(tCKmin_X_ps),
219 DIMM_PARM(tCKmin_X_minus_1_ps),
220 DIMM_PARM(tCKmin_X_minus_2_ps),
221 DIMM_PARM(tCKmax_ps),
224 DIMM_PARM(caslat_X_minus_1),
225 DIMM_PARM(caslat_X_minus_2),
227 DIMM_PARM(caslat_lowest_derated),
237 DIMM_PARM(refresh_rate_ps),
244 DIMM_PARM(tDQSQ_max_ps),
247 DIMM_PARM(rank_density),
249 DIMM_PARM(base_address),
252 static const unsigned int n_opts = ARRAY_SIZE(options);
254 if (handle_option_table(options, n_opts, p, optname_str, value_str))
257 printf("couldn't find option string %s\n", optname_str);
260 static void print_dimm_parameters(const dimm_params_t *pdimm)
262 static const struct options_string options[] = {
264 DIMM_PARM(data_width),
265 DIMM_PARM(primary_sdram_width),
266 DIMM_PARM(ec_sdram_width),
267 DIMM_PARM(registered_dimm),
269 DIMM_PARM(n_row_addr),
270 DIMM_PARM(n_col_addr),
271 DIMM_PARM(edc_config),
272 DIMM_PARM(n_banks_per_sdram_device),
274 DIMM_PARM(tCKmin_X_ps),
275 DIMM_PARM(tCKmin_X_minus_1_ps),
276 DIMM_PARM(tCKmin_X_minus_2_ps),
277 DIMM_PARM(tCKmax_ps),
281 DIMM_PARM(caslat_X_minus_1),
282 DIMM_PARM(caslat_X_minus_2),
283 DIMM_PARM(caslat_lowest_derated),
293 DIMM_PARM(refresh_rate_ps),
300 DIMM_PARM(tDQSQ_max_ps),
303 static const unsigned int n_opts = ARRAY_SIZE(options);
305 if (pdimm->n_ranks == 0) {
306 printf("DIMM not present\n");
309 printf("DIMM organization parameters:\n");
310 printf("module part name = %s\n", pdimm->mpart);
311 printf("rank_density = %llu bytes (%llu megabytes)\n",
312 pdimm->rank_density, pdimm->rank_density / 0x100000);
313 printf("capacity = %llu bytes (%llu megabytes)\n",
314 pdimm->capacity, pdimm->capacity / 0x100000);
315 printf("burst_lengths_bitmask = %02X\n",
316 pdimm->burst_lengths_bitmask);
317 printf("base_addresss = %llu (%08llX %08llX)\n",
319 (pdimm->base_address >> 32),
320 pdimm->base_address & 0xFFFFFFFF);
321 print_option_table(options, n_opts, pdimm);
324 static void print_lowest_common_dimm_parameters(
325 const common_timing_params_t *plcd_dimm_params)
327 static const struct options_string options[] = {
328 COMMON_TIMING(tCKmax_max_ps),
329 COMMON_TIMING(tRCD_ps),
330 COMMON_TIMING(tRP_ps),
331 COMMON_TIMING(tRAS_ps),
332 COMMON_TIMING(tWR_ps),
333 COMMON_TIMING(tWTR_ps),
334 COMMON_TIMING(tRFC_ps),
335 COMMON_TIMING(tRRD_ps),
336 COMMON_TIMING(tRC_ps),
337 COMMON_TIMING(refresh_rate_ps),
338 COMMON_TIMING(tIS_ps),
339 COMMON_TIMING(tDS_ps),
340 COMMON_TIMING(tDH_ps),
341 COMMON_TIMING(tRTP_ps),
342 COMMON_TIMING(tDQSQ_max_ps),
343 COMMON_TIMING(tQHS_ps),
344 COMMON_TIMING(lowest_common_SPD_caslat),
345 COMMON_TIMING(highest_common_derated_caslat),
346 COMMON_TIMING(additive_latency),
347 COMMON_TIMING(ndimms_present),
348 COMMON_TIMING(all_DIMMs_registered),
349 COMMON_TIMING(all_DIMMs_unbuffered),
350 COMMON_TIMING(all_DIMMs_ECC_capable),
352 static const unsigned int n_opts = ARRAY_SIZE(options);
354 /* Clock frequencies */
355 printf("tCKmin_X_ps = %u (%u MHz)\n",
356 plcd_dimm_params->tCKmin_X_ps,
357 picos_to_mhz(plcd_dimm_params->tCKmin_X_ps));
358 printf("tCKmax_ps = %u (%u MHz)\n",
359 plcd_dimm_params->tCKmax_ps,
360 picos_to_mhz(plcd_dimm_params->tCKmax_ps));
361 printf("all_DIMMs_burst_lengths_bitmask = %02X\n",
362 plcd_dimm_params->all_DIMMs_burst_lengths_bitmask);
364 print_option_table(options, n_opts, plcd_dimm_params);
366 printf("total_mem = %llu (%llu megabytes)\n",
367 plcd_dimm_params->total_mem,
368 plcd_dimm_params->total_mem / 0x100000);
369 printf("base_address = %llu (%llu megabytes)\n",
370 plcd_dimm_params->base_address,
371 plcd_dimm_params->base_address / 0x100000);
374 #define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
375 sizeof((memctl_options_t *)0)->x, 0}
376 #define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
377 offsetof(memctl_options_t, cs_local_opts[x].y), \
378 sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
380 static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
381 unsigned int ctl_num,
382 const char *optname_str,
383 const char *value_str)
385 memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
387 * This array all on the stack and *computed* each time this
390 static const struct options_string options[] = {
391 CTRL_OPTIONS_CS(0, odt_rd_cfg),
392 CTRL_OPTIONS_CS(0, odt_wr_cfg),
393 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
394 CTRL_OPTIONS_CS(1, odt_rd_cfg),
395 CTRL_OPTIONS_CS(1, odt_wr_cfg),
397 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
398 CTRL_OPTIONS_CS(2, odt_rd_cfg),
399 CTRL_OPTIONS_CS(2, odt_wr_cfg),
401 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
402 CTRL_OPTIONS_CS(3, odt_rd_cfg),
403 CTRL_OPTIONS_CS(3, odt_wr_cfg),
405 #if defined(CONFIG_FSL_DDR3)
406 CTRL_OPTIONS_CS(0, odt_rtt_norm),
407 CTRL_OPTIONS_CS(0, odt_rtt_wr),
408 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
409 CTRL_OPTIONS_CS(1, odt_rtt_norm),
410 CTRL_OPTIONS_CS(1, odt_rtt_wr),
412 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
413 CTRL_OPTIONS_CS(2, odt_rtt_norm),
414 CTRL_OPTIONS_CS(2, odt_rtt_wr),
416 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
417 CTRL_OPTIONS_CS(3, odt_rtt_norm),
418 CTRL_OPTIONS_CS(3, odt_rtt_wr),
421 CTRL_OPTIONS(memctl_interleaving),
422 CTRL_OPTIONS(memctl_interleaving_mode),
423 CTRL_OPTIONS(ba_intlv_ctl),
424 CTRL_OPTIONS(ECC_mode),
425 CTRL_OPTIONS(ECC_init_using_memctl),
426 CTRL_OPTIONS(DQS_config),
427 CTRL_OPTIONS(self_refresh_in_sleep),
428 CTRL_OPTIONS(dynamic_power),
429 CTRL_OPTIONS(data_bus_width),
430 CTRL_OPTIONS(burst_length),
431 CTRL_OPTIONS(cas_latency_override),
432 CTRL_OPTIONS(cas_latency_override_value),
433 CTRL_OPTIONS(use_derated_caslat),
434 CTRL_OPTIONS(additive_latency_override),
435 CTRL_OPTIONS(additive_latency_override_value),
436 CTRL_OPTIONS(clk_adjust),
437 CTRL_OPTIONS(cpo_override),
438 CTRL_OPTIONS(write_data_delay),
439 CTRL_OPTIONS(half_strength_driver_enable),
442 * These can probably be changed to 2T_EN and 3T_EN
443 * (using a leading numerical character) without problem
445 CTRL_OPTIONS(twoT_en),
446 CTRL_OPTIONS(threeT_en),
448 CTRL_OPTIONS(bstopre),
449 CTRL_OPTIONS(wrlvl_override),
450 CTRL_OPTIONS(wrlvl_sample),
451 CTRL_OPTIONS(wrlvl_start),
452 CTRL_OPTIONS(rcw_override),
455 CTRL_OPTIONS(ddr_cdr1),
456 CTRL_OPTIONS(ddr_cdr2),
457 CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
458 CTRL_OPTIONS(tFAW_window_four_activates_ps),
459 CTRL_OPTIONS(trwt_override),
463 static const unsigned int n_opts = ARRAY_SIZE(options);
465 if (handle_option_table(options, n_opts, p,
466 optname_str, value_str))
469 printf("couldn't find option string %s\n", optname_str);
472 #define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
473 sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
474 #define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
475 offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
476 sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
478 static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
481 static const struct options_string options[] = {
482 CFG_REGS_CS(0, bnds),
483 CFG_REGS_CS(0, config),
484 CFG_REGS_CS(0, config_2),
485 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
486 CFG_REGS_CS(1, bnds),
487 CFG_REGS_CS(1, config),
488 CFG_REGS_CS(1, config_2),
490 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
491 CFG_REGS_CS(2, bnds),
492 CFG_REGS_CS(2, config),
493 CFG_REGS_CS(2, config_2),
495 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
496 CFG_REGS_CS(3, bnds),
497 CFG_REGS_CS(3, config),
498 CFG_REGS_CS(3, config_2),
500 CFG_REGS(timing_cfg_3),
501 CFG_REGS(timing_cfg_0),
502 CFG_REGS(timing_cfg_1),
503 CFG_REGS(timing_cfg_2),
504 CFG_REGS(ddr_sdram_cfg),
505 CFG_REGS(ddr_sdram_cfg_2),
506 CFG_REGS(ddr_sdram_mode),
507 CFG_REGS(ddr_sdram_mode_2),
508 CFG_REGS(ddr_sdram_mode_3),
509 CFG_REGS(ddr_sdram_mode_4),
510 CFG_REGS(ddr_sdram_mode_5),
511 CFG_REGS(ddr_sdram_mode_6),
512 CFG_REGS(ddr_sdram_mode_7),
513 CFG_REGS(ddr_sdram_mode_8),
514 CFG_REGS(ddr_sdram_interval),
515 CFG_REGS(ddr_data_init),
516 CFG_REGS(ddr_sdram_clk_cntl),
517 CFG_REGS(ddr_init_addr),
518 CFG_REGS(ddr_init_ext_addr),
519 CFG_REGS(timing_cfg_4),
520 CFG_REGS(timing_cfg_5),
521 CFG_REGS(ddr_zq_cntl),
522 CFG_REGS(ddr_wrlvl_cntl),
523 CFG_REGS(ddr_wrlvl_cntl_2),
524 CFG_REGS(ddr_wrlvl_cntl_3),
525 CFG_REGS(ddr_sr_cntr),
526 CFG_REGS(ddr_sdram_rcw_1),
527 CFG_REGS(ddr_sdram_rcw_2),
530 CFG_REGS(err_disable),
531 CFG_REGS(err_int_en),
534 static const unsigned int n_opts = ARRAY_SIZE(options);
536 print_option_table(options, n_opts, ddr);
538 for (i = 0; i < 32; i++)
539 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
542 static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
543 unsigned int ctrl_num,
545 const char *value_str)
548 fsl_ddr_cfg_regs_t *ddr;
550 static const struct options_string options[] = {
551 CFG_REGS_CS(0, bnds),
552 CFG_REGS_CS(0, config),
553 CFG_REGS_CS(0, config_2),
554 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
555 CFG_REGS_CS(1, bnds),
556 CFG_REGS_CS(1, config),
557 CFG_REGS_CS(1, config_2),
559 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
560 CFG_REGS_CS(2, bnds),
561 CFG_REGS_CS(2, config),
562 CFG_REGS_CS(2, config_2),
564 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
565 CFG_REGS_CS(3, bnds),
566 CFG_REGS_CS(3, config),
567 CFG_REGS_CS(3, config_2),
569 CFG_REGS(timing_cfg_3),
570 CFG_REGS(timing_cfg_0),
571 CFG_REGS(timing_cfg_1),
572 CFG_REGS(timing_cfg_2),
573 CFG_REGS(ddr_sdram_cfg),
574 CFG_REGS(ddr_sdram_cfg_2),
575 CFG_REGS(ddr_sdram_mode),
576 CFG_REGS(ddr_sdram_mode_2),
577 CFG_REGS(ddr_sdram_mode_3),
578 CFG_REGS(ddr_sdram_mode_4),
579 CFG_REGS(ddr_sdram_mode_5),
580 CFG_REGS(ddr_sdram_mode_6),
581 CFG_REGS(ddr_sdram_mode_7),
582 CFG_REGS(ddr_sdram_mode_8),
583 CFG_REGS(ddr_sdram_interval),
584 CFG_REGS(ddr_data_init),
585 CFG_REGS(ddr_sdram_clk_cntl),
586 CFG_REGS(ddr_init_addr),
587 CFG_REGS(ddr_init_ext_addr),
588 CFG_REGS(timing_cfg_4),
589 CFG_REGS(timing_cfg_5),
590 CFG_REGS(ddr_zq_cntl),
591 CFG_REGS(ddr_wrlvl_cntl),
592 CFG_REGS(ddr_wrlvl_cntl_2),
593 CFG_REGS(ddr_wrlvl_cntl_3),
594 CFG_REGS(ddr_sr_cntr),
595 CFG_REGS(ddr_sdram_rcw_1),
596 CFG_REGS(ddr_sdram_rcw_2),
599 CFG_REGS(err_disable),
600 CFG_REGS(err_int_en),
601 CFG_REGS(ddr_sdram_rcw_2),
602 CFG_REGS(ddr_sdram_rcw_2),
605 static const unsigned int n_opts = ARRAY_SIZE(options);
607 debug("fsl_ddr_regs_edit: ctrl_num = %u, "
608 "regname = %s, value = %s\n",
609 ctrl_num, regname, value_str);
610 if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
613 ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
615 if (handle_option_table(options, n_opts, ddr, regname, value_str))
618 for (i = 0; i < 32; i++) {
619 unsigned int value = simple_strtoul(value_str, NULL, 0);
620 sprintf(buf, "debug_%u", i + 1);
621 if (strcmp(buf, regname) == 0) {
622 ddr->debug[i] = value;
626 printf("Error: couldn't find register string %s\n", regname);
629 #define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
630 sizeof((memctl_options_t *)0)->x, 1}
632 static void print_memctl_options(const memctl_options_t *popts)
634 static const struct options_string options[] = {
635 CTRL_OPTIONS_CS(0, odt_rd_cfg),
636 CTRL_OPTIONS_CS(0, odt_wr_cfg),
637 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
638 CTRL_OPTIONS_CS(1, odt_rd_cfg),
639 CTRL_OPTIONS_CS(1, odt_wr_cfg),
641 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
642 CTRL_OPTIONS_CS(2, odt_rd_cfg),
643 CTRL_OPTIONS_CS(2, odt_wr_cfg),
645 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
646 CTRL_OPTIONS_CS(3, odt_rd_cfg),
647 CTRL_OPTIONS_CS(3, odt_wr_cfg),
649 #if defined(CONFIG_FSL_DDR3)
650 CTRL_OPTIONS_CS(0, odt_rtt_norm),
651 CTRL_OPTIONS_CS(0, odt_rtt_wr),
652 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
653 CTRL_OPTIONS_CS(1, odt_rtt_norm),
654 CTRL_OPTIONS_CS(1, odt_rtt_wr),
656 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
657 CTRL_OPTIONS_CS(2, odt_rtt_norm),
658 CTRL_OPTIONS_CS(2, odt_rtt_wr),
660 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
661 CTRL_OPTIONS_CS(3, odt_rtt_norm),
662 CTRL_OPTIONS_CS(3, odt_rtt_wr),
665 CTRL_OPTIONS(memctl_interleaving),
666 CTRL_OPTIONS(memctl_interleaving_mode),
667 CTRL_OPTIONS_HEX(ba_intlv_ctl),
668 CTRL_OPTIONS(ECC_mode),
669 CTRL_OPTIONS(ECC_init_using_memctl),
670 CTRL_OPTIONS(DQS_config),
671 CTRL_OPTIONS(self_refresh_in_sleep),
672 CTRL_OPTIONS(dynamic_power),
673 CTRL_OPTIONS(data_bus_width),
674 CTRL_OPTIONS(burst_length),
675 CTRL_OPTIONS(cas_latency_override),
676 CTRL_OPTIONS(cas_latency_override_value),
677 CTRL_OPTIONS(use_derated_caslat),
678 CTRL_OPTIONS(additive_latency_override),
679 CTRL_OPTIONS(additive_latency_override_value),
680 CTRL_OPTIONS(clk_adjust),
681 CTRL_OPTIONS(cpo_override),
682 CTRL_OPTIONS(write_data_delay),
683 CTRL_OPTIONS(half_strength_driver_enable),
685 * These can probably be changed to 2T_EN and 3T_EN
686 * (using a leading numerical character) without problem
688 CTRL_OPTIONS(twoT_en),
689 CTRL_OPTIONS(threeT_en),
690 CTRL_OPTIONS(registered_dimm_en),
692 CTRL_OPTIONS(bstopre),
693 CTRL_OPTIONS(wrlvl_override),
694 CTRL_OPTIONS(wrlvl_sample),
695 CTRL_OPTIONS(wrlvl_start),
696 CTRL_OPTIONS(rcw_override),
699 CTRL_OPTIONS_HEX(ddr_cdr1),
700 CTRL_OPTIONS_HEX(ddr_cdr2),
701 CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
702 CTRL_OPTIONS(tFAW_window_four_activates_ps),
703 CTRL_OPTIONS(trwt_override),
706 static const unsigned int n_opts = ARRAY_SIZE(options);
708 print_option_table(options, n_opts, popts);
711 #ifdef CONFIG_FSL_DDR1
712 void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
716 printf("%-3d : %02x %s\n", 0, spd->info_size,
717 " spd->info_size, * 0 # bytes written into serial memory *");
718 printf("%-3d : %02x %s\n", 1, spd->chip_size,
719 " spd->chip_size, * 1 Total # bytes of SPD memory device *");
720 printf("%-3d : %02x %s\n", 2, spd->mem_type,
721 " spd->mem_type, * 2 Fundamental memory type *");
722 printf("%-3d : %02x %s\n", 3, spd->nrow_addr,
723 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *");
724 printf("%-3d : %02x %s\n", 4, spd->ncol_addr,
725 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *");
726 printf("%-3d : %02x %s\n", 5, spd->nrows,
727 " spd->nrows * 5 # of DIMM Banks *");
728 printf("%-3d : %02x %s\n", 6, spd->dataw_lsb,
729 " spd->dataw_lsb, * 6 Data Width lsb of this assembly *");
730 printf("%-3d : %02x %s\n", 7, spd->dataw_msb,
731 " spd->dataw_msb, * 7 Data Width msb of this assembly *");
732 printf("%-3d : %02x %s\n", 8, spd->voltage,
733 " spd->voltage, * 8 Voltage intf std of this assembly *");
734 printf("%-3d : %02x %s\n", 9, spd->clk_cycle,
735 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *");
736 printf("%-3d : %02x %s\n", 10, spd->clk_access,
737 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *");
738 printf("%-3d : %02x %s\n", 11, spd->config,
739 " spd->config, * 11 DIMM Configuration type *");
740 printf("%-3d : %02x %s\n", 12, spd->refresh,
741 " spd->refresh, * 12 Refresh Rate/Type *");
742 printf("%-3d : %02x %s\n", 13, spd->primw,
743 " spd->primw, * 13 Primary SDRAM Width *");
744 printf("%-3d : %02x %s\n", 14, spd->ecw,
745 " spd->ecw, * 14 Error Checking SDRAM width *");
746 printf("%-3d : %02x %s\n", 15, spd->min_delay,
747 " spd->min_delay, * 15 Back to Back Random Access *");
748 printf("%-3d : %02x %s\n", 16, spd->burstl,
749 " spd->burstl, * 16 Burst Lengths Supported *");
750 printf("%-3d : %02x %s\n", 17, spd->nbanks,
751 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *");
752 printf("%-3d : %02x %s\n", 18, spd->cas_lat,
753 " spd->cas_lat, * 18 CAS# Latencies Supported *");
754 printf("%-3d : %02x %s\n", 19, spd->cs_lat,
755 " spd->cs_lat, * 19 Chip Select Latency *");
756 printf("%-3d : %02x %s\n", 20, spd->write_lat,
757 " spd->write_lat, * 20 Write Latency/Recovery *");
758 printf("%-3d : %02x %s\n", 21, spd->mod_attr,
759 " spd->mod_attr, * 21 SDRAM Module Attributes *");
760 printf("%-3d : %02x %s\n", 22, spd->dev_attr,
761 " spd->dev_attr, * 22 SDRAM Device Attributes *");
762 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2,
763 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *");
764 printf("%-3d : %02x %s\n", 24, spd->clk_access2,
765 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
766 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3,
767 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *");
768 printf("%-3d : %02x %s\n", 26, spd->clk_access3,
769 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
770 printf("%-3d : %02x %s\n", 27, spd->trp,
771 " spd->trp, * 27 Min Row Precharge Time (tRP)*");
772 printf("%-3d : %02x %s\n", 28, spd->trrd,
773 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *");
774 printf("%-3d : %02x %s\n", 29, spd->trcd,
775 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *");
776 printf("%-3d : %02x %s\n", 30, spd->tras,
777 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *");
778 printf("%-3d : %02x %s\n", 31, spd->bank_dens,
779 " spd->bank_dens, * 31 Density of each bank on module *");
780 printf("%-3d : %02x %s\n", 32, spd->ca_setup,
781 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *");
782 printf("%-3d : %02x %s\n", 33, spd->ca_hold,
783 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *");
784 printf("%-3d : %02x %s\n", 34, spd->data_setup,
785 " spd->data_setup, * 34 Data signal input setup time *");
786 printf("%-3d : %02x %s\n", 35, spd->data_hold,
787 " spd->data_hold, * 35 Data signal input hold time *");
788 printf("%-3d : %02x %s\n", 36, spd->res_36_40[0],
789 " spd->res_36_40[0], * 36 Reserved / tWR *");
790 printf("%-3d : %02x %s\n", 37, spd->res_36_40[1],
791 " spd->res_36_40[1], * 37 Reserved / tWTR *");
792 printf("%-3d : %02x %s\n", 38, spd->res_36_40[2],
793 " spd->res_36_40[2], * 38 Reserved / tRTP *");
794 printf("%-3d : %02x %s\n", 39, spd->res_36_40[3],
795 " spd->res_36_40[3], * 39 Reserved / mem_probe *");
796 printf("%-3d : %02x %s\n", 40, spd->res_36_40[4],
797 " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
798 printf("%-3d : %02x %s\n", 41, spd->trc,
799 " spd->trc, * 41 Min Active to Auto refresh time tRC *");
800 printf("%-3d : %02x %s\n", 42, spd->trfc,
801 " spd->trfc, * 42 Min Auto to Active period tRFC *");
802 printf("%-3d : %02x %s\n", 43, spd->tckmax,
803 " spd->tckmax, * 43 Max device cycle time tCKmax *");
804 printf("%-3d : %02x %s\n", 44, spd->tdqsq,
805 " spd->tdqsq, * 44 Max DQS to DQ skew *");
806 printf("%-3d : %02x %s\n", 45, spd->tqhs,
807 " spd->tqhs, * 45 Max Read DataHold skew tQHS *");
808 printf("%-3d : %02x %s\n", 46, spd->res_46,
809 " spd->res_46, * 46 Reserved/ PLL Relock time *");
810 printf("%-3d : %02x %s\n", 47, spd->dimm_height,
811 " spd->dimm_height * 47 SDRAM DIMM Height *");
813 printf("%-3d-%3d: ", 48, 61);
815 for (i = 0; i < 14; i++)
816 printf("%02x", spd->res_48_61[i]);
818 printf(" * 48-61 IDD in SPD and Reserved space *\n");
820 printf("%-3d : %02x %s\n", 62, spd->spd_rev,
821 " spd->spd_rev, * 62 SPD Data Revision Code *");
822 printf("%-3d : %02x %s\n", 63, spd->cksum,
823 " spd->cksum, * 63 Checksum for bytes 0-62 *");
824 printf("%-3d-%3d: ", 64, 71);
826 for (i = 0; i < 8; i++)
827 printf("%02x", spd->mid[i]);
829 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
830 printf("%-3d : %02x %s\n", 72, spd->mloc,
831 " spd->mloc, * 72 Manufacturing Location *");
833 printf("%-3d-%3d: >>", 73, 90);
835 for (i = 0; i < 18; i++)
836 printf("%c", spd->mpart[i]);
838 printf("<<* 73 Manufacturer's Part Number *\n");
840 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
841 "* 91 Revision Code *");
842 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
843 "* 93 Manufacturing Date *");
844 printf("%-3d-%3d: ", 95, 98);
846 for (i = 0; i < 4; i++)
847 printf("%02x", spd->sernum[i]);
849 printf("* 95 Assembly Serial Number *\n");
851 printf("%-3d-%3d: ", 99, 127);
853 for (i = 0; i < 27; i++)
854 printf("%02x", spd->mspec[i]);
856 printf("* 99 Manufacturer Specific Data *\n");
860 #ifdef CONFIG_FSL_DDR2
861 void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
865 printf("%-3d : %02x %s\n", 0, spd->info_size,
866 " spd->info_size, * 0 # bytes written into serial memory *");
867 printf("%-3d : %02x %s\n", 1, spd->chip_size,
868 " spd->chip_size, * 1 Total # bytes of SPD memory device *");
869 printf("%-3d : %02x %s\n", 2, spd->mem_type,
870 " spd->mem_type, * 2 Fundamental memory type *");
871 printf("%-3d : %02x %s\n", 3, spd->nrow_addr,
872 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *");
873 printf("%-3d : %02x %s\n", 4, spd->ncol_addr,
874 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *");
875 printf("%-3d : %02x %s\n", 5, spd->mod_ranks,
876 " spd->mod_ranks * 5 # of Module Rows on this assembly *");
877 printf("%-3d : %02x %s\n", 6, spd->dataw,
878 " spd->dataw, * 6 Data Width of this assembly *");
879 printf("%-3d : %02x %s\n", 7, spd->res_7,
880 " spd->res_7, * 7 Reserved *");
881 printf("%-3d : %02x %s\n", 8, spd->voltage,
882 " spd->voltage, * 8 Voltage intf std of this assembly *");
883 printf("%-3d : %02x %s\n", 9, spd->clk_cycle,
884 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *");
885 printf("%-3d : %02x %s\n", 10, spd->clk_access,
886 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *");
887 printf("%-3d : %02x %s\n", 11, spd->config,
888 " spd->config, * 11 DIMM Configuration type *");
889 printf("%-3d : %02x %s\n", 12, spd->refresh,
890 " spd->refresh, * 12 Refresh Rate/Type *");
891 printf("%-3d : %02x %s\n", 13, spd->primw,
892 " spd->primw, * 13 Primary SDRAM Width *");
893 printf("%-3d : %02x %s\n", 14, spd->ecw,
894 " spd->ecw, * 14 Error Checking SDRAM width *");
895 printf("%-3d : %02x %s\n", 15, spd->res_15,
896 " spd->res_15, * 15 Reserved *");
897 printf("%-3d : %02x %s\n", 16, spd->burstl,
898 " spd->burstl, * 16 Burst Lengths Supported *");
899 printf("%-3d : %02x %s\n", 17, spd->nbanks,
900 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *");
901 printf("%-3d : %02x %s\n", 18, spd->cas_lat,
902 " spd->cas_lat, * 18 CAS# Latencies Supported *");
903 printf("%-3d : %02x %s\n", 19, spd->mech_char,
904 " spd->mech_char, * 19 Mechanical Characteristics *");
905 printf("%-3d : %02x %s\n", 20, spd->dimm_type,
906 " spd->dimm_type, * 20 DIMM type *");
907 printf("%-3d : %02x %s\n", 21, spd->mod_attr,
908 " spd->mod_attr, * 21 SDRAM Module Attributes *");
909 printf("%-3d : %02x %s\n", 22, spd->dev_attr,
910 " spd->dev_attr, * 22 SDRAM Device Attributes *");
911 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2,
912 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *");
913 printf("%-3d : %02x %s\n", 24, spd->clk_access2,
914 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
915 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3,
916 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *");
917 printf("%-3d : %02x %s\n", 26, spd->clk_access3,
918 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
919 printf("%-3d : %02x %s\n", 27, spd->trp,
920 " spd->trp, * 27 Min Row Precharge Time (tRP)*");
921 printf("%-3d : %02x %s\n", 28, spd->trrd,
922 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *");
923 printf("%-3d : %02x %s\n", 29, spd->trcd,
924 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *");
925 printf("%-3d : %02x %s\n", 30, spd->tras,
926 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *");
927 printf("%-3d : %02x %s\n", 31, spd->rank_dens,
928 " spd->rank_dens, * 31 Density of each rank on module *");
929 printf("%-3d : %02x %s\n", 32, spd->ca_setup,
930 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *");
931 printf("%-3d : %02x %s\n", 33, spd->ca_hold,
932 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *");
933 printf("%-3d : %02x %s\n", 34, spd->data_setup,
934 " spd->data_setup, * 34 Data signal input setup time *");
935 printf("%-3d : %02x %s\n", 35, spd->data_hold,
936 " spd->data_hold, * 35 Data signal input hold time *");
937 printf("%-3d : %02x %s\n", 36, spd->twr,
938 " spd->twr, * 36 Write Recovery time tWR *");
939 printf("%-3d : %02x %s\n", 37, spd->twtr,
940 " spd->twtr, * 37 Int write to read delay tWTR *");
941 printf("%-3d : %02x %s\n", 38, spd->trtp,
942 " spd->trtp, * 38 Int read to precharge delay tRTP *");
943 printf("%-3d : %02x %s\n", 39, spd->mem_probe,
944 " spd->mem_probe, * 39 Mem analysis probe characteristics *");
945 printf("%-3d : %02x %s\n", 40, spd->trctrfc_ext,
946 " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
947 printf("%-3d : %02x %s\n", 41, spd->trc,
948 " spd->trc, * 41 Min Active to Auto refresh time tRC *");
949 printf("%-3d : %02x %s\n", 42, spd->trfc,
950 " spd->trfc, * 42 Min Auto to Active period tRFC *");
951 printf("%-3d : %02x %s\n", 43, spd->tckmax,
952 " spd->tckmax, * 43 Max device cycle time tCKmax *");
953 printf("%-3d : %02x %s\n", 44, spd->tdqsq,
954 " spd->tdqsq, * 44 Max DQS to DQ skew *");
955 printf("%-3d : %02x %s\n", 45, spd->tqhs,
956 " spd->tqhs, * 45 Max Read DataHold skew tQHS *");
957 printf("%-3d : %02x %s\n", 46, spd->pll_relock,
958 " spd->pll_relock, * 46 PLL Relock time *");
959 printf("%-3d : %02x %s\n", 47, spd->Tcasemax,
960 " spd->Tcasemax, * 47 Tcasemax *");
961 printf("%-3d : %02x %s\n", 48, spd->psiTAdram,
962 " spd->psiTAdram, * 48 Thermal Resistance of DRAM Package "
963 "from Top (Case) to Ambient (Psi T-A DRAM) *");
964 printf("%-3d : %02x %s\n", 49, spd->dt0_mode,
965 " spd->dt0_mode, * 49 DRAM Case Temperature Rise from "
966 "Ambient due to Activate-Precharge/Mode Bits "
967 "(DT0/Mode Bits) *)");
968 printf("%-3d : %02x %s\n", 50, spd->dt2n_dt2q,
969 " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from "
970 "Ambient due to Precharge/Quiet Standby "
972 printf("%-3d : %02x %s\n", 51, spd->dt2p,
973 " spd->dt2p, * 51 DRAM Case Temperature Rise from "
974 "Ambient due to Precharge Power-Down (DT2P) *");
975 printf("%-3d : %02x %s\n", 52, spd->dt3n,
976 " spd->dt3n, * 52 DRAM Case Temperature Rise from "
977 "Ambient due to Active Standby (DT3N) *");
978 printf("%-3d : %02x %s\n", 53, spd->dt3pfast,
979 " spd->dt3pfast, * 53 DRAM Case Temperature Rise from "
980 "Ambient due to Active Power-Down with Fast PDN Exit "
982 printf("%-3d : %02x %s\n", 54, spd->dt3pslow,
983 " spd->dt3pslow, * 54 DRAM Case Temperature Rise from "
984 "Ambient due to Active Power-Down with Slow PDN Exit "
986 printf("%-3d : %02x %s\n", 55, spd->dt4r_dt4r4w,
987 " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
988 "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
989 "(DT4R/DT4R4W Mode Bit) *");
990 printf("%-3d : %02x %s\n", 56, spd->dt5b,
991 " spd->dt5b, * 56 DRAM Case Temperature Rise from "
992 "Ambient due to Burst Refresh (DT5B) *");
993 printf("%-3d : %02x %s\n", 57, spd->dt7,
994 " spd->dt7, * 57 DRAM Case Temperature Rise from "
995 "Ambient due to Bank Interleave Reads with "
996 "Auto-Precharge (DT7) *");
997 printf("%-3d : %02x %s\n", 58, spd->psiTApll,
998 " spd->psiTApll, * 58 Thermal Resistance of PLL Package form"
999 " Top (Case) to Ambient (Psi T-A PLL) *");
1000 printf("%-3d : %02x %s\n", 59, spd->psiTAreg,
1001 " spd->psiTAreg, * 59 Thermal Reisitance of Register Package"
1002 " from Top (Case) to Ambient (Psi T-A Register) *");
1003 printf("%-3d : %02x %s\n", 60, spd->dtpllactive,
1004 " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
1005 "Ambient due to PLL Active (DT PLL Active) *");
1006 printf("%-3d : %02x %s\n", 61, spd->dtregact,
1008 "* 61 Register Case Temperature Rise from Ambient due to "
1009 "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
1010 printf("%-3d : %02x %s\n", 62, spd->spd_rev,
1011 " spd->spd_rev, * 62 SPD Data Revision Code *");
1012 printf("%-3d : %02x %s\n", 63, spd->cksum,
1013 " spd->cksum, * 63 Checksum for bytes 0-62 *");
1015 printf("%-3d-%3d: ", 64, 71);
1017 for (i = 0; i < 8; i++)
1018 printf("%02x", spd->mid[i]);
1020 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1022 printf("%-3d : %02x %s\n", 72, spd->mloc,
1023 " spd->mloc, * 72 Manufacturing Location *");
1025 printf("%-3d-%3d: >>", 73, 90);
1026 for (i = 0; i < 18; i++)
1027 printf("%c", spd->mpart[i]);
1030 printf("<<* 73 Manufacturer's Part Number *\n");
1032 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1033 "* 91 Revision Code *");
1034 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1035 "* 93 Manufacturing Date *");
1036 printf("%-3d-%3d: ", 95, 98);
1038 for (i = 0; i < 4; i++)
1039 printf("%02x", spd->sernum[i]);
1041 printf("* 95 Assembly Serial Number *\n");
1043 printf("%-3d-%3d: ", 99, 127);
1044 for (i = 0; i < 27; i++)
1045 printf("%02x", spd->mspec[i]);
1048 printf("* 99 Manufacturer Specific Data *\n");
1052 #ifdef CONFIG_FSL_DDR3
1053 void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
1057 /* General Section: Bytes 0-59 */
1059 #define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y);
1060 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1061 printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1063 PRINT_NXS(0, spd->info_size_crc,
1064 "info_size_crc bytes written into serial memory, "
1066 PRINT_NXS(1, spd->spd_rev,
1067 "spd_rev SPD Revision");
1068 PRINT_NXS(2, spd->mem_type,
1069 "mem_type Key Byte / DRAM Device Type");
1070 PRINT_NXS(3, spd->module_type,
1071 "module_type Key Byte / Module Type");
1072 PRINT_NXS(4, spd->density_banks,
1073 "density_banks SDRAM Density and Banks");
1074 PRINT_NXS(5, spd->addressing,
1075 "addressing SDRAM Addressing");
1076 PRINT_NXS(6, spd->module_vdd,
1077 "module_vdd Module Nominal Voltage, VDD");
1078 PRINT_NXS(7, spd->organization,
1079 "organization Module Organization");
1080 PRINT_NXS(8, spd->bus_width,
1081 "bus_width Module Memory Bus Width");
1082 PRINT_NXS(9, spd->ftb_div,
1083 "ftb_div Fine Timebase (FTB) Dividend / Divisor");
1084 PRINT_NXS(10, spd->mtb_dividend,
1085 "mtb_dividend Medium Timebase (MTB) Dividend");
1086 PRINT_NXS(11, spd->mtb_divisor,
1087 "mtb_divisor Medium Timebase (MTB) Divisor");
1088 PRINT_NXS(12, spd->tCK_min,
1089 "tCK_min SDRAM Minimum Cycle Time");
1090 PRINT_NXS(13, spd->res_13,
1092 PRINT_NXS(14, spd->caslat_lsb,
1093 "caslat_lsb CAS Latencies Supported, LSB");
1094 PRINT_NXS(15, spd->caslat_msb,
1095 "caslat_msb CAS Latencies Supported, MSB");
1096 PRINT_NXS(16, spd->tAA_min,
1097 "tAA_min Min CAS Latency Time");
1098 PRINT_NXS(17, spd->tWR_min,
1099 "tWR_min Min Write REcovery Time");
1100 PRINT_NXS(18, spd->tRCD_min,
1101 "tRCD_min Min RAS# to CAS# Delay Time");
1102 PRINT_NXS(19, spd->tRRD_min,
1103 "tRRD_min Min Row Active to Row Active Delay Time");
1104 PRINT_NXS(20, spd->tRP_min,
1105 "tRP_min Min Row Precharge Delay Time");
1106 PRINT_NXS(21, spd->tRAS_tRC_ext,
1107 "tRAS_tRC_ext Upper Nibbles for tRAS and tRC");
1108 PRINT_NXS(22, spd->tRAS_min_lsb,
1109 "tRAS_min_lsb Min Active to Precharge Delay Time, LSB");
1110 PRINT_NXS(23, spd->tRC_min_lsb,
1111 "tRC_min_lsb Min Active to Active/Refresh Delay Time, LSB");
1112 PRINT_NXS(24, spd->tRFC_min_lsb,
1113 "tRFC_min_lsb Min Refresh Recovery Delay Time LSB");
1114 PRINT_NXS(25, spd->tRFC_min_msb,
1115 "tRFC_min_msb Min Refresh Recovery Delay Time MSB");
1116 PRINT_NXS(26, spd->tWTR_min,
1117 "tWTR_min Min Internal Write to Read Command Delay Time");
1118 PRINT_NXS(27, spd->tRTP_min,
1120 "Min Internal Read to Precharge Command Delay Time");
1121 PRINT_NXS(28, spd->tFAW_msb,
1122 "tFAW_msb Upper Nibble for tFAW");
1123 PRINT_NXS(29, spd->tFAW_min,
1124 "tFAW_min Min Four Activate Window Delay Time");
1125 PRINT_NXS(30, spd->opt_features,
1126 "opt_features SDRAM Optional Features");
1127 PRINT_NXS(31, spd->therm_ref_opt,
1128 "therm_ref_opt SDRAM Thermal and Refresh Opts");
1129 PRINT_NXS(32, spd->therm_sensor,
1130 "therm_sensor SDRAM Thermal Sensor");
1131 PRINT_NXS(33, spd->device_type,
1132 "device_type SDRAM Device Type");
1133 PRINT_NXS(34, spd->fine_tCK_min,
1134 "fine_tCK_min Fine offset for tCKmin");
1135 PRINT_NXS(35, spd->fine_tAA_min,
1136 "fine_tAA_min Fine offset for tAAmin");
1137 PRINT_NXS(36, spd->fine_tRCD_min,
1138 "fine_tRCD_min Fine offset for tRCDmin");
1139 PRINT_NXS(37, spd->fine_tRP_min,
1140 "fine_tRP_min Fine offset for tRPmin");
1141 PRINT_NXS(38, spd->fine_tRC_min,
1142 "fine_tRC_min Fine offset for tRCmin");
1144 printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */
1146 for (i = 39; i <= 59; i++)
1147 printf("%02x ", spd->res_39_59[i - 39]);
1151 switch (spd->module_type) {
1152 case 0x02: /* UDIMM */
1153 case 0x03: /* SO-DIMM */
1154 case 0x04: /* Micro-DIMM */
1155 case 0x06: /* Mini-UDIMM */
1156 PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
1157 "mod_height (Unbuffered) Module Nominal Height");
1158 PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
1159 "mod_thickness (Unbuffered) Module Maximum Thickness");
1160 PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
1161 "ref_raw_card (Unbuffered) Reference Raw Card Used");
1162 PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
1163 "addr_mapping (Unbuffered) Address mapping from "
1164 "Edge Connector to DRAM");
1166 case 0x01: /* RDIMM */
1167 case 0x05: /* Mini-RDIMM */
1168 PRINT_NXS(60, spd->mod_section.registered.mod_height,
1169 "mod_height (Registered) Module Nominal Height");
1170 PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
1171 "mod_thickness (Registered) Module Maximum Thickness");
1172 PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
1173 "ref_raw_card (Registered) Reference Raw Card Used");
1174 PRINT_NXS(63, spd->mod_section.registered.modu_attr,
1175 "modu_attr (Registered) DIMM Module Attributes");
1176 PRINT_NXS(64, spd->mod_section.registered.thermal,
1177 "thermal (Registered) Thermal Heat "
1178 "Spreader Solution");
1179 PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
1180 "reg_id_lo (Registered) Register Manufacturer ID "
1182 PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
1183 "reg_id_hi (Registered) Register Manufacturer ID "
1185 PRINT_NXS(67, spd->mod_section.registered.reg_rev,
1186 "reg_rev (Registered) Register "
1188 PRINT_NXS(68, spd->mod_section.registered.reg_type,
1189 "reg_type (Registered) Register Type");
1190 for (i = 69; i <= 76; i++) {
1191 printf("%-3d : %02x rcw[%d]\n", i,
1192 spd->mod_section.registered.rcw[i-69], i-69);
1196 /* Module-specific Section, Unsupported Module Type */
1197 printf("%-3d-%3d: ", 60, 116);
1199 for (i = 60; i <= 116; i++)
1200 printf("%02x", spd->mod_section.uc[i - 60]);
1205 /* Unique Module ID: Bytes 117-125 */
1206 PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1207 PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1208 PRINT_NXS(119, spd->mloc, "Mfg Location");
1209 PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
1211 printf("%-3d-%3d: ", 122, 125);
1213 for (i = 122; i <= 125; i++)
1214 printf("%02x ", spd->sernum[i - 122]);
1215 printf(" Module Serial Number\n");
1217 /* CRC: Bytes 126-127 */
1218 PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC");
1220 /* Other Manufacturer Fields and User Space: Bytes 128-255 */
1221 printf("%-3d-%3d: ", 128, 145);
1222 for (i = 128; i <= 145; i++)
1223 printf("%02x ", spd->mpart[i - 128]);
1224 printf(" Mfg's Module Part Number\n");
1226 PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
1227 "Module Revision code");
1229 PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1230 PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1232 printf("%-3d-%3d: ", 150, 175);
1233 for (i = 150; i <= 175; i++)
1234 printf("%02x ", spd->msd[i - 150]);
1235 printf(" Mfg's Specific Data\n");
1237 printf("%-3d-%3d: ", 176, 255);
1238 for (i = 176; i <= 255; i++)
1239 printf("%02x", spd->cust[i - 176]);
1240 printf(" Mfg's Specific Data\n");
1245 static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1247 #if defined(CONFIG_FSL_DDR1)
1249 #elif defined(CONFIG_FSL_DDR2)
1251 #elif defined(CONFIG_FSL_DDR3)
1256 static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1257 unsigned int ctrl_mask,
1258 unsigned int dimm_mask,
1259 unsigned int do_mask)
1261 unsigned int i, j, retval;
1263 /* STEP 1: DIMM SPD data */
1264 if (do_mask & STEP_GET_SPD) {
1265 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1266 if (!(ctrl_mask & (1 << i)))
1269 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1270 if (!(dimm_mask & (1 << j)))
1273 printf("SPD info: Controller=%u "
1276 &(pinfo->spd_installed_dimms[i][j]));
1284 /* STEP 2: DIMM Parameters */
1285 if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
1286 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1287 if (!(ctrl_mask & (1 << i)))
1289 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1290 if (!(dimm_mask & (1 << j)))
1292 printf("DIMM parameters: Controller=%u "
1294 print_dimm_parameters(
1295 &(pinfo->dimm_params[i][j]));
1303 /* STEP 3: Common Parameters */
1304 if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
1305 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1306 if (!(ctrl_mask & (1 << i)))
1308 printf("\"lowest common\" DIMM parameters: "
1309 "Controller=%u\n", i);
1310 print_lowest_common_dimm_parameters(
1311 &pinfo->common_timing_params[i]);
1317 /* STEP 4: User Configuration Options */
1318 if (do_mask & STEP_GATHER_OPTS) {
1319 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1320 if (!(ctrl_mask & (1 << i)))
1322 printf("User Config Options: Controller=%u\n", i);
1323 print_memctl_options(&pinfo->memctl_opts[i]);
1329 /* STEP 5: Address assignment */
1330 if (do_mask & STEP_ASSIGN_ADDRESSES) {
1331 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1332 if (!(ctrl_mask & (1 << i)))
1334 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1335 printf("Address Assignment: Controller=%u "
1337 printf("Don't have this functionality yet\n");
1344 /* STEP 6: computed controller register values */
1345 if (do_mask & STEP_COMPUTE_REGS) {
1346 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1347 if (!(ctrl_mask & (1 << i)))
1349 printf("Computed Register Values: Controller=%u\n", i);
1350 print_fsl_memctl_config_regs(
1351 &pinfo->fsl_ddr_config_reg[i]);
1352 retval = check_fsl_memctl_config_regs(
1353 &pinfo->fsl_ddr_config_reg[i]);
1355 printf("check_fsl_memctl_config_regs "
1356 "result = %u\n", retval);
1364 struct data_strings {
1365 const char *data_name;
1366 unsigned int step_mask;
1367 unsigned int dimm_number_required;
1370 #define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
1372 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
1374 unsigned long long ddrsize;
1375 const char *prompt = "FSL DDR>";
1376 char buffer[CONFIG_SYS_CBSIZE];
1377 char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
1379 unsigned int next_step = STEP_GET_SPD;
1380 static const struct data_strings options[] = {
1381 DATA_OPTIONS(spd, STEP_GET_SPD, 1),
1382 DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
1383 DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
1384 DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
1385 DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
1386 DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
1388 static const unsigned int n_opts = ARRAY_SIZE(options);
1389 const char *usage = {
1391 "print print SPD and intermediate computed data\n"
1392 "reset reboot machine\n"
1393 "recompute reload SPD and options to default and recompute regs\n"
1394 "edit modify spd, parameter, or option\n"
1395 "compute recompute registers from current next_step to end\n"
1396 "next_step shows current next_step\n"
1397 "help this message\n"
1398 "go program the memory controller and continue with u-boot\n"
1402 * The strategy for next_step is that it points to the next
1403 * step in the computation process that needs to be done.
1407 * No need to worry for buffer overflow here in
1408 * this function; readline() maxes out at CFG_CBSIZE
1410 readline_into_buffer(prompt, buffer, 0);
1411 argc = parse_line(buffer, argv);
1416 if (strcmp(argv[0], "help") == 0) {
1421 if (strcmp(argv[0], "next_step") == 0) {
1422 printf("next_step = 0x%02X (%s)\n",
1424 step_to_string(next_step));
1428 if (strcmp(argv[0], "edit") == 0) {
1430 unsigned int error = 0;
1431 unsigned int step_mask = 0;
1432 unsigned int ctlr_mask = 0;
1433 unsigned int dimm_mask = 0;
1434 char *p_element = NULL;
1435 char *p_value = NULL;
1436 unsigned int dimm_number_required = 0;
1437 unsigned int ctrl_num;
1438 unsigned int dimm_num;
1439 unsigned int matched = 0;
1442 /* Only the element and value must be last */
1443 printf("edit <c#> <d#> "
1444 "<spd|dimmparms|commonparms|opts|"
1445 "addresses|regs> <element> <value>\n");
1446 printf("for spd, specify byte number for "
1451 for (i = 1; i < argc - 2; i++) {
1452 for (j = 0; j < n_opts; j++) {
1453 if (strcmp(options[j].data_name,
1456 step_mask |= options[j].step_mask;
1457 dimm_number_required =
1458 options[j].dimm_number_required;
1466 if (argv[i][0] == 'c') {
1467 char c = argv[i][1];
1469 ctlr_mask |= 1 << (c - '0');
1473 if (argv[i][0] == 'd') {
1474 char c = argv[i][1];
1476 dimm_mask |= 1 << (c - '0');
1480 printf("unknown arg %s\n", argv[i]);
1491 /* Check arguments */
1493 /* ERROR: If no steps were found */
1494 if (step_mask == 0) {
1495 printf("Error: No valid steps were specified "
1500 /* ERROR: If multiple steps were found */
1501 if (step_mask & (step_mask - 1)) {
1502 printf("Error: Multiple steps specified in "
1507 /* ERROR: Controller not specified */
1508 if (ctlr_mask == 0) {
1509 printf("Error: controller number not "
1510 "specified or no element and "
1511 "value specified\n");
1515 if (ctlr_mask & (ctlr_mask - 1)) {
1516 printf("Error: multiple controllers "
1517 "specified, %X\n", ctlr_mask);
1521 /* ERROR: DIMM number not specified */
1522 if (dimm_number_required && dimm_mask == 0) {
1523 printf("Error: DIMM number number not "
1524 "specified or no element and "
1525 "value specified\n");
1529 if (dimm_mask & (dimm_mask - 1)) {
1530 printf("Error: multipled DIMMs specified\n");
1534 p_element = argv[argc - 2];
1535 p_value = argv[argc - 1];
1537 ctrl_num = __ilog2(ctlr_mask);
1538 dimm_num = __ilog2(dimm_mask);
1540 switch (step_mask) {
1543 unsigned int element_num;
1546 element_num = simple_strtoul(p_element,
1548 value = simple_strtoul(p_value,
1550 fsl_ddr_spd_edit(pinfo,
1555 next_step = STEP_COMPUTE_DIMM_PARMS;
1559 case STEP_COMPUTE_DIMM_PARMS:
1560 fsl_ddr_dimm_parameters_edit(
1561 pinfo, ctrl_num, dimm_num,
1562 p_element, p_value);
1563 next_step = STEP_COMPUTE_COMMON_PARMS;
1566 case STEP_COMPUTE_COMMON_PARMS:
1567 lowest_common_dimm_parameters_edit(pinfo,
1568 ctrl_num, p_element, p_value);
1569 next_step = STEP_GATHER_OPTS;
1572 case STEP_GATHER_OPTS:
1573 fsl_ddr_options_edit(pinfo, ctrl_num,
1574 p_element, p_value);
1575 next_step = STEP_ASSIGN_ADDRESSES;
1578 case STEP_ASSIGN_ADDRESSES:
1579 printf("editing of address assignment "
1580 "not yet implemented\n");
1583 case STEP_COMPUTE_REGS:
1585 fsl_ddr_regs_edit(pinfo,
1589 next_step = STEP_PROGRAM_REGS;
1594 printf("programming error\n");
1602 if (strcmp(argv[0], "reset") == 0) {
1605 * Args don't seem to matter because this
1608 do_reset(NULL, 0, 0, NULL);
1609 printf("Reset didn't work\n");
1612 if (strcmp(argv[0], "recompute") == 0) {
1614 * Recalculate everything, starting with
1615 * loading SPD EEPROM from DIMMs
1617 next_step = STEP_GET_SPD;
1618 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
1622 if (strcmp(argv[0], "compute") == 0) {
1624 * Compute rest of steps starting at
1625 * the current next_step/
1627 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
1631 if (strcmp(argv[0], "print") == 0) {
1633 unsigned int error = 0;
1634 unsigned int step_mask = 0;
1635 unsigned int ctlr_mask = 0;
1636 unsigned int dimm_mask = 0;
1637 unsigned int matched = 0;
1640 printf("print [c<n>] [d<n>] [spd] [dimmparms] "
1641 "[commonparms] [opts] [addresses] [regs]\n");
1645 for (i = 1; i < argc; i++) {
1646 for (j = 0; j < n_opts; j++) {
1647 if (strcmp(options[j].data_name,
1650 step_mask |= options[j].step_mask;
1658 if (argv[i][0] == 'c') {
1659 char c = argv[i][1];
1661 ctlr_mask |= 1 << (c - '0');
1665 if (argv[i][0] == 'd') {
1666 char c = argv[i][1];
1668 dimm_mask |= 1 << (c - '0');
1672 printf("unknown arg %s\n", argv[i]);
1681 /* If no particular controller was found, print all */
1685 /* If no particular dimm was found, print all dimms. */
1689 /* If no steps were found, print all steps. */
1691 step_mask = STEP_ALL;
1693 fsl_ddr_printinfo(pinfo, ctlr_mask,
1694 dimm_mask, step_mask);
1698 if (strcmp(argv[0], "go") == 0) {
1700 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
1704 printf("unknown command %s\n", argv[0]);
1707 debug("end of memory = %llu\n", (u64)ddrsize);