2 * Copyright 2010-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 or any later versionas published by the Free Software Foundation.
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
13 * York Sun [at freescale.com]
17 #include <linux/ctype.h>
18 #include <asm/types.h>
20 #include <asm/fsl_ddr_sdram.h>
23 /* Option parameter Structures */
24 struct options_string {
25 const char *option_name;
31 static unsigned int picos_to_mhz(unsigned int picos)
33 return 1000000 / picos;
36 static void print_option_table(const struct options_string *table,
42 unsigned long long *ptr_l;
44 for (i = 0; i < table_size; i++) {
45 switch (table[i].size) {
47 ptr = (unsigned int *) (base + table[i].offset);
48 if (table[i].printhex) {
49 printf("%s = 0x%08X\n",
50 table[i].option_name, *ptr);
53 table[i].option_name, *ptr);
57 ptr_l = (unsigned long long *) (base + table[i].offset);
59 table[i].option_name, *ptr_l);
62 printf("Unrecognized size!\n");
68 static int handle_option_table(const struct options_string *table,
75 unsigned int value, *ptr;
76 unsigned long long value_l, *ptr_l;
78 for (i = 0; i < table_size; i++) {
79 if (strcmp(table[i].option_name, opt) != 0)
81 switch (table[i].size) {
83 value = simple_strtoul(val, NULL, 0);
84 ptr = base + table[i].offset;
88 value_l = simple_strtoull(val, NULL, 0);
89 ptr_l = base + table[i].offset;
93 printf("Unrecognized size!\n");
102 static void fsl_ddr_generic_edit(void *pdata,
104 unsigned int element_size,
105 unsigned int element_num,
108 char *pcdata = (char *)pdata; /* BIG ENDIAN ONLY */
110 pcdata += element_num * element_size;
111 if ((pcdata + element_size) > (char *) pend) {
112 printf("trying to write past end of data\n");
116 switch (element_size) {
118 __raw_writeb(value, pcdata);
121 __raw_writew(value, pcdata);
124 __raw_writel(value, pcdata);
127 printf("unexpected element size %u\n", element_size);
132 static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
133 unsigned int ctrl_num,
134 unsigned int dimm_num,
135 unsigned int element_num,
138 generic_spd_eeprom_t *pspd;
140 pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
141 fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
144 #define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
145 sizeof((common_timing_params_t *)0)->x, 0}
147 static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
148 unsigned int ctrl_num,
149 const char *optname_str,
150 const char *value_str)
152 common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
154 static const struct options_string options[] = {
155 COMMON_TIMING(tCKmin_X_ps),
156 COMMON_TIMING(tCKmax_ps),
157 COMMON_TIMING(tCKmax_max_ps),
158 COMMON_TIMING(tRCD_ps),
159 COMMON_TIMING(tRP_ps),
160 COMMON_TIMING(tRAS_ps),
161 COMMON_TIMING(tWR_ps),
162 COMMON_TIMING(tWTR_ps),
163 COMMON_TIMING(tRFC_ps),
164 COMMON_TIMING(tRRD_ps),
165 COMMON_TIMING(tRC_ps),
166 COMMON_TIMING(refresh_rate_ps),
167 COMMON_TIMING(tIS_ps),
168 COMMON_TIMING(tIH_ps),
169 COMMON_TIMING(tDS_ps),
170 COMMON_TIMING(tDH_ps),
171 COMMON_TIMING(tRTP_ps),
172 COMMON_TIMING(tDQSQ_max_ps),
173 COMMON_TIMING(tQHS_ps),
174 COMMON_TIMING(ndimms_present),
175 COMMON_TIMING(lowest_common_SPD_caslat),
176 COMMON_TIMING(highest_common_derated_caslat),
177 COMMON_TIMING(additive_latency),
178 COMMON_TIMING(all_DIMMs_burst_lengths_bitmask),
179 COMMON_TIMING(all_DIMMs_registered),
180 COMMON_TIMING(all_DIMMs_unbuffered),
181 COMMON_TIMING(all_DIMMs_ECC_capable),
182 COMMON_TIMING(total_mem),
183 COMMON_TIMING(base_address),
185 static const unsigned int n_opts = ARRAY_SIZE(options);
187 if (handle_option_table(options, n_opts, p, optname_str, value_str))
190 printf("Error: couldn't find option string %s\n", optname_str);
193 #define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
194 sizeof((dimm_params_t *)0)->x, 0}
196 static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
197 unsigned int ctrl_num,
198 unsigned int dimm_num,
199 const char *optname_str,
200 const char *value_str)
202 dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
204 static const struct options_string options[] = {
206 DIMM_PARM(data_width),
207 DIMM_PARM(primary_sdram_width),
208 DIMM_PARM(ec_sdram_width),
209 DIMM_PARM(registered_dimm),
211 DIMM_PARM(n_row_addr),
212 DIMM_PARM(n_col_addr),
213 DIMM_PARM(edc_config),
214 DIMM_PARM(n_banks_per_sdram_device),
215 DIMM_PARM(burst_lengths_bitmask),
216 DIMM_PARM(row_density),
218 DIMM_PARM(tCKmin_X_ps),
219 DIMM_PARM(tCKmin_X_minus_1_ps),
220 DIMM_PARM(tCKmin_X_minus_2_ps),
221 DIMM_PARM(tCKmax_ps),
224 DIMM_PARM(caslat_X_minus_1),
225 DIMM_PARM(caslat_X_minus_2),
227 DIMM_PARM(caslat_lowest_derated),
237 DIMM_PARM(refresh_rate_ps),
244 DIMM_PARM(tDQSQ_max_ps),
247 DIMM_PARM(rank_density),
249 DIMM_PARM(base_address),
252 static const unsigned int n_opts = ARRAY_SIZE(options);
254 if (handle_option_table(options, n_opts, p, optname_str, value_str))
257 printf("couldn't find option string %s\n", optname_str);
260 static void print_dimm_parameters(const dimm_params_t *pdimm)
262 static const struct options_string options[] = {
264 DIMM_PARM(data_width),
265 DIMM_PARM(primary_sdram_width),
266 DIMM_PARM(ec_sdram_width),
267 DIMM_PARM(registered_dimm),
269 DIMM_PARM(n_row_addr),
270 DIMM_PARM(n_col_addr),
271 DIMM_PARM(edc_config),
272 DIMM_PARM(n_banks_per_sdram_device),
274 DIMM_PARM(tCKmin_X_ps),
275 DIMM_PARM(tCKmin_X_minus_1_ps),
276 DIMM_PARM(tCKmin_X_minus_2_ps),
277 DIMM_PARM(tCKmax_ps),
281 DIMM_PARM(caslat_X_minus_1),
282 DIMM_PARM(caslat_X_minus_2),
283 DIMM_PARM(caslat_lowest_derated),
293 DIMM_PARM(refresh_rate_ps),
300 DIMM_PARM(tDQSQ_max_ps),
303 static const unsigned int n_opts = ARRAY_SIZE(options);
305 if (pdimm->n_ranks == 0) {
306 printf("DIMM not present\n");
309 printf("DIMM organization parameters:\n");
310 printf("module part name = %s\n", pdimm->mpart);
311 printf("rank_density = %llu bytes (%llu megabytes)\n",
312 pdimm->rank_density, pdimm->rank_density / 0x100000);
313 printf("capacity = %llu bytes (%llu megabytes)\n",
314 pdimm->capacity, pdimm->capacity / 0x100000);
315 printf("burst_lengths_bitmask = %02X\n",
316 pdimm->burst_lengths_bitmask);
317 printf("base_addresss = %llu (%08llX %08llX)\n",
319 (pdimm->base_address >> 32),
320 pdimm->base_address & 0xFFFFFFFF);
321 print_option_table(options, n_opts, pdimm);
324 static void print_lowest_common_dimm_parameters(
325 const common_timing_params_t *plcd_dimm_params)
327 static const struct options_string options[] = {
328 COMMON_TIMING(tCKmax_max_ps),
329 COMMON_TIMING(tRCD_ps),
330 COMMON_TIMING(tRP_ps),
331 COMMON_TIMING(tRAS_ps),
332 COMMON_TIMING(tWR_ps),
333 COMMON_TIMING(tWTR_ps),
334 COMMON_TIMING(tRFC_ps),
335 COMMON_TIMING(tRRD_ps),
336 COMMON_TIMING(tRC_ps),
337 COMMON_TIMING(refresh_rate_ps),
338 COMMON_TIMING(tIS_ps),
339 COMMON_TIMING(tDS_ps),
340 COMMON_TIMING(tDH_ps),
341 COMMON_TIMING(tRTP_ps),
342 COMMON_TIMING(tDQSQ_max_ps),
343 COMMON_TIMING(tQHS_ps),
344 COMMON_TIMING(lowest_common_SPD_caslat),
345 COMMON_TIMING(highest_common_derated_caslat),
346 COMMON_TIMING(additive_latency),
347 COMMON_TIMING(ndimms_present),
348 COMMON_TIMING(all_DIMMs_registered),
349 COMMON_TIMING(all_DIMMs_unbuffered),
350 COMMON_TIMING(all_DIMMs_ECC_capable),
352 static const unsigned int n_opts = ARRAY_SIZE(options);
354 /* Clock frequencies */
355 printf("tCKmin_X_ps = %u (%u MHz)\n",
356 plcd_dimm_params->tCKmin_X_ps,
357 picos_to_mhz(plcd_dimm_params->tCKmin_X_ps));
358 printf("tCKmax_ps = %u (%u MHz)\n",
359 plcd_dimm_params->tCKmax_ps,
360 picos_to_mhz(plcd_dimm_params->tCKmax_ps));
361 printf("all_DIMMs_burst_lengths_bitmask = %02X\n",
362 plcd_dimm_params->all_DIMMs_burst_lengths_bitmask);
364 print_option_table(options, n_opts, plcd_dimm_params);
366 printf("total_mem = %llu (%llu megabytes)\n",
367 plcd_dimm_params->total_mem,
368 plcd_dimm_params->total_mem / 0x100000);
369 printf("base_address = %llu (%llu megabytes)\n",
370 plcd_dimm_params->base_address,
371 plcd_dimm_params->base_address / 0x100000);
374 #define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
375 sizeof((memctl_options_t *)0)->x, 0}
376 #define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
377 offsetof(memctl_options_t, cs_local_opts[x].y), \
378 sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
380 static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
381 unsigned int ctl_num,
382 const char *optname_str,
383 const char *value_str)
385 memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
387 * This array all on the stack and *computed* each time this
390 static const struct options_string options[] = {
391 CTRL_OPTIONS_CS(0, odt_rd_cfg),
392 CTRL_OPTIONS_CS(0, odt_wr_cfg),
393 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
394 CTRL_OPTIONS_CS(1, odt_rd_cfg),
395 CTRL_OPTIONS_CS(1, odt_wr_cfg),
397 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
398 CTRL_OPTIONS_CS(2, odt_rd_cfg),
399 CTRL_OPTIONS_CS(2, odt_wr_cfg),
401 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
402 CTRL_OPTIONS_CS(3, odt_rd_cfg),
403 CTRL_OPTIONS_CS(3, odt_wr_cfg),
405 #if defined(CONFIG_FSL_DDR3)
406 CTRL_OPTIONS_CS(0, odt_rtt_norm),
407 CTRL_OPTIONS_CS(0, odt_rtt_wr),
408 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
409 CTRL_OPTIONS_CS(1, odt_rtt_norm),
410 CTRL_OPTIONS_CS(1, odt_rtt_wr),
412 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
413 CTRL_OPTIONS_CS(2, odt_rtt_norm),
414 CTRL_OPTIONS_CS(2, odt_rtt_wr),
416 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
417 CTRL_OPTIONS_CS(3, odt_rtt_norm),
418 CTRL_OPTIONS_CS(3, odt_rtt_wr),
421 CTRL_OPTIONS(memctl_interleaving),
422 CTRL_OPTIONS(memctl_interleaving_mode),
423 CTRL_OPTIONS(ba_intlv_ctl),
424 CTRL_OPTIONS(ECC_mode),
425 CTRL_OPTIONS(ECC_init_using_memctl),
426 CTRL_OPTIONS(DQS_config),
427 CTRL_OPTIONS(self_refresh_in_sleep),
428 CTRL_OPTIONS(dynamic_power),
429 CTRL_OPTIONS(data_bus_width),
430 CTRL_OPTIONS(burst_length),
431 CTRL_OPTIONS(cas_latency_override),
432 CTRL_OPTIONS(cas_latency_override_value),
433 CTRL_OPTIONS(use_derated_caslat),
434 CTRL_OPTIONS(additive_latency_override),
435 CTRL_OPTIONS(additive_latency_override_value),
436 CTRL_OPTIONS(clk_adjust),
437 CTRL_OPTIONS(cpo_override),
438 CTRL_OPTIONS(write_data_delay),
439 CTRL_OPTIONS(half_strength_driver_enable),
442 * These can probably be changed to 2T_EN and 3T_EN
443 * (using a leading numerical character) without problem
445 CTRL_OPTIONS(twoT_en),
446 CTRL_OPTIONS(threeT_en),
448 CTRL_OPTIONS(bstopre),
449 CTRL_OPTIONS(wrlvl_override),
450 CTRL_OPTIONS(wrlvl_sample),
451 CTRL_OPTIONS(wrlvl_start),
452 CTRL_OPTIONS(rcw_override),
455 CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
456 CTRL_OPTIONS(tFAW_window_four_activates_ps),
457 CTRL_OPTIONS(trwt_override),
461 static const unsigned int n_opts = ARRAY_SIZE(options);
463 if (handle_option_table(options, n_opts, p,
464 optname_str, value_str))
467 printf("couldn't find option string %s\n", optname_str);
470 #define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
471 sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
472 #define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
473 offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
474 sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
476 static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
479 static const struct options_string options[] = {
480 CFG_REGS_CS(0, bnds),
481 CFG_REGS_CS(0, config),
482 CFG_REGS_CS(0, config_2),
483 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
484 CFG_REGS_CS(1, bnds),
485 CFG_REGS_CS(1, config),
486 CFG_REGS_CS(1, config_2),
488 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
489 CFG_REGS_CS(2, bnds),
490 CFG_REGS_CS(2, config),
491 CFG_REGS_CS(2, config_2),
493 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
494 CFG_REGS_CS(3, bnds),
495 CFG_REGS_CS(3, config),
496 CFG_REGS_CS(3, config_2),
498 CFG_REGS(timing_cfg_3),
499 CFG_REGS(timing_cfg_0),
500 CFG_REGS(timing_cfg_1),
501 CFG_REGS(timing_cfg_2),
502 CFG_REGS(ddr_sdram_cfg),
503 CFG_REGS(ddr_sdram_cfg_2),
504 CFG_REGS(ddr_sdram_mode),
505 CFG_REGS(ddr_sdram_mode_2),
506 CFG_REGS(ddr_sdram_mode_3),
507 CFG_REGS(ddr_sdram_mode_4),
508 CFG_REGS(ddr_sdram_mode_5),
509 CFG_REGS(ddr_sdram_mode_6),
510 CFG_REGS(ddr_sdram_mode_7),
511 CFG_REGS(ddr_sdram_mode_8),
512 CFG_REGS(ddr_sdram_interval),
513 CFG_REGS(ddr_data_init),
514 CFG_REGS(ddr_sdram_clk_cntl),
515 CFG_REGS(ddr_init_addr),
516 CFG_REGS(ddr_init_ext_addr),
517 CFG_REGS(timing_cfg_4),
518 CFG_REGS(timing_cfg_5),
519 CFG_REGS(ddr_zq_cntl),
520 CFG_REGS(ddr_wrlvl_cntl),
521 CFG_REGS(ddr_sr_cntr),
522 CFG_REGS(ddr_sdram_rcw_1),
523 CFG_REGS(ddr_sdram_rcw_2),
526 CFG_REGS(err_disable),
527 CFG_REGS(err_int_en),
529 static const unsigned int n_opts = ARRAY_SIZE(options);
531 print_option_table(options, n_opts, ddr);
533 for (i = 0; i < 32; i++)
534 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
537 static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
538 unsigned int ctrl_num,
540 const char *value_str)
543 fsl_ddr_cfg_regs_t *ddr;
545 static const struct options_string options[] = {
546 CFG_REGS_CS(0, bnds),
547 CFG_REGS_CS(0, config),
548 CFG_REGS_CS(0, config_2),
549 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
550 CFG_REGS_CS(1, bnds),
551 CFG_REGS_CS(1, config),
552 CFG_REGS_CS(1, config_2),
554 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
555 CFG_REGS_CS(2, bnds),
556 CFG_REGS_CS(2, config),
557 CFG_REGS_CS(2, config_2),
559 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
560 CFG_REGS_CS(3, bnds),
561 CFG_REGS_CS(3, config),
562 CFG_REGS_CS(3, config_2),
564 CFG_REGS(timing_cfg_3),
565 CFG_REGS(timing_cfg_0),
566 CFG_REGS(timing_cfg_1),
567 CFG_REGS(timing_cfg_2),
568 CFG_REGS(ddr_sdram_cfg),
569 CFG_REGS(ddr_sdram_cfg_2),
570 CFG_REGS(ddr_sdram_mode),
571 CFG_REGS(ddr_sdram_mode_2),
572 CFG_REGS(ddr_sdram_mode_3),
573 CFG_REGS(ddr_sdram_mode_4),
574 CFG_REGS(ddr_sdram_mode_5),
575 CFG_REGS(ddr_sdram_mode_6),
576 CFG_REGS(ddr_sdram_mode_7),
577 CFG_REGS(ddr_sdram_mode_8),
578 CFG_REGS(ddr_sdram_interval),
579 CFG_REGS(ddr_data_init),
580 CFG_REGS(ddr_sdram_clk_cntl),
581 CFG_REGS(ddr_init_addr),
582 CFG_REGS(ddr_init_ext_addr),
583 CFG_REGS(timing_cfg_4),
584 CFG_REGS(timing_cfg_5),
585 CFG_REGS(ddr_zq_cntl),
586 CFG_REGS(ddr_wrlvl_cntl),
587 CFG_REGS(ddr_sr_cntr),
588 CFG_REGS(ddr_sdram_rcw_1),
589 CFG_REGS(ddr_sdram_rcw_2),
592 CFG_REGS(err_disable),
593 CFG_REGS(err_int_en),
594 CFG_REGS(ddr_sdram_rcw_2),
595 CFG_REGS(ddr_sdram_rcw_2),
598 static const unsigned int n_opts = ARRAY_SIZE(options);
600 debug("fsl_ddr_regs_edit: ctrl_num = %u, "
601 "regname = %s, value = %s\n",
602 ctrl_num, regname, value_str);
603 if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
606 ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
608 if (handle_option_table(options, n_opts, ddr, regname, value_str))
611 for (i = 0; i < 32; i++) {
612 unsigned int value = simple_strtoul(value_str, NULL, 0);
613 sprintf(buf, "debug_%u", i + 1);
614 if (strcmp(buf, regname) == 0) {
615 ddr->debug[i] = value;
619 printf("Error: couldn't find register string %s\n", regname);
622 #define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
623 sizeof((memctl_options_t *)0)->x, 1}
625 static void print_memctl_options(const memctl_options_t *popts)
627 static const struct options_string options[] = {
628 CTRL_OPTIONS_CS(0, odt_rd_cfg),
629 CTRL_OPTIONS_CS(0, odt_wr_cfg),
630 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
631 CTRL_OPTIONS_CS(1, odt_rd_cfg),
632 CTRL_OPTIONS_CS(1, odt_wr_cfg),
634 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
635 CTRL_OPTIONS_CS(2, odt_rd_cfg),
636 CTRL_OPTIONS_CS(2, odt_wr_cfg),
638 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
639 CTRL_OPTIONS_CS(3, odt_rd_cfg),
640 CTRL_OPTIONS_CS(3, odt_wr_cfg),
642 #if defined(CONFIG_FSL_DDR3)
643 CTRL_OPTIONS_CS(0, odt_rtt_norm),
644 CTRL_OPTIONS_CS(0, odt_rtt_wr),
645 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
646 CTRL_OPTIONS_CS(1, odt_rtt_norm),
647 CTRL_OPTIONS_CS(1, odt_rtt_wr),
649 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
650 CTRL_OPTIONS_CS(2, odt_rtt_norm),
651 CTRL_OPTIONS_CS(2, odt_rtt_wr),
653 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
654 CTRL_OPTIONS_CS(3, odt_rtt_norm),
655 CTRL_OPTIONS_CS(3, odt_rtt_wr),
658 CTRL_OPTIONS(memctl_interleaving),
659 CTRL_OPTIONS(memctl_interleaving_mode),
660 CTRL_OPTIONS_HEX(ba_intlv_ctl),
661 CTRL_OPTIONS(ECC_mode),
662 CTRL_OPTIONS(ECC_init_using_memctl),
663 CTRL_OPTIONS(DQS_config),
664 CTRL_OPTIONS(self_refresh_in_sleep),
665 CTRL_OPTIONS(dynamic_power),
666 CTRL_OPTIONS(data_bus_width),
667 CTRL_OPTIONS(burst_length),
668 CTRL_OPTIONS(cas_latency_override),
669 CTRL_OPTIONS(cas_latency_override_value),
670 CTRL_OPTIONS(use_derated_caslat),
671 CTRL_OPTIONS(additive_latency_override),
672 CTRL_OPTIONS(additive_latency_override_value),
673 CTRL_OPTIONS(clk_adjust),
674 CTRL_OPTIONS(cpo_override),
675 CTRL_OPTIONS(write_data_delay),
676 CTRL_OPTIONS(half_strength_driver_enable),
678 * These can probably be changed to 2T_EN and 3T_EN
679 * (using a leading numerical character) without problem
681 CTRL_OPTIONS(twoT_en),
682 CTRL_OPTIONS(threeT_en),
683 CTRL_OPTIONS(registered_dimm_en),
685 CTRL_OPTIONS(bstopre),
686 CTRL_OPTIONS(wrlvl_override),
687 CTRL_OPTIONS(wrlvl_sample),
688 CTRL_OPTIONS(wrlvl_start),
689 CTRL_OPTIONS(rcw_override),
692 CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
693 CTRL_OPTIONS(tFAW_window_four_activates_ps),
694 CTRL_OPTIONS(trwt_override),
697 static const unsigned int n_opts = ARRAY_SIZE(options);
699 print_option_table(options, n_opts, popts);
702 #ifdef CONFIG_FSL_DDR1
703 void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
707 printf("%-3d : %02x %s\n", 0, spd->info_size,
708 " spd->info_size, * 0 # bytes written into serial memory *");
709 printf("%-3d : %02x %s\n", 1, spd->chip_size,
710 " spd->chip_size, * 1 Total # bytes of SPD memory device *");
711 printf("%-3d : %02x %s\n", 2, spd->mem_type,
712 " spd->mem_type, * 2 Fundamental memory type *");
713 printf("%-3d : %02x %s\n", 3, spd->nrow_addr,
714 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *");
715 printf("%-3d : %02x %s\n", 4, spd->ncol_addr,
716 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *");
717 printf("%-3d : %02x %s\n", 5, spd->nrows,
718 " spd->nrows * 5 # of DIMM Banks *");
719 printf("%-3d : %02x %s\n", 6, spd->dataw_lsb,
720 " spd->dataw_lsb, * 6 Data Width lsb of this assembly *");
721 printf("%-3d : %02x %s\n", 7, spd->dataw_msb,
722 " spd->dataw_msb, * 7 Data Width msb of this assembly *");
723 printf("%-3d : %02x %s\n", 8, spd->voltage,
724 " spd->voltage, * 8 Voltage intf std of this assembly *");
725 printf("%-3d : %02x %s\n", 9, spd->clk_cycle,
726 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *");
727 printf("%-3d : %02x %s\n", 10, spd->clk_access,
728 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *");
729 printf("%-3d : %02x %s\n", 11, spd->config,
730 " spd->config, * 11 DIMM Configuration type *");
731 printf("%-3d : %02x %s\n", 12, spd->refresh,
732 " spd->refresh, * 12 Refresh Rate/Type *");
733 printf("%-3d : %02x %s\n", 13, spd->primw,
734 " spd->primw, * 13 Primary SDRAM Width *");
735 printf("%-3d : %02x %s\n", 14, spd->ecw,
736 " spd->ecw, * 14 Error Checking SDRAM width *");
737 printf("%-3d : %02x %s\n", 15, spd->min_delay,
738 " spd->min_delay, * 15 Back to Back Random Access *");
739 printf("%-3d : %02x %s\n", 16, spd->burstl,
740 " spd->burstl, * 16 Burst Lengths Supported *");
741 printf("%-3d : %02x %s\n", 17, spd->nbanks,
742 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *");
743 printf("%-3d : %02x %s\n", 18, spd->cas_lat,
744 " spd->cas_lat, * 18 CAS# Latencies Supported *");
745 printf("%-3d : %02x %s\n", 19, spd->cs_lat,
746 " spd->cs_lat, * 19 Chip Select Latency *");
747 printf("%-3d : %02x %s\n", 20, spd->write_lat,
748 " spd->write_lat, * 20 Write Latency/Recovery *");
749 printf("%-3d : %02x %s\n", 21, spd->mod_attr,
750 " spd->mod_attr, * 21 SDRAM Module Attributes *");
751 printf("%-3d : %02x %s\n", 22, spd->dev_attr,
752 " spd->dev_attr, * 22 SDRAM Device Attributes *");
753 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2,
754 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *");
755 printf("%-3d : %02x %s\n", 24, spd->clk_access2,
756 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
757 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3,
758 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *");
759 printf("%-3d : %02x %s\n", 26, spd->clk_access3,
760 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
761 printf("%-3d : %02x %s\n", 27, spd->trp,
762 " spd->trp, * 27 Min Row Precharge Time (tRP)*");
763 printf("%-3d : %02x %s\n", 28, spd->trrd,
764 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *");
765 printf("%-3d : %02x %s\n", 29, spd->trcd,
766 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *");
767 printf("%-3d : %02x %s\n", 30, spd->tras,
768 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *");
769 printf("%-3d : %02x %s\n", 31, spd->bank_dens,
770 " spd->bank_dens, * 31 Density of each bank on module *");
771 printf("%-3d : %02x %s\n", 32, spd->ca_setup,
772 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *");
773 printf("%-3d : %02x %s\n", 33, spd->ca_hold,
774 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *");
775 printf("%-3d : %02x %s\n", 34, spd->data_setup,
776 " spd->data_setup, * 34 Data signal input setup time *");
777 printf("%-3d : %02x %s\n", 35, spd->data_hold,
778 " spd->data_hold, * 35 Data signal input hold time *");
779 printf("%-3d : %02x %s\n", 36, spd->res_36_40[0],
780 " spd->res_36_40[0], * 36 Reserved / tWR *");
781 printf("%-3d : %02x %s\n", 37, spd->res_36_40[1],
782 " spd->res_36_40[1], * 37 Reserved / tWTR *");
783 printf("%-3d : %02x %s\n", 38, spd->res_36_40[2],
784 " spd->res_36_40[2], * 38 Reserved / tRTP *");
785 printf("%-3d : %02x %s\n", 39, spd->res_36_40[3],
786 " spd->res_36_40[3], * 39 Reserved / mem_probe *");
787 printf("%-3d : %02x %s\n", 40, spd->res_36_40[4],
788 " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
789 printf("%-3d : %02x %s\n", 41, spd->trc,
790 " spd->trc, * 41 Min Active to Auto refresh time tRC *");
791 printf("%-3d : %02x %s\n", 42, spd->trfc,
792 " spd->trfc, * 42 Min Auto to Active period tRFC *");
793 printf("%-3d : %02x %s\n", 43, spd->tckmax,
794 " spd->tckmax, * 43 Max device cycle time tCKmax *");
795 printf("%-3d : %02x %s\n", 44, spd->tdqsq,
796 " spd->tdqsq, * 44 Max DQS to DQ skew *");
797 printf("%-3d : %02x %s\n", 45, spd->tqhs,
798 " spd->tqhs, * 45 Max Read DataHold skew tQHS *");
799 printf("%-3d : %02x %s\n", 46, spd->res_46,
800 " spd->res_46, * 46 Reserved/ PLL Relock time *");
801 printf("%-3d : %02x %s\n", 47, spd->dimm_height,
802 " spd->dimm_height * 47 SDRAM DIMM Height *");
804 printf("%-3d-%3d: ", 48, 61);
806 for (i = 0; i < 14; i++)
807 printf("%02x", spd->res_48_61[i]);
809 printf(" * 48-61 IDD in SPD and Reserved space *\n");
811 printf("%-3d : %02x %s\n", 62, spd->spd_rev,
812 " spd->spd_rev, * 62 SPD Data Revision Code *");
813 printf("%-3d : %02x %s\n", 63, spd->cksum,
814 " spd->cksum, * 63 Checksum for bytes 0-62 *");
815 printf("%-3d-%3d: ", 64, 71);
817 for (i = 0; i < 8; i++)
818 printf("%02x", spd->mid[i]);
820 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
821 printf("%-3d : %02x %s\n", 72, spd->mloc,
822 " spd->mloc, * 72 Manufacturing Location *");
824 printf("%-3d-%3d: >>", 73, 90);
826 for (i = 0; i < 18; i++)
827 printf("%c", spd->mpart[i]);
829 printf("<<* 73 Manufacturer's Part Number *\n");
831 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
832 "* 91 Revision Code *");
833 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
834 "* 93 Manufacturing Date *");
835 printf("%-3d-%3d: ", 95, 98);
837 for (i = 0; i < 4; i++)
838 printf("%02x", spd->sernum[i]);
840 printf("* 95 Assembly Serial Number *\n");
842 printf("%-3d-%3d: ", 99, 127);
844 for (i = 0; i < 27; i++)
845 printf("%02x", spd->mspec[i]);
847 printf("* 99 Manufacturer Specific Data *\n");
851 #ifdef CONFIG_FSL_DDR2
852 void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
856 printf("%-3d : %02x %s\n", 0, spd->info_size,
857 " spd->info_size, * 0 # bytes written into serial memory *");
858 printf("%-3d : %02x %s\n", 1, spd->chip_size,
859 " spd->chip_size, * 1 Total # bytes of SPD memory device *");
860 printf("%-3d : %02x %s\n", 2, spd->mem_type,
861 " spd->mem_type, * 2 Fundamental memory type *");
862 printf("%-3d : %02x %s\n", 3, spd->nrow_addr,
863 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *");
864 printf("%-3d : %02x %s\n", 4, spd->ncol_addr,
865 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *");
866 printf("%-3d : %02x %s\n", 5, spd->mod_ranks,
867 " spd->mod_ranks * 5 # of Module Rows on this assembly *");
868 printf("%-3d : %02x %s\n", 6, spd->dataw,
869 " spd->dataw, * 6 Data Width of this assembly *");
870 printf("%-3d : %02x %s\n", 7, spd->res_7,
871 " spd->res_7, * 7 Reserved *");
872 printf("%-3d : %02x %s\n", 8, spd->voltage,
873 " spd->voltage, * 8 Voltage intf std of this assembly *");
874 printf("%-3d : %02x %s\n", 9, spd->clk_cycle,
875 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *");
876 printf("%-3d : %02x %s\n", 10, spd->clk_access,
877 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *");
878 printf("%-3d : %02x %s\n", 11, spd->config,
879 " spd->config, * 11 DIMM Configuration type *");
880 printf("%-3d : %02x %s\n", 12, spd->refresh,
881 " spd->refresh, * 12 Refresh Rate/Type *");
882 printf("%-3d : %02x %s\n", 13, spd->primw,
883 " spd->primw, * 13 Primary SDRAM Width *");
884 printf("%-3d : %02x %s\n", 14, spd->ecw,
885 " spd->ecw, * 14 Error Checking SDRAM width *");
886 printf("%-3d : %02x %s\n", 15, spd->res_15,
887 " spd->res_15, * 15 Reserved *");
888 printf("%-3d : %02x %s\n", 16, spd->burstl,
889 " spd->burstl, * 16 Burst Lengths Supported *");
890 printf("%-3d : %02x %s\n", 17, spd->nbanks,
891 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *");
892 printf("%-3d : %02x %s\n", 18, spd->cas_lat,
893 " spd->cas_lat, * 18 CAS# Latencies Supported *");
894 printf("%-3d : %02x %s\n", 19, spd->mech_char,
895 " spd->mech_char, * 19 Mechanical Characteristics *");
896 printf("%-3d : %02x %s\n", 20, spd->dimm_type,
897 " spd->dimm_type, * 20 DIMM type *");
898 printf("%-3d : %02x %s\n", 21, spd->mod_attr,
899 " spd->mod_attr, * 21 SDRAM Module Attributes *");
900 printf("%-3d : %02x %s\n", 22, spd->dev_attr,
901 " spd->dev_attr, * 22 SDRAM Device Attributes *");
902 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2,
903 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *");
904 printf("%-3d : %02x %s\n", 24, spd->clk_access2,
905 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
906 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3,
907 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *");
908 printf("%-3d : %02x %s\n", 26, spd->clk_access3,
909 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
910 printf("%-3d : %02x %s\n", 27, spd->trp,
911 " spd->trp, * 27 Min Row Precharge Time (tRP)*");
912 printf("%-3d : %02x %s\n", 28, spd->trrd,
913 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *");
914 printf("%-3d : %02x %s\n", 29, spd->trcd,
915 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *");
916 printf("%-3d : %02x %s\n", 30, spd->tras,
917 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *");
918 printf("%-3d : %02x %s\n", 31, spd->rank_dens,
919 " spd->rank_dens, * 31 Density of each rank on module *");
920 printf("%-3d : %02x %s\n", 32, spd->ca_setup,
921 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *");
922 printf("%-3d : %02x %s\n", 33, spd->ca_hold,
923 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *");
924 printf("%-3d : %02x %s\n", 34, spd->data_setup,
925 " spd->data_setup, * 34 Data signal input setup time *");
926 printf("%-3d : %02x %s\n", 35, spd->data_hold,
927 " spd->data_hold, * 35 Data signal input hold time *");
928 printf("%-3d : %02x %s\n", 36, spd->twr,
929 " spd->twr, * 36 Write Recovery time tWR *");
930 printf("%-3d : %02x %s\n", 37, spd->twtr,
931 " spd->twtr, * 37 Int write to read delay tWTR *");
932 printf("%-3d : %02x %s\n", 38, spd->trtp,
933 " spd->trtp, * 38 Int read to precharge delay tRTP *");
934 printf("%-3d : %02x %s\n", 39, spd->mem_probe,
935 " spd->mem_probe, * 39 Mem analysis probe characteristics *");
936 printf("%-3d : %02x %s\n", 40, spd->trctrfc_ext,
937 " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
938 printf("%-3d : %02x %s\n", 41, spd->trc,
939 " spd->trc, * 41 Min Active to Auto refresh time tRC *");
940 printf("%-3d : %02x %s\n", 42, spd->trfc,
941 " spd->trfc, * 42 Min Auto to Active period tRFC *");
942 printf("%-3d : %02x %s\n", 43, spd->tckmax,
943 " spd->tckmax, * 43 Max device cycle time tCKmax *");
944 printf("%-3d : %02x %s\n", 44, spd->tdqsq,
945 " spd->tdqsq, * 44 Max DQS to DQ skew *");
946 printf("%-3d : %02x %s\n", 45, spd->tqhs,
947 " spd->tqhs, * 45 Max Read DataHold skew tQHS *");
948 printf("%-3d : %02x %s\n", 46, spd->pll_relock,
949 " spd->pll_relock, * 46 PLL Relock time *");
950 printf("%-3d : %02x %s\n", 47, spd->Tcasemax,
951 " spd->Tcasemax, * 47 Tcasemax *");
952 printf("%-3d : %02x %s\n", 48, spd->psiTAdram,
953 " spd->psiTAdram, * 48 Thermal Resistance of DRAM Package "
954 "from Top (Case) to Ambient (Psi T-A DRAM) *");
955 printf("%-3d : %02x %s\n", 49, spd->dt0_mode,
956 " spd->dt0_mode, * 49 DRAM Case Temperature Rise from "
957 "Ambient due to Activate-Precharge/Mode Bits "
958 "(DT0/Mode Bits) *)");
959 printf("%-3d : %02x %s\n", 50, spd->dt2n_dt2q,
960 " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from "
961 "Ambient due to Precharge/Quiet Standby "
963 printf("%-3d : %02x %s\n", 51, spd->dt2p,
964 " spd->dt2p, * 51 DRAM Case Temperature Rise from "
965 "Ambient due to Precharge Power-Down (DT2P) *");
966 printf("%-3d : %02x %s\n", 52, spd->dt3n,
967 " spd->dt3n, * 52 DRAM Case Temperature Rise from "
968 "Ambient due to Active Standby (DT3N) *");
969 printf("%-3d : %02x %s\n", 53, spd->dt3pfast,
970 " spd->dt3pfast, * 53 DRAM Case Temperature Rise from "
971 "Ambient due to Active Power-Down with Fast PDN Exit "
973 printf("%-3d : %02x %s\n", 54, spd->dt3pslow,
974 " spd->dt3pslow, * 54 DRAM Case Temperature Rise from "
975 "Ambient due to Active Power-Down with Slow PDN Exit "
977 printf("%-3d : %02x %s\n", 55, spd->dt4r_dt4r4w,
978 " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
979 "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
980 "(DT4R/DT4R4W Mode Bit) *");
981 printf("%-3d : %02x %s\n", 56, spd->dt5b,
982 " spd->dt5b, * 56 DRAM Case Temperature Rise from "
983 "Ambient due to Burst Refresh (DT5B) *");
984 printf("%-3d : %02x %s\n", 57, spd->dt7,
985 " spd->dt7, * 57 DRAM Case Temperature Rise from "
986 "Ambient due to Bank Interleave Reads with "
987 "Auto-Precharge (DT7) *");
988 printf("%-3d : %02x %s\n", 58, spd->psiTApll,
989 " spd->psiTApll, * 58 Thermal Resistance of PLL Package form"
990 " Top (Case) to Ambient (Psi T-A PLL) *");
991 printf("%-3d : %02x %s\n", 59, spd->psiTAreg,
992 " spd->psiTAreg, * 59 Thermal Reisitance of Register Package"
993 " from Top (Case) to Ambient (Psi T-A Register) *");
994 printf("%-3d : %02x %s\n", 60, spd->dtpllactive,
995 " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
996 "Ambient due to PLL Active (DT PLL Active) *");
997 printf("%-3d : %02x %s\n", 61, spd->dtregact,
999 "* 61 Register Case Temperature Rise from Ambient due to "
1000 "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
1001 printf("%-3d : %02x %s\n", 62, spd->spd_rev,
1002 " spd->spd_rev, * 62 SPD Data Revision Code *");
1003 printf("%-3d : %02x %s\n", 63, spd->cksum,
1004 " spd->cksum, * 63 Checksum for bytes 0-62 *");
1006 printf("%-3d-%3d: ", 64, 71);
1008 for (i = 0; i < 8; i++)
1009 printf("%02x", spd->mid[i]);
1011 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1013 printf("%-3d : %02x %s\n", 72, spd->mloc,
1014 " spd->mloc, * 72 Manufacturing Location *");
1016 printf("%-3d-%3d: >>", 73, 90);
1017 for (i = 0; i < 18; i++)
1018 printf("%c", spd->mpart[i]);
1021 printf("<<* 73 Manufacturer's Part Number *\n");
1023 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1024 "* 91 Revision Code *");
1025 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1026 "* 93 Manufacturing Date *");
1027 printf("%-3d-%3d: ", 95, 98);
1029 for (i = 0; i < 4; i++)
1030 printf("%02x", spd->sernum[i]);
1032 printf("* 95 Assembly Serial Number *\n");
1034 printf("%-3d-%3d: ", 99, 127);
1035 for (i = 0; i < 27; i++)
1036 printf("%02x", spd->mspec[i]);
1039 printf("* 99 Manufacturer Specific Data *\n");
1043 #ifdef CONFIG_FSL_DDR3
1044 void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
1048 /* General Section: Bytes 0-59 */
1050 #define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, y);
1051 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1052 printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1054 PRINT_NXS(0, spd->info_size_crc,
1055 "info_size_crc bytes written into serial memory, "
1057 PRINT_NXS(1, spd->spd_rev,
1058 "spd_rev SPD Revision");
1059 PRINT_NXS(2, spd->mem_type,
1060 "mem_type Key Byte / DRAM Device Type");
1061 PRINT_NXS(3, spd->module_type,
1062 "module_type Key Byte / Module Type");
1063 PRINT_NXS(4, spd->density_banks,
1064 "density_banks SDRAM Density and Banks");
1065 PRINT_NXS(5, spd->addressing,
1066 "addressing SDRAM Addressing");
1067 PRINT_NXS(6, spd->module_vdd,
1068 "module_vdd Module Nominal Voltage, VDD");
1069 PRINT_NXS(7, spd->organization,
1070 "organization Module Organization");
1071 PRINT_NXS(8, spd->bus_width,
1072 "bus_width Module Memory Bus Width");
1073 PRINT_NXS(9, spd->ftb_div,
1074 "ftb_div Fine Timebase (FTB) Dividend / Divisor");
1075 PRINT_NXS(10, spd->mtb_dividend,
1076 "mtb_dividend Medium Timebase (MTB) Dividend");
1077 PRINT_NXS(11, spd->mtb_divisor,
1078 "mtb_divisor Medium Timebase (MTB) Divisor");
1079 PRINT_NXS(12, spd->tCK_min,
1080 "tCK_min SDRAM Minimum Cycle Time");
1081 PRINT_NXS(13, spd->res_13,
1083 PRINT_NXS(14, spd->caslat_lsb,
1084 "caslat_lsb CAS Latencies Supported, LSB");
1085 PRINT_NXS(15, spd->caslat_msb,
1086 "caslat_msb CAS Latencies Supported, MSB");
1087 PRINT_NXS(16, spd->tAA_min,
1088 "tAA_min Min CAS Latency Time");
1089 PRINT_NXS(17, spd->tWR_min,
1090 "tWR_min Min Write REcovery Time");
1091 PRINT_NXS(18, spd->tRCD_min,
1092 "tRCD_min Min RAS# to CAS# Delay Time");
1093 PRINT_NXS(19, spd->tRRD_min,
1094 "tRRD_min Min Row Active to Row Active Delay Time");
1095 PRINT_NXS(20, spd->tRP_min,
1096 "tRP_min Min Row Precharge Delay Time");
1097 PRINT_NXS(21, spd->tRAS_tRC_ext,
1098 "tRAS_tRC_ext Upper Nibbles for tRAS and tRC");
1099 PRINT_NXS(22, spd->tRAS_min_lsb,
1100 "tRAS_min_lsb Min Active to Precharge Delay Time, LSB");
1101 PRINT_NXS(23, spd->tRC_min_lsb,
1102 "tRC_min_lsb Min Active to Active/Refresh Delay Time, LSB");
1103 PRINT_NXS(24, spd->tRFC_min_lsb,
1104 "tRFC_min_lsb Min Refresh Recovery Delay Time LSB");
1105 PRINT_NXS(25, spd->tRFC_min_msb,
1106 "tRFC_min_msb Min Refresh Recovery Delay Time MSB");
1107 PRINT_NXS(26, spd->tWTR_min,
1108 "tWTR_min Min Internal Write to Read Command Delay Time");
1109 PRINT_NXS(27, spd->tRTP_min,
1111 "Min Internal Read to Precharge Command Delay Time");
1112 PRINT_NXS(28, spd->tFAW_msb,
1113 "tFAW_msb Upper Nibble for tFAW");
1114 PRINT_NXS(29, spd->tFAW_min,
1115 "tFAW_min Min Four Activate Window Delay Time");
1116 PRINT_NXS(30, spd->opt_features,
1117 "opt_features SDRAM Optional Features");
1118 PRINT_NXS(31, spd->therm_ref_opt,
1119 "therm_ref_opt SDRAM Thermal and Refresh Opts");
1120 PRINT_NXS(32, spd->therm_sensor,
1121 "therm_sensor SDRAM Thermal Sensor");
1122 PRINT_NXS(33, spd->device_type,
1123 "device_type SDRAM Device Type");
1124 PRINT_NXS(34, spd->fine_tCK_min,
1125 "fine_tCK_min Fine offset for tCKmin");
1126 PRINT_NXS(35, spd->fine_tAA_min,
1127 "fine_tAA_min Fine offset for tAAmin");
1128 PRINT_NXS(36, spd->fine_tRCD_min,
1129 "fine_tRCD_min Fine offset for tRCDmin");
1130 PRINT_NXS(37, spd->fine_tRP_min,
1131 "fine_tRP_min Fine offset for tRPmin");
1132 PRINT_NXS(38, spd->fine_tRC_min,
1133 "fine_tRC_min Fine offset for tRCmin");
1135 printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */
1137 for (i = 39; i <= 59; i++)
1138 printf("%02x ", spd->res_39_59[i - 39]);
1142 switch (spd->module_type) {
1143 case 0x02: /* UDIMM */
1144 case 0x03: /* SO-DIMM */
1145 case 0x04: /* Micro-DIMM */
1146 case 0x06: /* Mini-UDIMM */
1147 PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
1148 "mod_height (Unbuffered) Module Nominal Height");
1149 PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
1150 "mod_thickness (Unbuffered) Module Maximum Thickness");
1151 PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
1152 "ref_raw_card (Unbuffered) Reference Raw Card Used");
1153 PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
1154 "addr_mapping (Unbuffered) Address mapping from "
1155 "Edge Connector to DRAM");
1157 case 0x01: /* RDIMM */
1158 case 0x05: /* Mini-RDIMM */
1159 PRINT_NXS(60, spd->mod_section.registered.mod_height,
1160 "mod_height (Registered) Module Nominal Height");
1161 PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
1162 "mod_thickness (Registered) Module Maximum Thickness");
1163 PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
1164 "ref_raw_card (Registered) Reference Raw Card Used");
1165 PRINT_NXS(63, spd->mod_section.registered.modu_attr,
1166 "modu_attr (Registered) DIMM Module Attributes");
1167 PRINT_NXS(64, spd->mod_section.registered.thermal,
1168 "thermal (Registered) Thermal Heat "
1169 "Spreader Solution");
1170 PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
1171 "reg_id_lo (Registered) Register Manufacturer ID "
1173 PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
1174 "reg_id_hi (Registered) Register Manufacturer ID "
1176 PRINT_NXS(67, spd->mod_section.registered.reg_rev,
1177 "reg_rev (Registered) Register "
1179 PRINT_NXS(68, spd->mod_section.registered.reg_type,
1180 "reg_type (Registered) Register Type");
1181 for (i = 69; i <= 76; i++) {
1182 printf("%-3d : %02x rcw[%d]\n", i,
1183 spd->mod_section.registered.rcw[i-69], i-69);
1187 /* Module-specific Section, Unsupported Module Type */
1188 printf("%-3d-%3d: ", 60, 116);
1190 for (i = 60; i <= 116; i++)
1191 printf("%02x", spd->mod_section.uc[i - 60]);
1196 /* Unique Module ID: Bytes 117-125 */
1197 PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1198 PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1199 PRINT_NXS(119, spd->mloc, "Mfg Location");
1200 PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
1202 printf("%-3d-%3d: ", 122, 125);
1204 for (i = 122; i <= 125; i++)
1205 printf("%02x ", spd->sernum[i - 122]);
1206 printf(" Module Serial Number\n");
1208 /* CRC: Bytes 126-127 */
1209 PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC");
1211 /* Other Manufacturer Fields and User Space: Bytes 128-255 */
1212 printf("%-3d-%3d: ", 128, 145);
1213 for (i = 128; i <= 145; i++)
1214 printf("%02x ", spd->mpart[i - 128]);
1215 printf(" Mfg's Module Part Number\n");
1217 PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
1218 "Module Revision code");
1220 PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1221 PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1223 printf("%-3d-%3d: ", 150, 175);
1224 for (i = 150; i <= 175; i++)
1225 printf("%02x ", spd->msd[i - 150]);
1226 printf(" Mfg's Specific Data\n");
1228 printf("%-3d-%3d: ", 176, 255);
1229 for (i = 176; i <= 255; i++)
1230 printf("%02x", spd->cust[i - 176]);
1231 printf(" Mfg's Specific Data\n");
1236 static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1238 #if defined(CONFIG_FSL_DDR1)
1240 #elif defined(CONFIG_FSL_DDR2)
1242 #elif defined(CONFIG_FSL_DDR3)
1247 static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1248 unsigned int ctrl_mask,
1249 unsigned int dimm_mask,
1250 unsigned int do_mask)
1252 unsigned int i, j, retval;
1254 /* STEP 1: DIMM SPD data */
1255 if (do_mask & STEP_GET_SPD) {
1256 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1257 if (!(ctrl_mask & (1 << i)))
1260 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1261 if (!(dimm_mask & (1 << j)))
1264 printf("SPD info: Controller=%u "
1267 &(pinfo->spd_installed_dimms[i][j]));
1275 /* STEP 2: DIMM Parameters */
1276 if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
1277 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1278 if (!(ctrl_mask & (1 << i)))
1280 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1281 if (!(dimm_mask & (1 << j)))
1283 printf("DIMM parameters: Controller=%u "
1285 print_dimm_parameters(
1286 &(pinfo->dimm_params[i][j]));
1294 /* STEP 3: Common Parameters */
1295 if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
1296 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1297 if (!(ctrl_mask & (1 << i)))
1299 printf("\"lowest common\" DIMM parameters: "
1300 "Controller=%u\n", i);
1301 print_lowest_common_dimm_parameters(
1302 &pinfo->common_timing_params[i]);
1308 /* STEP 4: User Configuration Options */
1309 if (do_mask & STEP_GATHER_OPTS) {
1310 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1311 if (!(ctrl_mask & (1 << i)))
1313 printf("User Config Options: Controller=%u\n", i);
1314 print_memctl_options(&pinfo->memctl_opts[i]);
1320 /* STEP 5: Address assignment */
1321 if (do_mask & STEP_ASSIGN_ADDRESSES) {
1322 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1323 if (!(ctrl_mask & (1 << i)))
1325 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1326 printf("Address Assignment: Controller=%u "
1328 printf("Don't have this functionality yet\n");
1335 /* STEP 6: computed controller register values */
1336 if (do_mask & STEP_COMPUTE_REGS) {
1337 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1338 if (!(ctrl_mask & (1 << i)))
1340 printf("Computed Register Values: Controller=%u\n", i);
1341 print_fsl_memctl_config_regs(
1342 &pinfo->fsl_ddr_config_reg[i]);
1343 retval = check_fsl_memctl_config_regs(
1344 &pinfo->fsl_ddr_config_reg[i]);
1346 printf("check_fsl_memctl_config_regs "
1347 "result = %u\n", retval);
1355 struct data_strings {
1356 const char *data_name;
1357 unsigned int step_mask;
1358 unsigned int dimm_number_required;
1361 #define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
1363 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
1365 unsigned long long ddrsize;
1366 const char *prompt = "FSL DDR>";
1367 char buffer[CONFIG_SYS_CBSIZE];
1368 char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
1370 unsigned int next_step = STEP_GET_SPD;
1371 static const struct data_strings options[] = {
1372 DATA_OPTIONS(spd, STEP_GET_SPD, 1),
1373 DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
1374 DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
1375 DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
1376 DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
1377 DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
1379 static const unsigned int n_opts = ARRAY_SIZE(options);
1380 const char *usage = {
1382 "print print SPD and intermediate computed data\n"
1383 "reset reboot machine\n"
1384 "recompute reload SPD and options to default and recompute regs\n"
1385 "edit modify spd, parameter, or option\n"
1386 "compute recompute registers from current next_step to end\n"
1387 "next_step shows current next_step\n"
1388 "help this message\n"
1389 "go program the memory controller and continue with u-boot\n"
1393 * The strategy for next_step is that it points to the next
1394 * step in the computation process that needs to be done.
1398 * No need to worry for buffer overflow here in
1399 * this function; readline() maxes out at CFG_CBSIZE
1401 readline_into_buffer(prompt, buffer);
1402 argc = parse_line(buffer, argv);
1407 if (strcmp(argv[0], "help") == 0) {
1412 if (strcmp(argv[0], "next_step") == 0) {
1413 printf("next_step = 0x%02X (%s)\n",
1415 step_to_string(next_step));
1419 if (strcmp(argv[0], "edit") == 0) {
1421 unsigned int error = 0;
1422 unsigned int step_mask = 0;
1423 unsigned int ctlr_mask = 0;
1424 unsigned int dimm_mask = 0;
1425 char *p_element = NULL;
1426 char *p_value = NULL;
1427 unsigned int dimm_number_required = 0;
1428 unsigned int ctrl_num;
1429 unsigned int dimm_num;
1430 unsigned int matched = 0;
1433 /* Only the element and value must be last */
1434 printf("edit <c#> <d#> "
1435 "<spd|dimmparms|commonparms|opts|"
1436 "addresses|regs> <element> <value>\n");
1437 printf("for spd, specify byte number for "
1442 for (i = 1; i < argc - 2; i++) {
1443 for (j = 0; j < n_opts; j++) {
1444 if (strcmp(options[j].data_name,
1447 step_mask |= options[j].step_mask;
1448 dimm_number_required =
1449 options[j].dimm_number_required;
1457 if (argv[i][0] == 'c') {
1458 char c = argv[i][1];
1460 ctlr_mask |= 1 << (c - '0');
1464 if (argv[i][0] == 'd') {
1465 char c = argv[i][1];
1467 dimm_mask |= 1 << (c - '0');
1471 printf("unknown arg %s\n", argv[i]);
1482 /* Check arguments */
1484 /* ERROR: If no steps were found */
1485 if (step_mask == 0) {
1486 printf("Error: No valid steps were specified "
1491 /* ERROR: If multiple steps were found */
1492 if (step_mask & (step_mask - 1)) {
1493 printf("Error: Multiple steps specified in "
1498 /* ERROR: Controller not specified */
1499 if (ctlr_mask == 0) {
1500 printf("Error: controller number not "
1501 "specified or no element and "
1502 "value specified\n");
1506 if (ctlr_mask & (ctlr_mask - 1)) {
1507 printf("Error: multiple controllers "
1508 "specified, %X\n", ctlr_mask);
1512 /* ERROR: DIMM number not specified */
1513 if (dimm_number_required && dimm_mask == 0) {
1514 printf("Error: DIMM number number not "
1515 "specified or no element and "
1516 "value specified\n");
1520 if (dimm_mask & (dimm_mask - 1)) {
1521 printf("Error: multipled DIMMs specified\n");
1525 p_element = argv[argc - 2];
1526 p_value = argv[argc - 1];
1528 ctrl_num = __ilog2(ctlr_mask);
1529 dimm_num = __ilog2(dimm_mask);
1531 switch (step_mask) {
1534 unsigned int element_num;
1537 element_num = simple_strtoul(p_element,
1539 value = simple_strtoul(p_value,
1541 fsl_ddr_spd_edit(pinfo,
1546 next_step = STEP_COMPUTE_DIMM_PARMS;
1550 case STEP_COMPUTE_DIMM_PARMS:
1551 fsl_ddr_dimm_parameters_edit(
1552 pinfo, ctrl_num, dimm_num,
1553 p_element, p_value);
1554 next_step = STEP_COMPUTE_COMMON_PARMS;
1557 case STEP_COMPUTE_COMMON_PARMS:
1558 lowest_common_dimm_parameters_edit(pinfo,
1559 ctrl_num, p_element, p_value);
1560 next_step = STEP_GATHER_OPTS;
1563 case STEP_GATHER_OPTS:
1564 fsl_ddr_options_edit(pinfo, ctrl_num,
1565 p_element, p_value);
1566 next_step = STEP_ASSIGN_ADDRESSES;
1569 case STEP_ASSIGN_ADDRESSES:
1570 printf("editing of address assignment "
1571 "not yet implemented\n");
1574 case STEP_COMPUTE_REGS:
1576 fsl_ddr_regs_edit(pinfo,
1580 next_step = STEP_PROGRAM_REGS;
1585 printf("programming error\n");
1593 if (strcmp(argv[0], "reset") == 0) {
1596 * Args don't seem to matter because this
1599 do_reset(NULL, 0, 0, NULL);
1602 if (strcmp(argv[0], "recompute") == 0) {
1604 * Recalculate everything, starting with
1605 * loading SPD EEPROM from DIMMs
1607 next_step = STEP_GET_SPD;
1608 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
1612 if (strcmp(argv[0], "compute") == 0) {
1614 * Compute rest of steps starting at
1615 * the current next_step/
1617 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
1621 if (strcmp(argv[0], "print") == 0) {
1623 unsigned int error = 0;
1624 unsigned int step_mask = 0;
1625 unsigned int ctlr_mask = 0;
1626 unsigned int dimm_mask = 0;
1627 unsigned int matched = 0;
1630 printf("print [c<n>] [d<n>] [spd] [dimmparms] "
1631 "[commonparms] [opts] [addresses] [regs]\n");
1635 for (i = 1; i < argc; i++) {
1636 for (j = 0; j < n_opts; j++) {
1637 if (strcmp(options[j].data_name,
1640 step_mask |= options[j].step_mask;
1648 if (argv[i][0] == 'c') {
1649 char c = argv[i][1];
1651 ctlr_mask |= 1 << (c - '0');
1655 if (argv[i][0] == 'd') {
1656 char c = argv[i][1];
1658 dimm_mask |= 1 << (c - '0');
1662 printf("unknown arg %s\n", argv[i]);
1671 /* If no particular controller was found, print all */
1675 /* If no particular dimm was found, print all dimms. */
1679 /* If no steps were found, print all steps. */
1681 step_mask = STEP_ALL;
1683 fsl_ddr_printinfo(pinfo, ctlr_mask,
1684 dimm_mask, step_mask);
1688 if (strcmp(argv[0], "go") == 0) {
1690 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
1694 printf("unknown command %s\n", argv[0]);
1697 debug("end of memory = %llu\n", (u64)ddrsize);