2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 #include <asm/fsl_ddr_sdram.h>
14 #if defined(CONFIG_FSL_DDR3)
16 compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
17 common_timing_params_t *outpdimm,
18 unsigned int number_of_dimms)
21 unsigned int tAAmin_ps = 0;
22 unsigned int tCKmin_X_ps = 0;
23 unsigned int common_caslat;
24 unsigned int caslat_actual;
25 unsigned int retry = 16;
27 const unsigned int mclk_ps = get_memory_clk_period_ps();
29 /* compute the common CAS latency supported between slots */
30 tmp = dimm_params[0].caslat_X;
31 for (i = 1; i < number_of_dimms; i++) {
32 if (dimm_params[i].n_ranks)
33 tmp &= dimm_params[i].caslat_X;
37 /* compute the max tAAmin tCKmin between slots */
38 for (i = 0; i < number_of_dimms; i++) {
39 tAAmin_ps = max(tAAmin_ps, dimm_params[i].tAA_ps);
40 tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
42 /* validate if the memory clk is in the range of dimms */
43 if (mclk_ps < tCKmin_X_ps) {
44 printf("DDR clock (MCLK cycle %u ps) is faster than "
45 "the slowest DIMM(s) (tCKmin %u ps) can support.\n",
46 mclk_ps, tCKmin_X_ps);
49 /* determine the acutal cas latency */
50 caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps;
51 /* check if the dimms support the CAS latency */
52 while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
56 /* once the caculation of caslat_actual is completed
57 * we must verify that this CAS latency value does not
58 * exceed tAAmax, which is 20 ns for all DDR3 speed grades
60 if (caslat_actual * mclk_ps > 20000) {
61 printf("The choosen cas latency %d is too large\n",
65 outpdimm->lowest_common_SPD_caslat = caslat_actual;
72 * compute_lowest_common_dimm_parameters()
74 * Determine the worst-case DIMM timing parameters from the set of DIMMs
75 * whose parameters have been computed into the array pointed to
79 compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
80 common_timing_params_t *outpdimm,
81 const unsigned int number_of_dimms)
85 unsigned int tCKmin_X_ps = 0;
86 unsigned int tCKmax_ps = 0xFFFFFFFF;
87 unsigned int tCKmax_max_ps = 0;
88 unsigned int tRCD_ps = 0;
89 unsigned int tRP_ps = 0;
90 unsigned int tRAS_ps = 0;
91 unsigned int tWR_ps = 0;
92 unsigned int tWTR_ps = 0;
93 unsigned int tRFC_ps = 0;
94 unsigned int tRRD_ps = 0;
95 unsigned int tRC_ps = 0;
96 unsigned int refresh_rate_ps = 0;
97 unsigned int tIS_ps = 0;
98 unsigned int tIH_ps = 0;
99 unsigned int tDS_ps = 0;
100 unsigned int tDH_ps = 0;
101 unsigned int tRTP_ps = 0;
102 unsigned int tDQSQ_max_ps = 0;
103 unsigned int tQHS_ps = 0;
105 unsigned int temp1, temp2;
106 unsigned int additive_latency = 0;
107 #if !defined(CONFIG_FSL_DDR3)
108 const unsigned int mclk_ps = get_memory_clk_period_ps();
109 unsigned int lowest_good_caslat;
112 debug("using mclk_ps = %u\n", mclk_ps);
116 for (i = 0; i < number_of_dimms; i++) {
118 * If there are no ranks on this DIMM,
119 * it probably doesn't exist, so skip it.
121 if (dimm_params[i].n_ranks == 0) {
125 if (dimm_params[i].n_ranks == 4 && i != 0) {
126 printf("Found Quad-rank DIMM in wrong bank, ignored."
127 " Software may not run as expected.\n");
133 * check if quad-rank DIMM is plugged if
134 * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
135 * Only the board with proper design is capable
137 #ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
138 if (dimm_params[i].n_ranks == 4 && \
139 CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
140 printf("Found Quad-rank DIMM, not able to support.");
146 * Find minimum tCKmax_ps to find fastest slow speed,
147 * i.e., this is the slowest the whole system can go.
149 tCKmax_ps = min(tCKmax_ps, dimm_params[i].tCKmax_ps);
151 /* Either find maximum value to determine slowest
152 * speed, delay, time, period, etc */
153 tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
154 tCKmax_max_ps = max(tCKmax_max_ps, dimm_params[i].tCKmax_ps);
155 tRCD_ps = max(tRCD_ps, dimm_params[i].tRCD_ps);
156 tRP_ps = max(tRP_ps, dimm_params[i].tRP_ps);
157 tRAS_ps = max(tRAS_ps, dimm_params[i].tRAS_ps);
158 tWR_ps = max(tWR_ps, dimm_params[i].tWR_ps);
159 tWTR_ps = max(tWTR_ps, dimm_params[i].tWTR_ps);
160 tRFC_ps = max(tRFC_ps, dimm_params[i].tRFC_ps);
161 tRRD_ps = max(tRRD_ps, dimm_params[i].tRRD_ps);
162 tRC_ps = max(tRC_ps, dimm_params[i].tRC_ps);
163 tIS_ps = max(tIS_ps, dimm_params[i].tIS_ps);
164 tIH_ps = max(tIH_ps, dimm_params[i].tIH_ps);
165 tDS_ps = max(tDS_ps, dimm_params[i].tDS_ps);
166 tDH_ps = max(tDH_ps, dimm_params[i].tDH_ps);
167 tRTP_ps = max(tRTP_ps, dimm_params[i].tRTP_ps);
168 tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps);
169 refresh_rate_ps = max(refresh_rate_ps,
170 dimm_params[i].refresh_rate_ps);
173 * Find maximum tDQSQ_max_ps to find slowest.
175 * FIXME: is finding the slowest value the correct
176 * strategy for this parameter?
178 tDQSQ_max_ps = max(tDQSQ_max_ps, dimm_params[i].tDQSQ_max_ps);
181 outpdimm->ndimms_present = number_of_dimms - temp1;
183 if (temp1 == number_of_dimms) {
184 debug("no dimms this memory controller\n");
188 outpdimm->tCKmin_X_ps = tCKmin_X_ps;
189 outpdimm->tCKmax_ps = tCKmax_ps;
190 outpdimm->tCKmax_max_ps = tCKmax_max_ps;
191 outpdimm->tRCD_ps = tRCD_ps;
192 outpdimm->tRP_ps = tRP_ps;
193 outpdimm->tRAS_ps = tRAS_ps;
194 outpdimm->tWR_ps = tWR_ps;
195 outpdimm->tWTR_ps = tWTR_ps;
196 outpdimm->tRFC_ps = tRFC_ps;
197 outpdimm->tRRD_ps = tRRD_ps;
198 outpdimm->tRC_ps = tRC_ps;
199 outpdimm->refresh_rate_ps = refresh_rate_ps;
200 outpdimm->tIS_ps = tIS_ps;
201 outpdimm->tIH_ps = tIH_ps;
202 outpdimm->tDS_ps = tDS_ps;
203 outpdimm->tDH_ps = tDH_ps;
204 outpdimm->tRTP_ps = tRTP_ps;
205 outpdimm->tDQSQ_max_ps = tDQSQ_max_ps;
206 outpdimm->tQHS_ps = tQHS_ps;
208 /* Determine common burst length for all DIMMs. */
210 for (i = 0; i < number_of_dimms; i++) {
211 if (dimm_params[i].n_ranks) {
212 temp1 &= dimm_params[i].burst_lengths_bitmask;
215 outpdimm->all_DIMMs_burst_lengths_bitmask = temp1;
217 /* Determine if all DIMMs registered buffered. */
219 for (i = 0; i < number_of_dimms; i++) {
220 if (dimm_params[i].n_ranks) {
221 if (dimm_params[i].registered_dimm) {
223 printf("Detected RDIMM %s\n",
224 dimm_params[i].mpart);
227 printf("Detected UDIMM %s\n",
228 dimm_params[i].mpart);
233 outpdimm->all_DIMMs_registered = 0;
234 outpdimm->all_DIMMs_unbuffered = 0;
235 if (temp1 && !temp2) {
236 outpdimm->all_DIMMs_registered = 1;
237 } else if (!temp1 && temp2) {
238 outpdimm->all_DIMMs_unbuffered = 1;
240 printf("ERROR: Mix of registered buffered and unbuffered "
241 "DIMMs detected!\n");
245 if (outpdimm->all_DIMMs_registered)
246 for (j = 0; j < 16; j++) {
247 outpdimm->rcw[j] = dimm_params[0].rcw[j];
248 for (i = 1; i < number_of_dimms; i++) {
249 if (!dimm_params[i].n_ranks)
251 if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
259 printf("ERROR: Mix different RDIMM detected!\n");
261 #if defined(CONFIG_FSL_DDR3)
262 if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
266 * Compute a CAS latency suitable for all DIMMs
268 * Strategy for SPD-defined latencies: compute only
269 * CAS latency defined by all DIMMs.
273 * Step 1: find CAS latency common to all DIMMs using bitwise
277 for (i = 0; i < number_of_dimms; i++) {
278 if (dimm_params[i].n_ranks) {
280 temp2 |= 1 << dimm_params[i].caslat_X;
281 temp2 |= 1 << dimm_params[i].caslat_X_minus_1;
282 temp2 |= 1 << dimm_params[i].caslat_X_minus_2;
284 * FIXME: If there was no entry for X-2 (X-1) in
285 * the SPD, then caslat_X_minus_2
286 * (caslat_X_minus_1) contains either 255 or
287 * 0xFFFFFFFF because that's what the glorious
288 * __ilog2 function returns for an input of 0.
289 * On 32-bit PowerPC, left shift counts with bit
290 * 26 set (that the value of 255 or 0xFFFFFFFF
291 * will have), cause the destination register to
292 * be 0. That is why this works.
299 * Step 2: check each common CAS latency against tCK of each
302 lowest_good_caslat = 0;
306 temp2 = __ilog2(temp1);
307 debug("checking common caslat = %u\n", temp2);
309 /* Check if this CAS latency will work on all DIMMs at tCK. */
310 for (i = 0; i < number_of_dimms; i++) {
311 if (!dimm_params[i].n_ranks) {
314 if (dimm_params[i].caslat_X == temp2) {
315 if (mclk_ps >= dimm_params[i].tCKmin_X_ps) {
316 debug("CL = %u ok on DIMM %u at tCK=%u"
317 " ps with its tCKmin_X_ps of %u\n",
319 dimm_params[i].tCKmin_X_ps);
326 if (dimm_params[i].caslat_X_minus_1 == temp2) {
327 unsigned int tCKmin_X_minus_1_ps
328 = dimm_params[i].tCKmin_X_minus_1_ps;
329 if (mclk_ps >= tCKmin_X_minus_1_ps) {
330 debug("CL = %u ok on DIMM %u at "
331 "tCK=%u ps with its "
332 "tCKmin_X_minus_1_ps of %u\n",
334 tCKmin_X_minus_1_ps);
341 if (dimm_params[i].caslat_X_minus_2 == temp2) {
342 unsigned int tCKmin_X_minus_2_ps
343 = dimm_params[i].tCKmin_X_minus_2_ps;
344 if (mclk_ps >= tCKmin_X_minus_2_ps) {
345 debug("CL = %u ok on DIMM %u at "
346 "tCK=%u ps with its "
347 "tCKmin_X_minus_2_ps of %u\n",
349 tCKmin_X_minus_2_ps);
358 lowest_good_caslat = temp2;
361 temp1 &= ~(1 << temp2);
364 debug("lowest common SPD-defined CAS latency = %u\n",
366 outpdimm->lowest_common_SPD_caslat = lowest_good_caslat;
370 * Compute a common 'de-rated' CAS latency.
372 * The strategy here is to find the *highest* dereated cas latency
373 * with the assumption that all of the DIMMs will support a dereated
374 * CAS latency higher than or equal to their lowest dereated value.
377 for (i = 0; i < number_of_dimms; i++) {
378 temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
380 outpdimm->highest_common_derated_caslat = temp1;
381 debug("highest common dereated CAS latency = %u\n", temp1);
382 #endif /* #if defined(CONFIG_FSL_DDR3) */
384 /* Determine if all DIMMs ECC capable. */
386 for (i = 0; i < number_of_dimms; i++) {
387 if (dimm_params[i].n_ranks &&
388 !(dimm_params[i].edc_config & EDC_ECC)) {
394 debug("all DIMMs ECC capable\n");
396 debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
398 outpdimm->all_DIMMs_ECC_capable = temp1;
400 #ifndef CONFIG_FSL_DDR3
401 /* FIXME: move to somewhere else to validate. */
402 if (mclk_ps > tCKmax_max_ps) {
403 printf("Warning: some of the installed DIMMs "
404 "can not operate this slowly.\n");
409 * Compute additive latency.
411 * For DDR1, additive latency should be 0.
413 * For DDR2, with ODT enabled, use "a value" less than ACTTORW,
414 * which comes from Trcd, and also note that:
415 * add_lat + caslat must be >= 4
417 * For DDR3, we use the AL=0
419 * When to use additive latency for DDR2:
421 * I. Because you are using CL=3 and need to do ODT on writes and
422 * want functionality.
423 * 1. Are you going to use ODT? (Does your board not have
424 * additional termination circuitry for DQ, DQS, DQS_,
425 * DM, RDQS, RDQS_ for x4/x8 configs?)
426 * 2. If so, is your lowest supported CL going to be 3?
427 * 3. If so, then you must set AL=1 because
429 * WL >= 3 for ODT on writes
438 * RL >= 3 for ODT on reads
441 * Since CL aren't usually less than 2, AL=0 is a minimum,
442 * so the WL-derived AL should be the -- FIXME?
444 * II. Because you are using auto-precharge globally and want to
445 * use additive latency (posted CAS) to get more bandwidth.
446 * 1. Are you going to use auto-precharge mode globally?
448 * Use addtivie latency and compute AL to be 1 cycle less than
449 * tRCD, i.e. the READ or WRITE command is in the cycle
450 * immediately following the ACTIVATE command..
452 * III. Because you feel like it or want to do some sort of
453 * degraded-performance experiment.
454 * 1. Do you just want to use additive latency because you feel
457 * Validation: AL is less than tRCD, and within the other
458 * read-to-precharge constraints.
461 additive_latency = 0;
463 #if defined(CONFIG_FSL_DDR2)
464 if (lowest_good_caslat < 4) {
465 additive_latency = (picos_to_mclk(tRCD_ps) > lowest_good_caslat)
466 ? picos_to_mclk(tRCD_ps) - lowest_good_caslat : 0;
467 if (mclk_to_picos(additive_latency) > tRCD_ps) {
468 additive_latency = picos_to_mclk(tRCD_ps);
469 debug("setting additive_latency to %u because it was "
470 " greater than tRCD_ps\n", additive_latency);
474 #elif defined(CONFIG_FSL_DDR3)
476 * The system will not use the global auto-precharge mode.
477 * However, it uses the page mode, so we set AL=0
479 additive_latency = 0;
483 * Validate additive latency
484 * FIXME: move to somewhere else to validate
488 if (mclk_to_picos(additive_latency) > tRCD_ps) {
489 printf("Error: invalid additive latency exceeds tRCD(min).\n");
494 * RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled
495 * WL = RL - 1; WL >= 3 for ODT_WL_CFG to be enabled
496 * ADD_LAT (the register) must be set to a value less
497 * than ACTTORW if WL = 1, then AL must be set to 1
498 * RD_TO_PRE (the register) must be set to a minimum
499 * tRTP + AL if AL is nonzero
503 * Additive latency will be applied only if the memctl option to
506 outpdimm->additive_latency = additive_latency;
508 debug("tCKmin_ps = %u\n", outpdimm->tCKmin_X_ps);
509 debug("tRCD_ps = %u\n", outpdimm->tRCD_ps);
510 debug("tRP_ps = %u\n", outpdimm->tRP_ps);
511 debug("tRAS_ps = %u\n", outpdimm->tRAS_ps);
512 debug("tWR_ps = %u\n", outpdimm->tWR_ps);
513 debug("tWTR_ps = %u\n", outpdimm->tWTR_ps);
514 debug("tRFC_ps = %u\n", outpdimm->tRFC_ps);
515 debug("tRRD_ps = %u\n", outpdimm->tRRD_ps);
516 debug("tRC_ps = %u\n", outpdimm->tRC_ps);