2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 #include <asm/fsl_ddr_sdram.h>
15 compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
16 common_timing_params_t *outpdimm,
17 unsigned int number_of_dimms)
20 unsigned int tAAmin_ps = 0;
21 unsigned int tCKmin_X_ps = 0;
22 unsigned int common_caslat;
23 unsigned int caslat_actual;
24 unsigned int retry = 16;
26 const unsigned int mclk_ps = get_memory_clk_period_ps();
28 /* compute the common CAS latency supported between slots */
29 tmp = dimm_params[0].caslat_X;
30 for (i = 1; i < number_of_dimms; i++)
31 tmp &= dimm_params[i].caslat_X;
34 /* compute the max tAAmin tCKmin between slots */
35 for (i = 0; i < number_of_dimms; i++) {
36 tAAmin_ps = max(tAAmin_ps, dimm_params[i].tAA_ps);
37 tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
39 /* validate if the memory clk is in the range of dimms */
40 if (mclk_ps < tCKmin_X_ps) {
41 printf("The DIMM max tCKmin is %d ps,"
42 "doesn't support the MCLK cycle %d ps\n",
43 tCKmin_X_ps, mclk_ps);
46 /* determine the acutal cas latency */
47 caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps;
48 /* check if the dimms support the CAS latency */
49 while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
53 /* once the caculation of caslat_actual is completed
54 * we must verify that this CAS latency value does not
55 * exceed tAAmax, which is 20 ns for all DDR3 speed grades
57 if (caslat_actual * mclk_ps > 20000) {
58 printf("The choosen cas latency %d is too large\n",
62 outpdimm->lowest_common_SPD_caslat = caslat_actual;
68 * compute_lowest_common_dimm_parameters()
70 * Determine the worst-case DIMM timing parameters from the set of DIMMs
71 * whose parameters have been computed into the array pointed to
75 compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
76 common_timing_params_t *outpdimm,
77 unsigned int number_of_dimms)
81 unsigned int tCKmin_X_ps = 0;
82 unsigned int tCKmax_ps = 0xFFFFFFFF;
83 unsigned int tCKmax_max_ps = 0;
84 unsigned int tRCD_ps = 0;
85 unsigned int tRP_ps = 0;
86 unsigned int tRAS_ps = 0;
87 unsigned int tWR_ps = 0;
88 unsigned int tWTR_ps = 0;
89 unsigned int tRFC_ps = 0;
90 unsigned int tRRD_ps = 0;
91 unsigned int tRC_ps = 0;
92 unsigned int refresh_rate_ps = 0;
93 unsigned int tIS_ps = 0;
94 unsigned int tIH_ps = 0;
95 unsigned int tDS_ps = 0;
96 unsigned int tDH_ps = 0;
97 unsigned int tRTP_ps = 0;
98 unsigned int tDQSQ_max_ps = 0;
99 unsigned int tQHS_ps = 0;
101 unsigned int temp1, temp2, temp3;
102 unsigned int additive_latency = 0;
103 #if !defined(CONFIG_FSL_DDR3)
104 const unsigned int mclk_ps = get_memory_clk_period_ps();
105 unsigned int lowest_good_caslat;
108 debug("using mclk_ps = %u\n", mclk_ps);
112 for (i = 0; i < number_of_dimms; i++) {
114 * If there are no ranks on this DIMM,
115 * it probably doesn't exist, so skip it.
117 if (dimm_params[i].n_ranks == 0) {
121 if (dimm_params[i].n_ranks == 4 && i != 0) {
122 printf("Found Quad-rank DIMM in wrong bank, ignored."
123 " Software may not run as expected.\n");
127 if (dimm_params[i].n_ranks == 4 && \
128 CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
129 printf("Found Quad-rank DIMM, not able to support.");
135 * Find minimum tCKmax_ps to find fastest slow speed,
136 * i.e., this is the slowest the whole system can go.
138 tCKmax_ps = min(tCKmax_ps, dimm_params[i].tCKmax_ps);
140 /* Either find maximum value to determine slowest
141 * speed, delay, time, period, etc */
142 tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
143 tCKmax_max_ps = max(tCKmax_max_ps, dimm_params[i].tCKmax_ps);
144 tRCD_ps = max(tRCD_ps, dimm_params[i].tRCD_ps);
145 tRP_ps = max(tRP_ps, dimm_params[i].tRP_ps);
146 tRAS_ps = max(tRAS_ps, dimm_params[i].tRAS_ps);
147 tWR_ps = max(tWR_ps, dimm_params[i].tWR_ps);
148 tWTR_ps = max(tWTR_ps, dimm_params[i].tWTR_ps);
149 tRFC_ps = max(tRFC_ps, dimm_params[i].tRFC_ps);
150 tRRD_ps = max(tRRD_ps, dimm_params[i].tRRD_ps);
151 tRC_ps = max(tRC_ps, dimm_params[i].tRC_ps);
152 tIS_ps = max(tIS_ps, dimm_params[i].tIS_ps);
153 tIH_ps = max(tIH_ps, dimm_params[i].tIH_ps);
154 tDS_ps = max(tDS_ps, dimm_params[i].tDS_ps);
155 tDH_ps = max(tDH_ps, dimm_params[i].tDH_ps);
156 tRTP_ps = max(tRTP_ps, dimm_params[i].tRTP_ps);
157 tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps);
158 refresh_rate_ps = max(refresh_rate_ps,
159 dimm_params[i].refresh_rate_ps);
162 * Find maximum tDQSQ_max_ps to find slowest.
164 * FIXME: is finding the slowest value the correct
165 * strategy for this parameter?
167 tDQSQ_max_ps = max(tDQSQ_max_ps, dimm_params[i].tDQSQ_max_ps);
170 outpdimm->ndimms_present = number_of_dimms - temp1;
172 if (temp1 == number_of_dimms) {
173 debug("no dimms this memory controller\n");
177 outpdimm->tCKmin_X_ps = tCKmin_X_ps;
178 outpdimm->tCKmax_ps = tCKmax_ps;
179 outpdimm->tCKmax_max_ps = tCKmax_max_ps;
180 outpdimm->tRCD_ps = tRCD_ps;
181 outpdimm->tRP_ps = tRP_ps;
182 outpdimm->tRAS_ps = tRAS_ps;
183 outpdimm->tWR_ps = tWR_ps;
184 outpdimm->tWTR_ps = tWTR_ps;
185 outpdimm->tRFC_ps = tRFC_ps;
186 outpdimm->tRRD_ps = tRRD_ps;
187 outpdimm->tRC_ps = tRC_ps;
188 outpdimm->refresh_rate_ps = refresh_rate_ps;
189 outpdimm->tIS_ps = tIS_ps;
190 outpdimm->tIH_ps = tIH_ps;
191 outpdimm->tDS_ps = tDS_ps;
192 outpdimm->tDH_ps = tDH_ps;
193 outpdimm->tRTP_ps = tRTP_ps;
194 outpdimm->tDQSQ_max_ps = tDQSQ_max_ps;
195 outpdimm->tQHS_ps = tQHS_ps;
197 /* Determine common burst length for all DIMMs. */
199 for (i = 0; i < number_of_dimms; i++) {
200 if (dimm_params[i].n_ranks) {
201 temp1 &= dimm_params[i].burst_lengths_bitmask;
204 outpdimm->all_DIMMs_burst_lengths_bitmask = temp1;
206 /* Determine if all DIMMs registered buffered. */
208 for (i = 0; i < number_of_dimms; i++) {
209 if (dimm_params[i].n_ranks) {
210 if (dimm_params[i].registered_dimm)
212 if (!dimm_params[i].registered_dimm)
217 outpdimm->all_DIMMs_registered = 0;
218 if (temp1 && !temp2) {
219 outpdimm->all_DIMMs_registered = 1;
222 outpdimm->all_DIMMs_unbuffered = 0;
223 if (!temp1 && temp2) {
224 outpdimm->all_DIMMs_unbuffered = 1;
228 if (!outpdimm->all_DIMMs_registered
229 && !outpdimm->all_DIMMs_unbuffered) {
230 printf("ERROR: Mix of registered buffered and unbuffered "
231 "DIMMs detected!\n");
235 if (outpdimm->all_DIMMs_registered)
236 for (j = 0; j < 16; j++) {
237 outpdimm->rcw[j] = dimm_params[0].rcw[j];
238 for (i = 1; i < number_of_dimms; i++)
239 if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
246 printf("ERROR: Mix different RDIMM detected!\n");
248 #if defined(CONFIG_FSL_DDR3)
249 if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
253 * Compute a CAS latency suitable for all DIMMs
255 * Strategy for SPD-defined latencies: compute only
256 * CAS latency defined by all DIMMs.
260 * Step 1: find CAS latency common to all DIMMs using bitwise
264 for (i = 0; i < number_of_dimms; i++) {
265 if (dimm_params[i].n_ranks) {
267 temp2 |= 1 << dimm_params[i].caslat_X;
268 temp2 |= 1 << dimm_params[i].caslat_X_minus_1;
269 temp2 |= 1 << dimm_params[i].caslat_X_minus_2;
271 * FIXME: If there was no entry for X-2 (X-1) in
272 * the SPD, then caslat_X_minus_2
273 * (caslat_X_minus_1) contains either 255 or
274 * 0xFFFFFFFF because that's what the glorious
275 * __ilog2 function returns for an input of 0.
276 * On 32-bit PowerPC, left shift counts with bit
277 * 26 set (that the value of 255 or 0xFFFFFFFF
278 * will have), cause the destination register to
279 * be 0. That is why this works.
286 * Step 2: check each common CAS latency against tCK of each
289 lowest_good_caslat = 0;
293 temp2 = __ilog2(temp1);
294 debug("checking common caslat = %u\n", temp2);
296 /* Check if this CAS latency will work on all DIMMs at tCK. */
297 for (i = 0; i < number_of_dimms; i++) {
298 if (!dimm_params[i].n_ranks) {
301 if (dimm_params[i].caslat_X == temp2) {
302 if (mclk_ps >= dimm_params[i].tCKmin_X_ps) {
303 debug("CL = %u ok on DIMM %u at tCK=%u"
304 " ps with its tCKmin_X_ps of %u\n",
306 dimm_params[i].tCKmin_X_ps);
313 if (dimm_params[i].caslat_X_minus_1 == temp2) {
314 unsigned int tCKmin_X_minus_1_ps
315 = dimm_params[i].tCKmin_X_minus_1_ps;
316 if (mclk_ps >= tCKmin_X_minus_1_ps) {
317 debug("CL = %u ok on DIMM %u at "
318 "tCK=%u ps with its "
319 "tCKmin_X_minus_1_ps of %u\n",
321 tCKmin_X_minus_1_ps);
328 if (dimm_params[i].caslat_X_minus_2 == temp2) {
329 unsigned int tCKmin_X_minus_2_ps
330 = dimm_params[i].tCKmin_X_minus_2_ps;
331 if (mclk_ps >= tCKmin_X_minus_2_ps) {
332 debug("CL = %u ok on DIMM %u at "
333 "tCK=%u ps with its "
334 "tCKmin_X_minus_2_ps of %u\n",
336 tCKmin_X_minus_2_ps);
345 lowest_good_caslat = temp2;
348 temp1 &= ~(1 << temp2);
351 debug("lowest common SPD-defined CAS latency = %u\n",
353 outpdimm->lowest_common_SPD_caslat = lowest_good_caslat;
357 * Compute a common 'de-rated' CAS latency.
359 * The strategy here is to find the *highest* dereated cas latency
360 * with the assumption that all of the DIMMs will support a dereated
361 * CAS latency higher than or equal to their lowest dereated value.
364 for (i = 0; i < number_of_dimms; i++) {
365 temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
367 outpdimm->highest_common_derated_caslat = temp1;
368 debug("highest common dereated CAS latency = %u\n", temp1);
369 #endif /* #if defined(CONFIG_FSL_DDR3) */
371 /* Determine if all DIMMs ECC capable. */
373 for (i = 0; i < number_of_dimms; i++) {
374 if (dimm_params[i].n_ranks && dimm_params[i].edc_config != 2) {
380 debug("all DIMMs ECC capable\n");
382 debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
384 outpdimm->all_DIMMs_ECC_capable = temp1;
386 #ifndef CONFIG_FSL_DDR3
387 /* FIXME: move to somewhere else to validate. */
388 if (mclk_ps > tCKmax_max_ps) {
389 printf("Warning: some of the installed DIMMs "
390 "can not operate this slowly.\n");
395 * Compute additive latency.
397 * For DDR1, additive latency should be 0.
399 * For DDR2, with ODT enabled, use "a value" less than ACTTORW,
400 * which comes from Trcd, and also note that:
401 * add_lat + caslat must be >= 4
403 * For DDR3, we use the AL=0
405 * When to use additive latency for DDR2:
407 * I. Because you are using CL=3 and need to do ODT on writes and
408 * want functionality.
409 * 1. Are you going to use ODT? (Does your board not have
410 * additional termination circuitry for DQ, DQS, DQS_,
411 * DM, RDQS, RDQS_ for x4/x8 configs?)
412 * 2. If so, is your lowest supported CL going to be 3?
413 * 3. If so, then you must set AL=1 because
415 * WL >= 3 for ODT on writes
424 * RL >= 3 for ODT on reads
427 * Since CL aren't usually less than 2, AL=0 is a minimum,
428 * so the WL-derived AL should be the -- FIXME?
430 * II. Because you are using auto-precharge globally and want to
431 * use additive latency (posted CAS) to get more bandwidth.
432 * 1. Are you going to use auto-precharge mode globally?
434 * Use addtivie latency and compute AL to be 1 cycle less than
435 * tRCD, i.e. the READ or WRITE command is in the cycle
436 * immediately following the ACTIVATE command..
438 * III. Because you feel like it or want to do some sort of
439 * degraded-performance experiment.
440 * 1. Do you just want to use additive latency because you feel
443 * Validation: AL is less than tRCD, and within the other
444 * read-to-precharge constraints.
447 additive_latency = 0;
449 #if defined(CONFIG_FSL_DDR2)
450 if (lowest_good_caslat < 4) {
451 additive_latency = picos_to_mclk(tRCD_ps) - lowest_good_caslat;
452 if (mclk_to_picos(additive_latency) > tRCD_ps) {
453 additive_latency = picos_to_mclk(tRCD_ps);
454 debug("setting additive_latency to %u because it was "
455 " greater than tRCD_ps\n", additive_latency);
459 #elif defined(CONFIG_FSL_DDR3)
461 * The system will not use the global auto-precharge mode.
462 * However, it uses the page mode, so we set AL=0
464 additive_latency = 0;
468 * Validate additive latency
469 * FIXME: move to somewhere else to validate
473 if (mclk_to_picos(additive_latency) > tRCD_ps) {
474 printf("Error: invalid additive latency exceeds tRCD(min).\n");
479 * RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled
480 * WL = RL - 1; WL >= 3 for ODT_WL_CFG to be enabled
481 * ADD_LAT (the register) must be set to a value less
482 * than ACTTORW if WL = 1, then AL must be set to 1
483 * RD_TO_PRE (the register) must be set to a minimum
484 * tRTP + AL if AL is nonzero
488 * Additive latency will be applied only if the memctl option to
491 outpdimm->additive_latency = additive_latency;