2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 #include <asm/fsl_ddr_sdram.h>
14 #if defined(CONFIG_FSL_DDR3)
16 compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
17 common_timing_params_t *outpdimm,
18 unsigned int number_of_dimms)
21 unsigned int taamin_ps = 0;
22 unsigned int tckmin_x_ps = 0;
23 unsigned int common_caslat;
24 unsigned int caslat_actual;
25 unsigned int retry = 16;
27 const unsigned int mclk_ps = get_memory_clk_period_ps();
29 /* compute the common CAS latency supported between slots */
30 tmp = dimm_params[0].caslat_x;
31 for (i = 1; i < number_of_dimms; i++) {
32 if (dimm_params[i].n_ranks)
33 tmp &= dimm_params[i].caslat_x;
37 /* compute the max tAAmin tCKmin between slots */
38 for (i = 0; i < number_of_dimms; i++) {
39 taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
40 tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
42 /* validate if the memory clk is in the range of dimms */
43 if (mclk_ps < tckmin_x_ps) {
44 printf("DDR clock (MCLK cycle %u ps) is faster than "
45 "the slowest DIMM(s) (tCKmin %u ps) can support.\n",
46 mclk_ps, tckmin_x_ps);
48 /* determine the acutal cas latency */
49 caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps;
50 /* check if the dimms support the CAS latency */
51 while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
55 /* once the caculation of caslat_actual is completed
56 * we must verify that this CAS latency value does not
57 * exceed tAAmax, which is 20 ns for all DDR3 speed grades
59 if (caslat_actual * mclk_ps > 20000) {
60 printf("The choosen cas latency %d is too large\n",
63 outpdimm->lowest_common_SPD_caslat = caslat_actual;
70 * compute_lowest_common_dimm_parameters()
72 * Determine the worst-case DIMM timing parameters from the set of DIMMs
73 * whose parameters have been computed into the array pointed to
77 compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
78 common_timing_params_t *outpdimm,
79 const unsigned int number_of_dimms)
83 unsigned int tckmin_x_ps = 0;
84 unsigned int tckmax_ps = 0xFFFFFFFF;
85 unsigned int tckmax_max_ps = 0;
86 unsigned int trcd_ps = 0;
87 unsigned int trp_ps = 0;
88 unsigned int tras_ps = 0;
89 unsigned int twr_ps = 0;
90 unsigned int twtr_ps = 0;
91 unsigned int trfc_ps = 0;
92 unsigned int trrd_ps = 0;
93 unsigned int trc_ps = 0;
94 unsigned int refresh_rate_ps = 0;
95 unsigned int tis_ps = 0;
96 unsigned int tih_ps = 0;
97 unsigned int tds_ps = 0;
98 unsigned int tdh_ps = 0;
99 unsigned int trtp_ps = 0;
100 unsigned int tdqsq_max_ps = 0;
101 unsigned int tqhs_ps = 0;
103 unsigned int temp1, temp2;
104 unsigned int additive_latency = 0;
105 #if !defined(CONFIG_FSL_DDR3)
106 const unsigned int mclk_ps = get_memory_clk_period_ps();
107 unsigned int lowest_good_caslat;
110 debug("using mclk_ps = %u\n", mclk_ps);
114 for (i = 0; i < number_of_dimms; i++) {
116 * If there are no ranks on this DIMM,
117 * it probably doesn't exist, so skip it.
119 if (dimm_params[i].n_ranks == 0) {
123 if (dimm_params[i].n_ranks == 4 && i != 0) {
124 printf("Found Quad-rank DIMM in wrong bank, ignored."
125 " Software may not run as expected.\n");
131 * check if quad-rank DIMM is plugged if
132 * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
133 * Only the board with proper design is capable
135 #ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
136 if (dimm_params[i].n_ranks == 4 && \
137 CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
138 printf("Found Quad-rank DIMM, not able to support.");
144 * Find minimum tckmax_ps to find fastest slow speed,
145 * i.e., this is the slowest the whole system can go.
147 tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps);
149 /* Either find maximum value to determine slowest
150 * speed, delay, time, period, etc */
151 tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
152 tckmax_max_ps = max(tckmax_max_ps, dimm_params[i].tckmax_ps);
153 trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps);
154 trp_ps = max(trp_ps, dimm_params[i].trp_ps);
155 tras_ps = max(tras_ps, dimm_params[i].tras_ps);
156 twr_ps = max(twr_ps, dimm_params[i].twr_ps);
157 twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps);
158 trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps);
159 trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps);
160 trc_ps = max(trc_ps, dimm_params[i].trc_ps);
161 tis_ps = max(tis_ps, dimm_params[i].tis_ps);
162 tih_ps = max(tih_ps, dimm_params[i].tih_ps);
163 tds_ps = max(tds_ps, dimm_params[i].tds_ps);
164 tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps);
165 trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps);
166 tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps);
167 refresh_rate_ps = max(refresh_rate_ps,
168 dimm_params[i].refresh_rate_ps);
171 * Find maximum tdqsq_max_ps to find slowest.
173 * FIXME: is finding the slowest value the correct
174 * strategy for this parameter?
176 tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps);
179 outpdimm->ndimms_present = number_of_dimms - temp1;
181 if (temp1 == number_of_dimms) {
182 debug("no dimms this memory controller\n");
186 outpdimm->tckmin_x_ps = tckmin_x_ps;
187 outpdimm->tckmax_ps = tckmax_ps;
188 outpdimm->tckmax_max_ps = tckmax_max_ps;
189 outpdimm->trcd_ps = trcd_ps;
190 outpdimm->trp_ps = trp_ps;
191 outpdimm->tras_ps = tras_ps;
192 outpdimm->twr_ps = twr_ps;
193 outpdimm->twtr_ps = twtr_ps;
194 outpdimm->trfc_ps = trfc_ps;
195 outpdimm->trrd_ps = trrd_ps;
196 outpdimm->trc_ps = trc_ps;
197 outpdimm->refresh_rate_ps = refresh_rate_ps;
198 outpdimm->tis_ps = tis_ps;
199 outpdimm->tih_ps = tih_ps;
200 outpdimm->tds_ps = tds_ps;
201 outpdimm->tdh_ps = tdh_ps;
202 outpdimm->trtp_ps = trtp_ps;
203 outpdimm->tdqsq_max_ps = tdqsq_max_ps;
204 outpdimm->tqhs_ps = tqhs_ps;
206 /* Determine common burst length for all DIMMs. */
208 for (i = 0; i < number_of_dimms; i++) {
209 if (dimm_params[i].n_ranks) {
210 temp1 &= dimm_params[i].burst_lengths_bitmask;
213 outpdimm->all_dimms_burst_lengths_bitmask = temp1;
215 /* Determine if all DIMMs registered buffered. */
217 for (i = 0; i < number_of_dimms; i++) {
218 if (dimm_params[i].n_ranks) {
219 if (dimm_params[i].registered_dimm) {
221 #ifndef CONFIG_SPL_BUILD
222 printf("Detected RDIMM %s\n",
223 dimm_params[i].mpart);
227 #ifndef CONFIG_SPL_BUILD
228 printf("Detected UDIMM %s\n",
229 dimm_params[i].mpart);
235 outpdimm->all_dimms_registered = 0;
236 outpdimm->all_dimms_unbuffered = 0;
237 if (temp1 && !temp2) {
238 outpdimm->all_dimms_registered = 1;
239 } else if (!temp1 && temp2) {
240 outpdimm->all_dimms_unbuffered = 1;
242 printf("ERROR: Mix of registered buffered and unbuffered "
243 "DIMMs detected!\n");
247 if (outpdimm->all_dimms_registered)
248 for (j = 0; j < 16; j++) {
249 outpdimm->rcw[j] = dimm_params[0].rcw[j];
250 for (i = 1; i < number_of_dimms; i++) {
251 if (!dimm_params[i].n_ranks)
253 if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
261 printf("ERROR: Mix different RDIMM detected!\n");
263 #if defined(CONFIG_FSL_DDR3)
264 if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
268 * Compute a CAS latency suitable for all DIMMs
270 * Strategy for SPD-defined latencies: compute only
271 * CAS latency defined by all DIMMs.
275 * Step 1: find CAS latency common to all DIMMs using bitwise
279 for (i = 0; i < number_of_dimms; i++) {
280 if (dimm_params[i].n_ranks) {
282 temp2 |= 1 << dimm_params[i].caslat_x;
283 temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
284 temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
286 * FIXME: If there was no entry for X-2 (X-1) in
287 * the SPD, then caslat_x_minus_2
288 * (caslat_x_minus_1) contains either 255 or
289 * 0xFFFFFFFF because that's what the glorious
290 * __ilog2 function returns for an input of 0.
291 * On 32-bit PowerPC, left shift counts with bit
292 * 26 set (that the value of 255 or 0xFFFFFFFF
293 * will have), cause the destination register to
294 * be 0. That is why this works.
301 * Step 2: check each common CAS latency against tCK of each
304 lowest_good_caslat = 0;
308 temp2 = __ilog2(temp1);
309 debug("checking common caslat = %u\n", temp2);
311 /* Check if this CAS latency will work on all DIMMs at tCK. */
312 for (i = 0; i < number_of_dimms; i++) {
313 if (!dimm_params[i].n_ranks) {
316 if (dimm_params[i].caslat_x == temp2) {
317 if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
318 debug("CL = %u ok on DIMM %u at tCK=%u"
319 " ps with its tCKmin_X_ps of %u\n",
321 dimm_params[i].tckmin_x_ps);
328 if (dimm_params[i].caslat_x_minus_1 == temp2) {
329 unsigned int tckmin_x_minus_1_ps
330 = dimm_params[i].tckmin_x_minus_1_ps;
331 if (mclk_ps >= tckmin_x_minus_1_ps) {
332 debug("CL = %u ok on DIMM %u at "
333 "tCK=%u ps with its "
334 "tckmin_x_minus_1_ps of %u\n",
336 tckmin_x_minus_1_ps);
343 if (dimm_params[i].caslat_x_minus_2 == temp2) {
344 unsigned int tckmin_x_minus_2_ps
345 = dimm_params[i].tckmin_x_minus_2_ps;
346 if (mclk_ps >= tckmin_x_minus_2_ps) {
347 debug("CL = %u ok on DIMM %u at "
348 "tCK=%u ps with its "
349 "tckmin_x_minus_2_ps of %u\n",
351 tckmin_x_minus_2_ps);
360 lowest_good_caslat = temp2;
363 temp1 &= ~(1 << temp2);
366 debug("lowest common SPD-defined CAS latency = %u\n",
368 outpdimm->lowest_common_SPD_caslat = lowest_good_caslat;
372 * Compute a common 'de-rated' CAS latency.
374 * The strategy here is to find the *highest* dereated cas latency
375 * with the assumption that all of the DIMMs will support a dereated
376 * CAS latency higher than or equal to their lowest dereated value.
379 for (i = 0; i < number_of_dimms; i++) {
380 temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
382 outpdimm->highest_common_derated_caslat = temp1;
383 debug("highest common dereated CAS latency = %u\n", temp1);
384 #endif /* #if defined(CONFIG_FSL_DDR3) */
386 /* Determine if all DIMMs ECC capable. */
388 for (i = 0; i < number_of_dimms; i++) {
389 if (dimm_params[i].n_ranks &&
390 !(dimm_params[i].edc_config & EDC_ECC)) {
396 debug("all DIMMs ECC capable\n");
398 debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
400 outpdimm->all_dimms_ecc_capable = temp1;
402 #ifndef CONFIG_FSL_DDR3
403 /* FIXME: move to somewhere else to validate. */
404 if (mclk_ps > tckmax_max_ps) {
405 printf("Warning: some of the installed DIMMs "
406 "can not operate this slowly.\n");
411 * Compute additive latency.
413 * For DDR1, additive latency should be 0.
415 * For DDR2, with ODT enabled, use "a value" less than ACTTORW,
416 * which comes from Trcd, and also note that:
417 * add_lat + caslat must be >= 4
419 * For DDR3, we use the AL=0
421 * When to use additive latency for DDR2:
423 * I. Because you are using CL=3 and need to do ODT on writes and
424 * want functionality.
425 * 1. Are you going to use ODT? (Does your board not have
426 * additional termination circuitry for DQ, DQS, DQS_,
427 * DM, RDQS, RDQS_ for x4/x8 configs?)
428 * 2. If so, is your lowest supported CL going to be 3?
429 * 3. If so, then you must set AL=1 because
431 * WL >= 3 for ODT on writes
440 * RL >= 3 for ODT on reads
443 * Since CL aren't usually less than 2, AL=0 is a minimum,
444 * so the WL-derived AL should be the -- FIXME?
446 * II. Because you are using auto-precharge globally and want to
447 * use additive latency (posted CAS) to get more bandwidth.
448 * 1. Are you going to use auto-precharge mode globally?
450 * Use addtivie latency and compute AL to be 1 cycle less than
451 * tRCD, i.e. the READ or WRITE command is in the cycle
452 * immediately following the ACTIVATE command..
454 * III. Because you feel like it or want to do some sort of
455 * degraded-performance experiment.
456 * 1. Do you just want to use additive latency because you feel
459 * Validation: AL is less than tRCD, and within the other
460 * read-to-precharge constraints.
463 additive_latency = 0;
465 #if defined(CONFIG_FSL_DDR2)
466 if (lowest_good_caslat < 4) {
467 additive_latency = (picos_to_mclk(trcd_ps) > lowest_good_caslat)
468 ? picos_to_mclk(trcd_ps) - lowest_good_caslat : 0;
469 if (mclk_to_picos(additive_latency) > trcd_ps) {
470 additive_latency = picos_to_mclk(trcd_ps);
471 debug("setting additive_latency to %u because it was "
472 " greater than tRCD_ps\n", additive_latency);
476 #elif defined(CONFIG_FSL_DDR3)
478 * The system will not use the global auto-precharge mode.
479 * However, it uses the page mode, so we set AL=0
481 additive_latency = 0;
485 * Validate additive latency
486 * FIXME: move to somewhere else to validate
490 if (mclk_to_picos(additive_latency) > trcd_ps) {
491 printf("Error: invalid additive latency exceeds tRCD(min).\n");
496 * RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled
497 * WL = RL - 1; WL >= 3 for ODT_WL_CFG to be enabled
498 * ADD_LAT (the register) must be set to a value less
499 * than ACTTORW if WL = 1, then AL must be set to 1
500 * RD_TO_PRE (the register) must be set to a minimum
501 * tRTP + AL if AL is nonzero
505 * Additive latency will be applied only if the memctl option to
508 outpdimm->additive_latency = additive_latency;
510 debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps);
511 debug("trcd_ps = %u\n", outpdimm->trcd_ps);
512 debug("trp_ps = %u\n", outpdimm->trp_ps);
513 debug("tras_ps = %u\n", outpdimm->tras_ps);
514 debug("twr_ps = %u\n", outpdimm->twr_ps);
515 debug("twtr_ps = %u\n", outpdimm->twtr_ps);
516 debug("trfc_ps = %u\n", outpdimm->trfc_ps);
517 debug("trrd_ps = %u\n", outpdimm->trrd_ps);
518 debug("trc_ps = %u\n", outpdimm->trc_ps);