2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 #include <asm/fsl_ddr_sdram.h>
15 compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
16 common_timing_params_t *outpdimm,
17 unsigned int number_of_dimms)
20 unsigned int tAAmin_ps = 0;
21 unsigned int tCKmin_X_ps = 0;
22 unsigned int common_caslat;
23 unsigned int caslat_actual;
24 unsigned int retry = 16;
26 const unsigned int mclk_ps = get_memory_clk_period_ps();
28 /* compute the common CAS latency supported between slots */
29 tmp = dimm_params[0].caslat_X;
30 for (i = 1; i < number_of_dimms; i++) {
31 if (dimm_params[i].n_ranks)
32 tmp &= dimm_params[i].caslat_X;
36 /* compute the max tAAmin tCKmin between slots */
37 for (i = 0; i < number_of_dimms; i++) {
38 tAAmin_ps = max(tAAmin_ps, dimm_params[i].tAA_ps);
39 tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
41 /* validate if the memory clk is in the range of dimms */
42 if (mclk_ps < tCKmin_X_ps) {
43 printf("DDR clock (MCLK cycle %u ps) is faster than "
44 "the slowest DIMM(s) (tCKmin %u ps) can support.\n",
45 mclk_ps, tCKmin_X_ps);
48 /* determine the acutal cas latency */
49 caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps;
50 /* check if the dimms support the CAS latency */
51 while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
55 /* once the caculation of caslat_actual is completed
56 * we must verify that this CAS latency value does not
57 * exceed tAAmax, which is 20 ns for all DDR3 speed grades
59 if (caslat_actual * mclk_ps > 20000) {
60 printf("The choosen cas latency %d is too large\n",
64 outpdimm->lowest_common_SPD_caslat = caslat_actual;
70 * compute_lowest_common_dimm_parameters()
72 * Determine the worst-case DIMM timing parameters from the set of DIMMs
73 * whose parameters have been computed into the array pointed to
77 compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
78 common_timing_params_t *outpdimm,
79 unsigned int number_of_dimms)
83 unsigned int tCKmin_X_ps = 0;
84 unsigned int tCKmax_ps = 0xFFFFFFFF;
85 unsigned int tCKmax_max_ps = 0;
86 unsigned int tRCD_ps = 0;
87 unsigned int tRP_ps = 0;
88 unsigned int tRAS_ps = 0;
89 unsigned int tWR_ps = 0;
90 unsigned int tWTR_ps = 0;
91 unsigned int tRFC_ps = 0;
92 unsigned int tRRD_ps = 0;
93 unsigned int tRC_ps = 0;
94 unsigned int refresh_rate_ps = 0;
95 unsigned int tIS_ps = 0;
96 unsigned int tIH_ps = 0;
97 unsigned int tDS_ps = 0;
98 unsigned int tDH_ps = 0;
99 unsigned int tRTP_ps = 0;
100 unsigned int tDQSQ_max_ps = 0;
101 unsigned int tQHS_ps = 0;
103 unsigned int temp1, temp2;
104 unsigned int additive_latency = 0;
105 #if !defined(CONFIG_FSL_DDR3)
106 const unsigned int mclk_ps = get_memory_clk_period_ps();
107 unsigned int lowest_good_caslat;
110 debug("using mclk_ps = %u\n", mclk_ps);
114 for (i = 0; i < number_of_dimms; i++) {
116 * If there are no ranks on this DIMM,
117 * it probably doesn't exist, so skip it.
119 if (dimm_params[i].n_ranks == 0) {
123 if (dimm_params[i].n_ranks == 4 && i != 0) {
124 printf("Found Quad-rank DIMM in wrong bank, ignored."
125 " Software may not run as expected.\n");
129 if (dimm_params[i].n_ranks == 4 && \
130 CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
131 printf("Found Quad-rank DIMM, not able to support.");
137 * Find minimum tCKmax_ps to find fastest slow speed,
138 * i.e., this is the slowest the whole system can go.
140 tCKmax_ps = min(tCKmax_ps, dimm_params[i].tCKmax_ps);
142 /* Either find maximum value to determine slowest
143 * speed, delay, time, period, etc */
144 tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
145 tCKmax_max_ps = max(tCKmax_max_ps, dimm_params[i].tCKmax_ps);
146 tRCD_ps = max(tRCD_ps, dimm_params[i].tRCD_ps);
147 tRP_ps = max(tRP_ps, dimm_params[i].tRP_ps);
148 tRAS_ps = max(tRAS_ps, dimm_params[i].tRAS_ps);
149 tWR_ps = max(tWR_ps, dimm_params[i].tWR_ps);
150 tWTR_ps = max(tWTR_ps, dimm_params[i].tWTR_ps);
151 tRFC_ps = max(tRFC_ps, dimm_params[i].tRFC_ps);
152 tRRD_ps = max(tRRD_ps, dimm_params[i].tRRD_ps);
153 tRC_ps = max(tRC_ps, dimm_params[i].tRC_ps);
154 tIS_ps = max(tIS_ps, dimm_params[i].tIS_ps);
155 tIH_ps = max(tIH_ps, dimm_params[i].tIH_ps);
156 tDS_ps = max(tDS_ps, dimm_params[i].tDS_ps);
157 tDH_ps = max(tDH_ps, dimm_params[i].tDH_ps);
158 tRTP_ps = max(tRTP_ps, dimm_params[i].tRTP_ps);
159 tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps);
160 refresh_rate_ps = max(refresh_rate_ps,
161 dimm_params[i].refresh_rate_ps);
164 * Find maximum tDQSQ_max_ps to find slowest.
166 * FIXME: is finding the slowest value the correct
167 * strategy for this parameter?
169 tDQSQ_max_ps = max(tDQSQ_max_ps, dimm_params[i].tDQSQ_max_ps);
172 outpdimm->ndimms_present = number_of_dimms - temp1;
174 if (temp1 == number_of_dimms) {
175 debug("no dimms this memory controller\n");
179 outpdimm->tCKmin_X_ps = tCKmin_X_ps;
180 outpdimm->tCKmax_ps = tCKmax_ps;
181 outpdimm->tCKmax_max_ps = tCKmax_max_ps;
182 outpdimm->tRCD_ps = tRCD_ps;
183 outpdimm->tRP_ps = tRP_ps;
184 outpdimm->tRAS_ps = tRAS_ps;
185 outpdimm->tWR_ps = tWR_ps;
186 outpdimm->tWTR_ps = tWTR_ps;
187 outpdimm->tRFC_ps = tRFC_ps;
188 outpdimm->tRRD_ps = tRRD_ps;
189 outpdimm->tRC_ps = tRC_ps;
190 outpdimm->refresh_rate_ps = refresh_rate_ps;
191 outpdimm->tIS_ps = tIS_ps;
192 outpdimm->tIH_ps = tIH_ps;
193 outpdimm->tDS_ps = tDS_ps;
194 outpdimm->tDH_ps = tDH_ps;
195 outpdimm->tRTP_ps = tRTP_ps;
196 outpdimm->tDQSQ_max_ps = tDQSQ_max_ps;
197 outpdimm->tQHS_ps = tQHS_ps;
199 /* Determine common burst length for all DIMMs. */
201 for (i = 0; i < number_of_dimms; i++) {
202 if (dimm_params[i].n_ranks) {
203 temp1 &= dimm_params[i].burst_lengths_bitmask;
206 outpdimm->all_DIMMs_burst_lengths_bitmask = temp1;
208 /* Determine if all DIMMs registered buffered. */
210 for (i = 0; i < number_of_dimms; i++) {
211 if (dimm_params[i].n_ranks) {
212 if (dimm_params[i].registered_dimm) {
214 printf("Detected RDIMM %s\n",
215 dimm_params[i].mpart);
218 printf("Detected UDIMM %s\n",
219 dimm_params[i].mpart);
224 outpdimm->all_DIMMs_registered = 0;
225 outpdimm->all_DIMMs_unbuffered = 0;
226 if (temp1 && !temp2) {
227 outpdimm->all_DIMMs_registered = 1;
228 } else if (!temp1 && temp2) {
229 outpdimm->all_DIMMs_unbuffered = 1;
231 printf("ERROR: Mix of registered buffered and unbuffered "
232 "DIMMs detected!\n");
236 if (outpdimm->all_DIMMs_registered)
237 for (j = 0; j < 16; j++) {
238 outpdimm->rcw[j] = dimm_params[0].rcw[j];
239 for (i = 1; i < number_of_dimms; i++)
240 if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
247 printf("ERROR: Mix different RDIMM detected!\n");
249 #if defined(CONFIG_FSL_DDR3)
250 if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
254 * Compute a CAS latency suitable for all DIMMs
256 * Strategy for SPD-defined latencies: compute only
257 * CAS latency defined by all DIMMs.
261 * Step 1: find CAS latency common to all DIMMs using bitwise
265 for (i = 0; i < number_of_dimms; i++) {
266 if (dimm_params[i].n_ranks) {
268 temp2 |= 1 << dimm_params[i].caslat_X;
269 temp2 |= 1 << dimm_params[i].caslat_X_minus_1;
270 temp2 |= 1 << dimm_params[i].caslat_X_minus_2;
272 * FIXME: If there was no entry for X-2 (X-1) in
273 * the SPD, then caslat_X_minus_2
274 * (caslat_X_minus_1) contains either 255 or
275 * 0xFFFFFFFF because that's what the glorious
276 * __ilog2 function returns for an input of 0.
277 * On 32-bit PowerPC, left shift counts with bit
278 * 26 set (that the value of 255 or 0xFFFFFFFF
279 * will have), cause the destination register to
280 * be 0. That is why this works.
287 * Step 2: check each common CAS latency against tCK of each
290 lowest_good_caslat = 0;
294 temp2 = __ilog2(temp1);
295 debug("checking common caslat = %u\n", temp2);
297 /* Check if this CAS latency will work on all DIMMs at tCK. */
298 for (i = 0; i < number_of_dimms; i++) {
299 if (!dimm_params[i].n_ranks) {
302 if (dimm_params[i].caslat_X == temp2) {
303 if (mclk_ps >= dimm_params[i].tCKmin_X_ps) {
304 debug("CL = %u ok on DIMM %u at tCK=%u"
305 " ps with its tCKmin_X_ps of %u\n",
307 dimm_params[i].tCKmin_X_ps);
314 if (dimm_params[i].caslat_X_minus_1 == temp2) {
315 unsigned int tCKmin_X_minus_1_ps
316 = dimm_params[i].tCKmin_X_minus_1_ps;
317 if (mclk_ps >= tCKmin_X_minus_1_ps) {
318 debug("CL = %u ok on DIMM %u at "
319 "tCK=%u ps with its "
320 "tCKmin_X_minus_1_ps of %u\n",
322 tCKmin_X_minus_1_ps);
329 if (dimm_params[i].caslat_X_minus_2 == temp2) {
330 unsigned int tCKmin_X_minus_2_ps
331 = dimm_params[i].tCKmin_X_minus_2_ps;
332 if (mclk_ps >= tCKmin_X_minus_2_ps) {
333 debug("CL = %u ok on DIMM %u at "
334 "tCK=%u ps with its "
335 "tCKmin_X_minus_2_ps of %u\n",
337 tCKmin_X_minus_2_ps);
346 lowest_good_caslat = temp2;
349 temp1 &= ~(1 << temp2);
352 debug("lowest common SPD-defined CAS latency = %u\n",
354 outpdimm->lowest_common_SPD_caslat = lowest_good_caslat;
358 * Compute a common 'de-rated' CAS latency.
360 * The strategy here is to find the *highest* dereated cas latency
361 * with the assumption that all of the DIMMs will support a dereated
362 * CAS latency higher than or equal to their lowest dereated value.
365 for (i = 0; i < number_of_dimms; i++) {
366 temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
368 outpdimm->highest_common_derated_caslat = temp1;
369 debug("highest common dereated CAS latency = %u\n", temp1);
370 #endif /* #if defined(CONFIG_FSL_DDR3) */
372 /* Determine if all DIMMs ECC capable. */
374 for (i = 0; i < number_of_dimms; i++) {
375 if (dimm_params[i].n_ranks &&
376 !(dimm_params[i].edc_config & EDC_ECC)) {
382 debug("all DIMMs ECC capable\n");
384 debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
386 outpdimm->all_DIMMs_ECC_capable = temp1;
388 #ifndef CONFIG_FSL_DDR3
389 /* FIXME: move to somewhere else to validate. */
390 if (mclk_ps > tCKmax_max_ps) {
391 printf("Warning: some of the installed DIMMs "
392 "can not operate this slowly.\n");
397 * Compute additive latency.
399 * For DDR1, additive latency should be 0.
401 * For DDR2, with ODT enabled, use "a value" less than ACTTORW,
402 * which comes from Trcd, and also note that:
403 * add_lat + caslat must be >= 4
405 * For DDR3, we use the AL=0
407 * When to use additive latency for DDR2:
409 * I. Because you are using CL=3 and need to do ODT on writes and
410 * want functionality.
411 * 1. Are you going to use ODT? (Does your board not have
412 * additional termination circuitry for DQ, DQS, DQS_,
413 * DM, RDQS, RDQS_ for x4/x8 configs?)
414 * 2. If so, is your lowest supported CL going to be 3?
415 * 3. If so, then you must set AL=1 because
417 * WL >= 3 for ODT on writes
426 * RL >= 3 for ODT on reads
429 * Since CL aren't usually less than 2, AL=0 is a minimum,
430 * so the WL-derived AL should be the -- FIXME?
432 * II. Because you are using auto-precharge globally and want to
433 * use additive latency (posted CAS) to get more bandwidth.
434 * 1. Are you going to use auto-precharge mode globally?
436 * Use addtivie latency and compute AL to be 1 cycle less than
437 * tRCD, i.e. the READ or WRITE command is in the cycle
438 * immediately following the ACTIVATE command..
440 * III. Because you feel like it or want to do some sort of
441 * degraded-performance experiment.
442 * 1. Do you just want to use additive latency because you feel
445 * Validation: AL is less than tRCD, and within the other
446 * read-to-precharge constraints.
449 additive_latency = 0;
451 #if defined(CONFIG_FSL_DDR2)
452 if (lowest_good_caslat < 4) {
453 additive_latency = (picos_to_mclk(tRCD_ps) > lowest_good_caslat)
454 ? picos_to_mclk(tRCD_ps) - lowest_good_caslat : 0;
455 if (mclk_to_picos(additive_latency) > tRCD_ps) {
456 additive_latency = picos_to_mclk(tRCD_ps);
457 debug("setting additive_latency to %u because it was "
458 " greater than tRCD_ps\n", additive_latency);
462 #elif defined(CONFIG_FSL_DDR3)
464 * The system will not use the global auto-precharge mode.
465 * However, it uses the page mode, so we set AL=0
467 additive_latency = 0;
471 * Validate additive latency
472 * FIXME: move to somewhere else to validate
476 if (mclk_to_picos(additive_latency) > tRCD_ps) {
477 printf("Error: invalid additive latency exceeds tRCD(min).\n");
482 * RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled
483 * WL = RL - 1; WL >= 3 for ODT_WL_CFG to be enabled
484 * ADD_LAT (the register) must be set to a value less
485 * than ACTTORW if WL = 1, then AL must be set to 1
486 * RD_TO_PRE (the register) must be set to a minimum
487 * tRTP + AL if AL is nonzero
491 * Additive latency will be applied only if the memctl option to
494 outpdimm->additive_latency = additive_latency;
496 debug("tCKmin_ps = %u\n", outpdimm->tCKmin_X_ps);
497 debug("tRCD_ps = %u\n", outpdimm->tRCD_ps);
498 debug("tRP_ps = %u\n", outpdimm->tRP_ps);
499 debug("tRAS_ps = %u\n", outpdimm->tRAS_ps);
500 debug("tWR_ps = %u\n", outpdimm->tWR_ps);
501 debug("tWTR_ps = %u\n", outpdimm->tWTR_ps);
502 debug("tRFC_ps = %u\n", outpdimm->tRFC_ps);
503 debug("tRRD_ps = %u\n", outpdimm->tRRD_ps);
504 debug("tRC_ps = %u\n", outpdimm->tRC_ps);