2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
17 #include <asm/fsl_ddr_sdram.h>
21 extern void fsl_ddr_set_lawbar(
22 const common_timing_params_t *memctl_common_params,
23 unsigned int memctl_interleaved,
24 unsigned int ctrl_num);
26 /* processor specific function */
27 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
28 unsigned int ctrl_num);
30 #if defined(SPD_EEPROM_ADDRESS) || \
31 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
32 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
33 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
34 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
35 [0][0] = SPD_EEPROM_ADDRESS,
38 #if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
39 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
40 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
41 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
44 #if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
45 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
46 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
47 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
48 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
49 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
53 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
55 int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
56 sizeof(generic_spd_eeprom_t));
59 printf("DDR: failed to read SPD from address %u\n", i2c_address);
60 memset(spd, 0, sizeof(generic_spd_eeprom_t));
64 __attribute__((weak, alias("__get_spd")))
65 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
67 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
68 unsigned int ctrl_num)
71 unsigned int i2c_address = 0;
73 if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
74 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
78 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
79 i2c_address = spd_i2c_addr[ctrl_num][i];
80 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
84 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
85 unsigned int ctrl_num)
88 #endif /* SPD_EEPROM_ADDRESSx */
92 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
93 * - Same memory data bus width on all controllers
97 * The memory controller and associated documentation use confusing
98 * terminology when referring to the orgranization of DRAM.
100 * Here is a terminology translation table:
102 * memory controller/documention |industry |this code |signals
103 * -------------------------------|-----------|-----------|-----------------
104 * physical bank/bank |rank |rank |chip select (CS)
105 * logical bank/sub-bank |bank |bank |bank address (BA)
106 * page/row |row |page |row address
107 * ??? |column |column |column address
109 * The naming confusion is further exacerbated by the descriptions of the
110 * memory controller interleaving feature, where accesses are interleaved
111 * _BETWEEN_ two seperate memory controllers. This is configured only in
112 * CS0_CONFIG[INTLV_CTL] of each memory controller.
114 * memory controller documentation | number of chip selects
115 * | per memory controller supported
116 * --------------------------------|-----------------------------------------
117 * cache line interleaving | 1 (CS0 only)
118 * page interleaving | 1 (CS0 only)
119 * bank interleaving | 1 (CS0 only)
120 * superbank interleraving | depends on bank (chip select)
121 * | interleraving [rank interleaving]
122 * | mode used on every memory controller
124 * Even further confusing is the existence of the interleaving feature
125 * _WITHIN_ each memory controller. The feature is referred to in
126 * documentation as chip select interleaving or bank interleaving,
127 * although it is configured in the DDR_SDRAM_CFG field.
129 * Name of field | documentation name | this code
130 * -----------------------------|-----------------------|------------------
131 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
136 const char *step_string_tbl[] = {
138 "STEP_COMPUTE_DIMM_PARMS",
139 "STEP_COMPUTE_COMMON_PARMS",
141 "STEP_ASSIGN_ADDRESSES",
147 const char * step_to_string(unsigned int step) {
149 unsigned int s = __ilog2(step);
151 if ((1 << s) != step)
152 return step_string_tbl[7];
154 return step_string_tbl[s];
158 int step_assign_addresses(fsl_ddr_info_t *pinfo,
159 unsigned int dbw_cap_adj[],
160 unsigned int *all_memctl_interleaving,
161 unsigned int *all_ctlr_rank_interleaving)
166 * If a reduced data width is requested, but the SPD
167 * specifies a physically wider device, adjust the
168 * computed dimm capacities accordingly before
169 * assigning addresses.
171 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
172 unsigned int found = 0;
174 switch (pinfo->memctl_opts[i].data_bus_width) {
177 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
179 if (!pinfo->dimm_params[i][j].n_ranks)
181 dw = pinfo->dimm_params[i][j].primary_sdram_width;
182 if ((dw == 72 || dw == 64)) {
185 } else if ((dw == 40 || dw == 32)) {
194 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
196 dw = pinfo->dimm_params[i][j].data_width;
197 if (pinfo->dimm_params[i][j].n_ranks
198 && (dw == 72 || dw == 64)) {
200 * FIXME: can't really do it
201 * like this because this just
202 * further reduces the memory
218 printf("unexpected data bus width "
219 "specified controller %u\n", i);
225 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
226 if (pinfo->memctl_opts[i].memctl_interleaving)
229 * Not support less than all memory controllers interleaving
230 * if more than two controllers
232 if (j == CONFIG_NUM_DDR_CONTROLLERS)
233 *all_memctl_interleaving = 1;
235 /* Check that all controllers are rank interleaving. */
237 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
238 if (pinfo->memctl_opts[i].ba_intlv_ctl)
241 * All memory controllers must be populated to qualify for
242 * all controller rank interleaving
244 if (j == CONFIG_NUM_DDR_CONTROLLERS)
245 *all_ctlr_rank_interleaving = 1;
247 if (*all_memctl_interleaving) {
248 unsigned long long addr, total_mem_per_ctlr = 0;
250 * If interleaving between memory controllers,
251 * make each controller start at a base address
254 * Also, if bank interleaving (chip select
255 * interleaving) is enabled on each memory
256 * controller, CS0 needs to be programmed to
257 * cover the entire memory range on that memory
260 * Bank interleaving also implies that each
261 * addressed chip select is identical in size.
264 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
266 pinfo->common_timing_params[i].base_address = 0ull;
267 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
268 unsigned long long cap
269 = pinfo->dimm_params[i][j].capacity;
271 pinfo->dimm_params[i][j].base_address = addr;
272 addr += cap >> dbw_cap_adj[i];
273 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
276 pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
279 * Simple linear assignment if memory
280 * controllers are not interleaved.
282 unsigned long long cur_memsize = 0;
283 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
284 u64 total_mem_per_ctlr = 0;
285 pinfo->common_timing_params[i].base_address =
287 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
288 /* Compute DIMM base addresses. */
289 unsigned long long cap =
290 pinfo->dimm_params[i][j].capacity;
291 pinfo->dimm_params[i][j].base_address =
293 cur_memsize += cap >> dbw_cap_adj[i];
294 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
296 pinfo->common_timing_params[i].total_mem =
305 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
306 unsigned int size_only)
309 unsigned int all_controllers_memctl_interleaving = 0;
310 unsigned int all_controllers_rank_interleaving = 0;
311 unsigned long long total_mem = 0;
313 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
314 common_timing_params_t *timing_params = pinfo->common_timing_params;
316 /* data bus width capacity adjust shift amount */
317 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
319 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
320 dbw_capacity_adjust[i] = 0;
323 debug("starting at step %u (%s)\n",
324 start_step, step_to_string(start_step));
326 switch (start_step) {
328 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
329 /* STEP 1: Gather all DIMM SPD data */
330 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
331 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
334 case STEP_COMPUTE_DIMM_PARMS:
335 /* STEP 2: Compute DIMM parameters from SPD data */
337 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
338 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
340 generic_spd_eeprom_t *spd =
341 &(pinfo->spd_installed_dimms[i][j]);
342 dimm_params_t *pdimm =
343 &(pinfo->dimm_params[i][j]);
345 retval = compute_dimm_parameters(spd, pdimm, i);
346 #ifdef CONFIG_SYS_DDR_RAW_TIMING
348 printf("SPD error! Trying fallback to "
349 "raw timing calculation\n");
350 fsl_ddr_get_dimm_params(pdimm, i, j);
354 printf("Error: compute_dimm_parameters"
355 " non-zero returned FATAL value "
356 "for memctl=%u dimm=%u\n", i, j);
361 debug("Warning: compute_dimm_parameters"
362 " non-zero return value for memctl=%u "
369 case STEP_COMPUTE_DIMM_PARMS:
370 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
371 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
372 dimm_params_t *pdimm =
373 &(pinfo->dimm_params[i][j]);
374 fsl_ddr_get_dimm_params(pdimm, i, j);
377 debug("Filling dimm parameters from board specific file\n");
379 case STEP_COMPUTE_COMMON_PARMS:
381 * STEP 3: Compute a common set of timing parameters
382 * suitable for all of the DIMMs on each memory controller
384 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
385 debug("Computing lowest common DIMM"
386 " parameters for memctl=%u\n", i);
387 compute_lowest_common_dimm_parameters(
388 pinfo->dimm_params[i],
390 CONFIG_DIMM_SLOTS_PER_CTLR);
393 case STEP_GATHER_OPTS:
394 /* STEP 4: Gather configuration requirements from user */
395 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
396 debug("Reloading memory controller "
397 "configuration options for memctl=%u\n", i);
399 * This "reloads" the memory controller options
400 * to defaults. If the user "edits" an option,
401 * next_step points to the step after this,
402 * which is currently STEP_ASSIGN_ADDRESSES.
404 populate_memctl_options(
405 timing_params[i].all_DIMMs_registered,
406 &pinfo->memctl_opts[i],
407 pinfo->dimm_params[i], i);
409 check_interleaving_options(pinfo);
410 case STEP_ASSIGN_ADDRESSES:
411 /* STEP 5: Assign addresses to chip selects */
412 step_assign_addresses(pinfo,
414 &all_controllers_memctl_interleaving,
415 &all_controllers_rank_interleaving);
417 case STEP_COMPUTE_REGS:
418 /* STEP 6: compute controller register values */
419 debug("FSL Memory ctrl cg register computation\n");
420 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
421 if (timing_params[i].ndimms_present == 0) {
422 memset(&ddr_reg[i], 0,
423 sizeof(fsl_ddr_cfg_regs_t));
427 compute_fsl_memctl_config_regs(
428 &pinfo->memctl_opts[i],
429 &ddr_reg[i], &timing_params[i],
430 pinfo->dimm_params[i],
431 dbw_capacity_adjust[i],
439 /* Compute the total amount of memory. */
442 * If bank interleaving but NOT memory controller interleaving
443 * CS_BNDS describe the quantity of memory on each memory
444 * controller, so the total is the sum across.
446 if (!all_controllers_memctl_interleaving
447 && all_controllers_rank_interleaving) {
449 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
450 total_mem += timing_params[i].total_mem;
455 * Compute the amount of memory available just by
456 * looking for the highest valid CSn_BNDS value.
457 * This allows us to also experiment with using
458 * only CS0 when using dual-rank DIMMs.
460 unsigned int max_end = 0;
462 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
463 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
464 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
465 if (reg->cs[j].config & 0x80000000) {
467 end = reg->cs[j].bnds & 0xFFF;
475 total_mem = 1 + (((unsigned long long)max_end << 24ULL)
483 * fsl_ddr_sdram() -- this is the main function to be called by
484 * initdram() in the board file.
486 * It returns amount of memory configured in bytes.
488 phys_size_t fsl_ddr_sdram(void)
491 unsigned int memctl_interleaved;
492 unsigned long long total_memory;
495 /* Reset info structure. */
496 memset(&info, 0, sizeof(fsl_ddr_info_t));
498 /* Compute it once normally. */
499 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
501 /* Check for memory controller interleaving. */
502 memctl_interleaved = 0;
503 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
504 memctl_interleaved +=
505 info.memctl_opts[i].memctl_interleaving;
508 if (memctl_interleaved) {
509 if (memctl_interleaved == CONFIG_NUM_DDR_CONTROLLERS) {
510 debug("memctl interleaving\n");
512 * Change the meaning of memctl_interleaved
515 memctl_interleaved = 1;
517 printf("Warning: memctl interleaving not "
518 "properly configured on all controllers\n");
519 memctl_interleaved = 0;
520 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
521 info.memctl_opts[i].memctl_interleaving = 0;
522 debug("Recomputing with memctl_interleaving off.\n");
523 total_memory = fsl_ddr_compute(&info,
524 STEP_ASSIGN_ADDRESSES,
529 /* Program configuration registers. */
530 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
531 debug("Programming controller %u\n", i);
532 if (info.common_timing_params[i].ndimms_present == 0) {
533 debug("No dimms present on controller %u; "
534 "skipping programming\n", i);
538 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
541 if (memctl_interleaved) {
542 const unsigned int ctrl_num = 0;
544 /* Only set LAWBAR1 if memory controller interleaving is on. */
545 fsl_ddr_set_lawbar(&info.common_timing_params[0],
546 memctl_interleaved, ctrl_num);
549 * Memory controller interleaving is NOT on;
550 * set each lawbar individually.
552 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
553 fsl_ddr_set_lawbar(&info.common_timing_params[i],
558 debug("total_memory = %llu\n", total_memory);
560 #if !defined(CONFIG_PHYS_64BIT)
561 /* Check for 4G or more. Bad. */
562 if (total_memory >= (1ull << 32)) {
563 printf("Detected %lld MB of memory\n", total_memory >> 20);
564 printf(" This U-Boot only supports < 4G of DDR\n");
565 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
566 printf(" "); /* re-align to match init_func_ram print */
567 total_memory = CONFIG_MAX_MEM_MAPPED;
575 * fsl_ddr_sdram_size() - This function only returns the size of the total
576 * memory without setting ddr control registers.
579 fsl_ddr_sdram_size(void)
582 unsigned long long total_memory = 0;
584 memset(&info, 0 , sizeof(fsl_ddr_info_t));
586 /* Compute it once normally. */
587 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);