git.sur5r.net Git - u-boot/blob - arch/powerpc/cpu/mpc8xxx/ddr/options.c

   1 /*
   2  * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 #include <common.h>
  11 #include <hwconfig.h>
  12 #include <asm/fsl_ddr_sdram.h>
  13
  14 #include "ddr.h"
  15
  16 /*
  17  * Use our own stack based buffer before relocation to allow accessing longer
  18  * hwconfig strings that might be in the environment before we've relocated.
  19  * This is pretty fragile on both the use of stack and if the buffer is big
  20  * enough. However we will get a warning from getenv_f for the later.
  21  */
  22 #define HWCONFIG_BUFFER_SIZE    128
  23
  24 /* Board-specific functions defined in each board's ddr.c */
  25 extern void fsl_ddr_board_options(memctl_options_t *popts,
  26                 dimm_params_t *pdimm,
  27                 unsigned int ctrl_num);
  28
  29 struct dynamic_odt {
  30         unsigned int odt_rd_cfg;
  31         unsigned int odt_wr_cfg;
  32         unsigned int odt_rtt_norm;
  33         unsigned int odt_rtt_wr;
  34 };
  35
  36 #ifdef CONFIG_FSL_DDR3
  37 static const struct dynamic_odt single_Q[4] = {
  38         {       /* cs0 */
  39                 FSL_DDR_ODT_NEVER,
  40                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  41                 DDR3_RTT_20_OHM,
  42                 DDR3_RTT_120_OHM
  43         },
  44         {       /* cs1 */
  45                 FSL_DDR_ODT_NEVER,
  46                 FSL_DDR_ODT_NEVER,      /* tied high */
  47                 DDR3_RTT_OFF,
  48                 DDR3_RTT_120_OHM
  49         },
  50         {       /* cs2 */
  51                 FSL_DDR_ODT_NEVER,
  52                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  53                 DDR3_RTT_20_OHM,
  54                 DDR3_RTT_120_OHM
  55         },
  56         {       /* cs3 */
  57                 FSL_DDR_ODT_NEVER,
  58                 FSL_DDR_ODT_NEVER,      /* tied high */
  59                 DDR3_RTT_OFF,
  60                 DDR3_RTT_120_OHM
  61         }
  62 };
  63
  64 static const struct dynamic_odt single_D[4] = {
  65         {       /* cs0 */
  66                 FSL_DDR_ODT_NEVER,
  67                 FSL_DDR_ODT_ALL,
  68                 DDR3_RTT_40_OHM,
  69                 DDR3_RTT_OFF
  70         },
  71         {       /* cs1 */
  72                 FSL_DDR_ODT_NEVER,
  73                 FSL_DDR_ODT_NEVER,
  74                 DDR3_RTT_OFF,
  75                 DDR3_RTT_OFF
  76         },
  77         {0, 0, 0, 0},
  78         {0, 0, 0, 0}
  79 };
  80
  81 static const struct dynamic_odt single_S[4] = {
  82         {       /* cs0 */
  83                 FSL_DDR_ODT_NEVER,
  84                 FSL_DDR_ODT_ALL,
  85                 DDR3_RTT_40_OHM,
  86                 DDR3_RTT_OFF
  87         },
  88         {0, 0, 0, 0},
  89         {0, 0, 0, 0},
  90         {0, 0, 0, 0},
  91 };
  92
  93 static const struct dynamic_odt dual_DD[4] = {
  94         {       /* cs0 */
  95                 FSL_DDR_ODT_NEVER,
  96                 FSL_DDR_ODT_SAME_DIMM,
  97                 DDR3_RTT_120_OHM,
  98                 DDR3_RTT_OFF
  99         },
 100         {       /* cs1 */
 101                 FSL_DDR_ODT_OTHER_DIMM,
 102                 FSL_DDR_ODT_OTHER_DIMM,
 103                 DDR3_RTT_30_OHM,
 104                 DDR3_RTT_OFF
 105         },
 106         {       /* cs2 */
 107                 FSL_DDR_ODT_NEVER,
 108                 FSL_DDR_ODT_SAME_DIMM,
 109                 DDR3_RTT_120_OHM,
 110                 DDR3_RTT_OFF
 111         },
 112         {       /* cs3 */
 113                 FSL_DDR_ODT_OTHER_DIMM,
 114                 FSL_DDR_ODT_OTHER_DIMM,
 115                 DDR3_RTT_30_OHM,
 116                 DDR3_RTT_OFF
 117         }
 118 };
 119
 120 static const struct dynamic_odt dual_DS[4] = {
 121         {       /* cs0 */
 122                 FSL_DDR_ODT_NEVER,
 123                 FSL_DDR_ODT_SAME_DIMM,
 124                 DDR3_RTT_120_OHM,
 125                 DDR3_RTT_OFF
 126         },
 127         {       /* cs1 */
 128                 FSL_DDR_ODT_OTHER_DIMM,
 129                 FSL_DDR_ODT_OTHER_DIMM,
 130                 DDR3_RTT_30_OHM,
 131                 DDR3_RTT_OFF
 132         },
 133         {       /* cs2 */
 134                 FSL_DDR_ODT_OTHER_DIMM,
 135                 FSL_DDR_ODT_ALL,
 136                 DDR3_RTT_20_OHM,
 137                 DDR3_RTT_120_OHM
 138         },
 139         {0, 0, 0, 0}
 140 };
 141 static const struct dynamic_odt dual_SD[4] = {
 142         {       /* cs0 */
 143                 FSL_DDR_ODT_OTHER_DIMM,
 144                 FSL_DDR_ODT_ALL,
 145                 DDR3_RTT_20_OHM,
 146                 DDR3_RTT_120_OHM
 147         },
 148         {0, 0, 0, 0},
 149         {       /* cs2 */
 150                 FSL_DDR_ODT_NEVER,
 151                 FSL_DDR_ODT_SAME_DIMM,
 152                 DDR3_RTT_120_OHM,
 153                 DDR3_RTT_OFF
 154         },
 155         {       /* cs3 */
 156                 FSL_DDR_ODT_OTHER_DIMM,
 157                 FSL_DDR_ODT_OTHER_DIMM,
 158                 DDR3_RTT_20_OHM,
 159                 DDR3_RTT_OFF
 160         }
 161 };
 162
 163 static const struct dynamic_odt dual_SS[4] = {
 164         {       /* cs0 */
 165                 FSL_DDR_ODT_OTHER_DIMM,
 166                 FSL_DDR_ODT_ALL,
 167                 DDR3_RTT_30_OHM,
 168                 DDR3_RTT_120_OHM
 169         },
 170         {0, 0, 0, 0},
 171         {       /* cs2 */
 172                 FSL_DDR_ODT_OTHER_DIMM,
 173                 FSL_DDR_ODT_ALL,
 174                 DDR3_RTT_30_OHM,
 175                 DDR3_RTT_120_OHM
 176         },
 177         {0, 0, 0, 0}
 178 };
 179
 180 static const struct dynamic_odt dual_D0[4] = {
 181         {       /* cs0 */
 182                 FSL_DDR_ODT_NEVER,
 183                 FSL_DDR_ODT_SAME_DIMM,
 184                 DDR3_RTT_40_OHM,
 185                 DDR3_RTT_OFF
 186         },
 187         {       /* cs1 */
 188                 FSL_DDR_ODT_NEVER,
 189                 FSL_DDR_ODT_NEVER,
 190                 DDR3_RTT_OFF,
 191                 DDR3_RTT_OFF
 192         },
 193         {0, 0, 0, 0},
 194         {0, 0, 0, 0}
 195 };
 196
 197 static const struct dynamic_odt dual_0D[4] = {
 198         {0, 0, 0, 0},
 199         {0, 0, 0, 0},
 200         {       /* cs2 */
 201                 FSL_DDR_ODT_NEVER,
 202                 FSL_DDR_ODT_SAME_DIMM,
 203                 DDR3_RTT_40_OHM,
 204                 DDR3_RTT_OFF
 205         },
 206         {       /* cs3 */
 207                 FSL_DDR_ODT_NEVER,
 208                 FSL_DDR_ODT_NEVER,
 209                 DDR3_RTT_OFF,
 210                 DDR3_RTT_OFF
 211         }
 212 };
 213
 214 static const struct dynamic_odt dual_S0[4] = {
 215         {       /* cs0 */
 216                 FSL_DDR_ODT_NEVER,
 217                 FSL_DDR_ODT_CS,
 218                 DDR3_RTT_40_OHM,
 219                 DDR3_RTT_OFF
 220         },
 221         {0, 0, 0, 0},
 222         {0, 0, 0, 0},
 223         {0, 0, 0, 0}
 224
 225 };
 226
 227 static const struct dynamic_odt dual_0S[4] = {
 228         {0, 0, 0, 0},
 229         {0, 0, 0, 0},
 230         {       /* cs2 */
 231                 FSL_DDR_ODT_NEVER,
 232                 FSL_DDR_ODT_CS,
 233                 DDR3_RTT_40_OHM,
 234                 DDR3_RTT_OFF
 235         },
 236         {0, 0, 0, 0}
 237
 238 };
 239
 240 static const struct dynamic_odt odt_unknown[4] = {
 241         {       /* cs0 */
 242                 FSL_DDR_ODT_NEVER,
 243                 FSL_DDR_ODT_CS,
 244                 DDR3_RTT_120_OHM,
 245                 DDR3_RTT_OFF
 246         },
 247         {       /* cs1 */
 248                 FSL_DDR_ODT_NEVER,
 249                 FSL_DDR_ODT_CS,
 250                 DDR3_RTT_120_OHM,
 251                 DDR3_RTT_OFF
 252         },
 253         {       /* cs2 */
 254                 FSL_DDR_ODT_NEVER,
 255                 FSL_DDR_ODT_CS,
 256                 DDR3_RTT_120_OHM,
 257                 DDR3_RTT_OFF
 258         },
 259         {       /* cs3 */
 260                 FSL_DDR_ODT_NEVER,
 261                 FSL_DDR_ODT_CS,
 262                 DDR3_RTT_120_OHM,
 263                 DDR3_RTT_OFF
 264         }
 265 };
 266 #else   /* CONFIG_FSL_DDR3 */
 267 static const struct dynamic_odt single_Q[4] = {
 268         {0, 0, 0, 0},
 269         {0, 0, 0, 0},
 270         {0, 0, 0, 0},
 271         {0, 0, 0, 0}
 272 };
 273
 274 static const struct dynamic_odt single_D[4] = {
 275         {       /* cs0 */
 276                 FSL_DDR_ODT_NEVER,
 277                 FSL_DDR_ODT_ALL,
 278                 DDR2_RTT_150_OHM,
 279                 DDR2_RTT_OFF
 280         },
 281         {       /* cs1 */
 282                 FSL_DDR_ODT_NEVER,
 283                 FSL_DDR_ODT_NEVER,
 284                 DDR2_RTT_OFF,
 285                 DDR2_RTT_OFF
 286         },
 287         {0, 0, 0, 0},
 288         {0, 0, 0, 0}
 289 };
 290
 291 static const struct dynamic_odt single_S[4] = {
 292         {       /* cs0 */
 293                 FSL_DDR_ODT_NEVER,
 294                 FSL_DDR_ODT_ALL,
 295                 DDR2_RTT_150_OHM,
 296                 DDR2_RTT_OFF
 297         },
 298         {0, 0, 0, 0},
 299         {0, 0, 0, 0},
 300         {0, 0, 0, 0},
 301 };
 302
 303 static const struct dynamic_odt dual_DD[4] = {
 304         {       /* cs0 */
 305                 FSL_DDR_ODT_OTHER_DIMM,
 306                 FSL_DDR_ODT_OTHER_DIMM,
 307                 DDR2_RTT_75_OHM,
 308                 DDR2_RTT_OFF
 309         },
 310         {       /* cs1 */
 311                 FSL_DDR_ODT_NEVER,
 312                 FSL_DDR_ODT_NEVER,
 313                 DDR2_RTT_OFF,
 314                 DDR2_RTT_OFF
 315         },
 316         {       /* cs2 */
 317                 FSL_DDR_ODT_OTHER_DIMM,
 318                 FSL_DDR_ODT_OTHER_DIMM,
 319                 DDR2_RTT_75_OHM,
 320                 DDR2_RTT_OFF
 321         },
 322         {       /* cs3 */
 323                 FSL_DDR_ODT_NEVER,
 324                 FSL_DDR_ODT_NEVER,
 325                 DDR2_RTT_OFF,
 326                 DDR2_RTT_OFF
 327         }
 328 };
 329
 330 static const struct dynamic_odt dual_DS[4] = {
 331         {       /* cs0 */
 332                 FSL_DDR_ODT_OTHER_DIMM,
 333                 FSL_DDR_ODT_OTHER_DIMM,
 334                 DDR2_RTT_75_OHM,
 335                 DDR2_RTT_OFF
 336         },
 337         {       /* cs1 */
 338                 FSL_DDR_ODT_NEVER,
 339                 FSL_DDR_ODT_NEVER,
 340                 DDR2_RTT_OFF,
 341                 DDR2_RTT_OFF
 342         },
 343         {       /* cs2 */
 344                 FSL_DDR_ODT_OTHER_DIMM,
 345                 FSL_DDR_ODT_OTHER_DIMM,
 346                 DDR2_RTT_75_OHM,
 347                 DDR2_RTT_OFF
 348         },
 349         {0, 0, 0, 0}
 350 };
 351
 352 static const struct dynamic_odt dual_SD[4] = {
 353         {       /* cs0 */
 354                 FSL_DDR_ODT_OTHER_DIMM,
 355                 FSL_DDR_ODT_OTHER_DIMM,
 356                 DDR2_RTT_75_OHM,
 357                 DDR2_RTT_OFF
 358         },
 359         {0, 0, 0, 0},
 360         {       /* cs2 */
 361                 FSL_DDR_ODT_OTHER_DIMM,
 362                 FSL_DDR_ODT_OTHER_DIMM,
 363                 DDR2_RTT_75_OHM,
 364                 DDR2_RTT_OFF
 365         },
 366         {       /* cs3 */
 367                 FSL_DDR_ODT_NEVER,
 368                 FSL_DDR_ODT_NEVER,
 369                 DDR2_RTT_OFF,
 370                 DDR2_RTT_OFF
 371         }
 372 };
 373
 374 static const struct dynamic_odt dual_SS[4] = {
 375         {       /* cs0 */
 376                 FSL_DDR_ODT_OTHER_DIMM,
 377                 FSL_DDR_ODT_OTHER_DIMM,
 378                 DDR2_RTT_75_OHM,
 379                 DDR2_RTT_OFF
 380         },
 381         {0, 0, 0, 0},
 382         {       /* cs2 */
 383                 FSL_DDR_ODT_OTHER_DIMM,
 384                 FSL_DDR_ODT_OTHER_DIMM,
 385                 DDR2_RTT_75_OHM,
 386                 DDR2_RTT_OFF
 387         },
 388         {0, 0, 0, 0}
 389 };
 390
 391 static const struct dynamic_odt dual_D0[4] = {
 392         {       /* cs0 */
 393                 FSL_DDR_ODT_NEVER,
 394                 FSL_DDR_ODT_ALL,
 395                 DDR2_RTT_150_OHM,
 396                 DDR2_RTT_OFF
 397         },
 398         {       /* cs1 */
 399                 FSL_DDR_ODT_NEVER,
 400                 FSL_DDR_ODT_NEVER,
 401                 DDR2_RTT_OFF,
 402                 DDR2_RTT_OFF
 403         },
 404         {0, 0, 0, 0},
 405         {0, 0, 0, 0}
 406 };
 407
 408 static const struct dynamic_odt dual_0D[4] = {
 409         {0, 0, 0, 0},
 410         {0, 0, 0, 0},
 411         {       /* cs2 */
 412                 FSL_DDR_ODT_NEVER,
 413                 FSL_DDR_ODT_ALL,
 414                 DDR2_RTT_150_OHM,
 415                 DDR2_RTT_OFF
 416         },
 417         {       /* cs3 */
 418                 FSL_DDR_ODT_NEVER,
 419                 FSL_DDR_ODT_NEVER,
 420                 DDR2_RTT_OFF,
 421                 DDR2_RTT_OFF
 422         }
 423 };
 424
 425 static const struct dynamic_odt dual_S0[4] = {
 426         {       /* cs0 */
 427                 FSL_DDR_ODT_NEVER,
 428                 FSL_DDR_ODT_CS,
 429                 DDR2_RTT_150_OHM,
 430                 DDR2_RTT_OFF
 431         },
 432         {0, 0, 0, 0},
 433         {0, 0, 0, 0},
 434         {0, 0, 0, 0}
 435
 436 };
 437
 438 static const struct dynamic_odt dual_0S[4] = {
 439         {0, 0, 0, 0},
 440         {0, 0, 0, 0},
 441         {       /* cs2 */
 442                 FSL_DDR_ODT_NEVER,
 443                 FSL_DDR_ODT_CS,
 444                 DDR2_RTT_150_OHM,
 445                 DDR2_RTT_OFF
 446         },
 447         {0, 0, 0, 0}
 448
 449 };
 450
 451 static const struct dynamic_odt odt_unknown[4] = {
 452         {       /* cs0 */
 453                 FSL_DDR_ODT_NEVER,
 454                 FSL_DDR_ODT_CS,
 455                 DDR2_RTT_75_OHM,
 456                 DDR2_RTT_OFF
 457         },
 458         {       /* cs1 */
 459                 FSL_DDR_ODT_NEVER,
 460                 FSL_DDR_ODT_NEVER,
 461                 DDR2_RTT_OFF,
 462                 DDR2_RTT_OFF
 463         },
 464         {       /* cs2 */
 465                 FSL_DDR_ODT_NEVER,
 466                 FSL_DDR_ODT_CS,
 467                 DDR2_RTT_75_OHM,
 468                 DDR2_RTT_OFF
 469         },
 470         {       /* cs3 */
 471                 FSL_DDR_ODT_NEVER,
 472                 FSL_DDR_ODT_NEVER,
 473                 DDR2_RTT_OFF,
 474                 DDR2_RTT_OFF
 475         }
 476 };
 477 #endif
 478 unsigned int populate_memctl_options(int all_DIMMs_registered,
 479                         memctl_options_t *popts,
 480                         dimm_params_t *pdimm,
 481                         unsigned int ctrl_num)
 482 {
 483         unsigned int i;
 484         char buffer[HWCONFIG_BUFFER_SIZE];
 485         char *buf = NULL;
 486         const struct dynamic_odt *pdodt = odt_unknown;
 487         ulong ddr_freq;
 488
 489         /*
 490          * Extract hwconfig from environment since we have not properly setup
 491          * the environment but need it for ddr config params
 492          */
 493         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 494                 buf = buffer;
 495
 496         /* Chip select options. */
 497         if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
 498                 switch (pdimm[0].n_ranks) {
 499                 case 1:
 500                         pdodt = single_S;
 501                         break;
 502                 case 2:
 503                         pdodt = single_D;
 504                         break;
 505                 case 4:
 506                         pdodt = single_Q;
 507                         break;
 508                 }
 509         } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
 510                 switch (pdimm[0].n_ranks) {
 511                 case 2:
 512                         switch (pdimm[1].n_ranks) {
 513                         case 2:
 514                                 pdodt = dual_DD;
 515                                 break;
 516                         case 1:
 517                                 pdodt = dual_DS;
 518                                 break;
 519                         case 0:
 520                                 pdodt = dual_D0;
 521                                 break;
 522                         }
 523                         break;
 524                 case 1:
 525                         switch (pdimm[1].n_ranks) {
 526                         case 2:
 527                                 pdodt = dual_SD;
 528                                 break;
 529                         case 1:
 530                                 pdodt = dual_SS;
 531                                 break;
 532                         case 0:
 533                                 pdodt = dual_S0;
 534                                 break;
 535                         }
 536                         break;
 537                 case 0:
 538                         switch (pdimm[1].n_ranks) {
 539                         case 2:
 540                                 pdodt = dual_0D;
 541                                 break;
 542                         case 1:
 543                                 pdodt = dual_0S;
 544                                 break;
 545                         }
 546                         break;
 547                 }
 548         }
 549
 550         /* Pick chip-select local options. */
 551         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 552 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
 553                 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
 554                 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
 555                 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
 556                 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
 557 #else
 558                 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
 559                 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
 560 #endif
 561                 popts->cs_local_opts[i].auto_precharge = 0;
 562         }
 563
 564         /* Pick interleaving mode. */
 565
 566         /*
 567          * 0 = no interleaving
 568          * 1 = interleaving between 2 controllers
 569          */
 570         popts->memctl_interleaving = 0;
 571
 572         /*
 573          * 0 = cacheline
 574          * 1 = page
 575          * 2 = (logical) bank
 576          * 3 = superbank (only if CS interleaving is enabled)
 577          */
 578         popts->memctl_interleaving_mode = 0;
 579
 580         /*
 581          * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
 582          * 1: page:      bit to the left of the column bits selects the memctl
 583          * 2: bank:      bit to the left of the bank bits selects the memctl
 584          * 3: superbank: bit to the left of the chip select selects the memctl
 585          *
 586          * NOTE: ba_intlv (rank interleaving) is independent of memory
 587          * controller interleaving; it is only within a memory controller.
 588          * Must use superbank interleaving if rank interleaving is used and
 589          * memory controller interleaving is enabled.
 590          */
 591
 592         /*
 593          * 0 = no
 594          * 0x40 = CS0,CS1
 595          * 0x20 = CS2,CS3
 596          * 0x60 = CS0,CS1 + CS2,CS3
 597          * 0x04 = CS0,CS1,CS2,CS3
 598          */
 599         popts->ba_intlv_ctl = 0;
 600
 601         /* Memory Organization Parameters */
 602         popts->registered_dimm_en = all_DIMMs_registered;
 603
 604         /* Operational Mode Paramters */
 605
 606         /* Pick ECC modes */
 607         popts->ECC_mode = 0;              /* 0 = disabled, 1 = enabled */
 608 #ifdef CONFIG_DDR_ECC
 609         if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
 610                 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
 611                         popts->ECC_mode = 1;
 612         } else
 613                 popts->ECC_mode = 1;
 614 #endif
 615         popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
 616
 617         /*
 618          * Choose DQS config
 619          * 0 for DDR1
 620          * 1 for DDR2
 621          */
 622 #if defined(CONFIG_FSL_DDR1)
 623         popts->DQS_config = 0;
 624 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
 625         popts->DQS_config = 1;
 626 #endif
 627
 628         /* Choose self-refresh during sleep. */
 629         popts->self_refresh_in_sleep = 1;
 630
 631         /* Choose dynamic power management mode. */
 632         popts->dynamic_power = 0;
 633
 634         /*
 635          * check first dimm for primary sdram width
 636          * presuming all dimms are similar
 637          * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
 638          */
 639 #if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
 640         if (pdimm[0].n_ranks != 0) {
 641                 if ((pdimm[0].data_width >= 64) && \
 642                         (pdimm[0].data_width <= 72))
 643                         popts->data_bus_width = 0;
 644                 else if ((pdimm[0].data_width >= 32) || \
 645                         (pdimm[0].data_width <= 40))
 646                         popts->data_bus_width = 1;
 647                 else {
 648                         panic("Error: data width %u is invalid!\n",
 649                                 pdimm[0].data_width);
 650                 }
 651         }
 652 #else
 653         if (pdimm[0].n_ranks != 0) {
 654                 if (pdimm[0].primary_sdram_width == 64)
 655                         popts->data_bus_width = 0;
 656                 else if (pdimm[0].primary_sdram_width == 32)
 657                         popts->data_bus_width = 1;
 658                 else if (pdimm[0].primary_sdram_width == 16)
 659                         popts->data_bus_width = 2;
 660                 else {
 661                         panic("Error: primary sdram width %u is invalid!\n",
 662                                 pdimm[0].primary_sdram_width);
 663                 }
 664         }
 665 #endif
 666
 667         /* Choose burst length. */
 668 #if defined(CONFIG_FSL_DDR3)
 669 #if defined(CONFIG_E500MC)
 670         popts->OTF_burst_chop_en = 0;   /* on-the-fly burst chop disable */
 671         popts->burst_length = DDR_BL8;  /* Fixed 8-beat burst len */
 672 #else
 673         if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
 674                 /* 32-bit or 16-bit bus */
 675                 popts->OTF_burst_chop_en = 0;
 676                 popts->burst_length = DDR_BL8;
 677         } else {
 678                 popts->OTF_burst_chop_en = 1;   /* on-the-fly burst chop */
 679                 popts->burst_length = DDR_OTF;  /* on-the-fly BC4 and BL8 */
 680         }
 681 #endif
 682 #else
 683         popts->burst_length = DDR_BL4;  /* has to be 4 for DDR2 */
 684 #endif
 685
 686         /* Choose ddr controller address mirror mode */
 687 #if defined(CONFIG_FSL_DDR3)
 688         popts->mirrored_dimm = pdimm[0].mirrored_dimm;
 689 #endif
 690
 691         /* Global Timing Parameters. */
 692         debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
 693
 694         /* Pick a caslat override. */
 695         popts->cas_latency_override = 0;
 696         popts->cas_latency_override_value = 3;
 697         if (popts->cas_latency_override) {
 698                 debug("using caslat override value = %u\n",
 699                        popts->cas_latency_override_value);
 700         }
 701
 702         /* Decide whether to use the computed derated latency */
 703         popts->use_derated_caslat = 0;
 704
 705         /* Choose an additive latency. */
 706         popts->additive_latency_override = 0;
 707         popts->additive_latency_override_value = 3;
 708         if (popts->additive_latency_override) {
 709                 debug("using additive latency override value = %u\n",
 710                        popts->additive_latency_override_value);
 711         }
 712
 713         /*
 714          * 2T_EN setting
 715          *
 716          * Factors to consider for 2T_EN:
 717          *      - number of DIMMs installed
 718          *      - number of components, number of active ranks
 719          *      - how much time you want to spend playing around
 720          */
 721         popts->twoT_en = 0;
 722         popts->threeT_en = 0;
 723
 724         /* for RDIMM, address parity enable */
 725         popts->ap_en = 1;
 726
 727         /*
 728          * BSTTOPRE precharge interval
 729          *
 730          * Set this to 0 for global auto precharge
 731          *
 732          * FIXME: Should this be configured in picoseconds?
 733          * Why it should be in ps:  better understanding of this
 734          * relative to actual DRAM timing parameters such as tRAS.
 735          * e.g. tRAS(min) = 40 ns
 736          */
 737         popts->bstopre = 0x100;
 738
 739         /* Minimum CKE pulse width -- tCKE(MIN) */
 740         popts->tCKE_clock_pulse_width_ps
 741                 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
 742
 743         /*
 744          * Window for four activates -- tFAW
 745          *
 746          * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
 747          * FIXME: varies depending upon number of column addresses or data
 748          * FIXME: width, was considering looking at pdimm->primary_sdram_width
 749          */
 750 #if defined(CONFIG_FSL_DDR1)
 751         popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
 752
 753 #elif defined(CONFIG_FSL_DDR2)
 754         /*
 755          * x4/x8;  some datasheets have 35000
 756          * x16 wide columns only?  Use 50000?
 757          */
 758         popts->tFAW_window_four_activates_ps = 37500;
 759
 760 #elif defined(CONFIG_FSL_DDR3)
 761         popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
 762 #endif
 763         popts->zq_en = 0;
 764         popts->wrlvl_en = 0;
 765 #if defined(CONFIG_FSL_DDR3)
 766         /*
 767          * due to ddr3 dimm is fly-by topology
 768          * we suggest to enable write leveling to
 769          * meet the tQDSS under different loading.
 770          */
 771         popts->wrlvl_en = 1;
 772         popts->zq_en = 1;
 773         popts->wrlvl_override = 0;
 774 #endif
 775
 776         /*
 777          * Check interleaving configuration from environment.
 778          * Please refer to doc/README.fsl-ddr for the detail.
 779          *
 780          * If memory controller interleaving is enabled, then the data
 781          * bus widths must be programmed identically for all memory controllers.
 782          *
 783          * XXX: Attempt to set all controllers to the same chip select
 784          * interleaving mode. It will do a best effort to get the
 785          * requested ranks interleaved together such that the result
 786          * should be a subset of the requested configuration.
 787          */
 788 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 789         if (hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) {
 790                 if (pdimm[0].n_ranks == 0) {
 791                         printf("There is no rank on CS0 for controller %d. Because only"
 792                                 " rank on CS0 and ranks chip-select interleaved with CS0"
 793                                 " are controller interleaved, force non memory "
 794                                 "controller interleaving\n", ctrl_num);
 795                         popts->memctl_interleaving = 0;
 796                 } else {
 797                         popts->memctl_interleaving = 1;
 798                         /*
 799                          * test null first. if CONFIG_HWCONFIG is not defined
 800                          * hwconfig_arg_cmp returns non-zero
 801                          */
 802                         if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 803                                                     "null", buf)) {
 804                                 popts->memctl_interleaving = 0;
 805                                 debug("memory controller interleaving disabled.\n");
 806                         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 807                                                          "ctlr_intlv",
 808                                                          "cacheline", buf))
 809                                 popts->memctl_interleaving_mode =
 810                                         FSL_DDR_CACHE_LINE_INTERLEAVING;
 811                         else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 812                                                        "page", buf))
 813                                 popts->memctl_interleaving_mode =
 814                                         FSL_DDR_PAGE_INTERLEAVING;
 815                         else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 816                                                        "bank", buf))
 817                                 popts->memctl_interleaving_mode =
 818                                         FSL_DDR_BANK_INTERLEAVING;
 819                         else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 820                                                        "superbank", buf))
 821                                 popts->memctl_interleaving_mode =
 822                                         FSL_DDR_SUPERBANK_INTERLEAVING;
 823                         else {
 824                                 popts->memctl_interleaving = 0;
 825                                 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
 826                         }
 827                 }
 828         }
 829 #endif
 830         if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
 831                 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
 832                 /* test null first. if CONFIG_HWCONFIG is not defined,
 833                  * hwconfig_subarg_cmp_f returns non-zero */
 834                 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 835                                             "null", buf))
 836                         debug("bank interleaving disabled.\n");
 837                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 838                                                  "cs0_cs1", buf))
 839                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
 840                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 841                                                  "cs2_cs3", buf))
 842                         popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
 843                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 844                                                  "cs0_cs1_and_cs2_cs3", buf))
 845                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
 846                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 847                                                  "cs0_cs1_cs2_cs3", buf))
 848                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
 849                 else
 850                         printf("hwconfig has unrecognized parameter for bank_intlv.\n");
 851                 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 852                 case FSL_DDR_CS0_CS1_CS2_CS3:
 853 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 854                         if (pdimm[0].n_ranks < 4) {
 855                                 popts->ba_intlv_ctl = 0;
 856                                 printf("Not enough bank(chip-select) for "
 857                                         "CS0+CS1+CS2+CS3 on controller %d, "
 858                                         "force non-interleaving!\n", ctrl_num);
 859                         }
 860 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 861                         if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
 862                                 popts->ba_intlv_ctl = 0;
 863                                 printf("Not enough bank(chip-select) for "
 864                                         "CS0+CS1+CS2+CS3 on controller %d, "
 865                                         "force non-interleaving!\n", ctrl_num);
 866                         }
 867                         if (pdimm[0].capacity != pdimm[1].capacity) {
 868                                 popts->ba_intlv_ctl = 0;
 869                                 printf("Not identical DIMM size for "
 870                                         "CS0+CS1+CS2+CS3 on controller %d, "
 871                                         "force non-interleaving!\n", ctrl_num);
 872                         }
 873 #endif
 874                         break;
 875                 case FSL_DDR_CS0_CS1:
 876                         if (pdimm[0].n_ranks < 2) {
 877                                 popts->ba_intlv_ctl = 0;
 878                                 printf("Not enough bank(chip-select) for "
 879                                         "CS0+CS1 on controller %d, "
 880                                         "force non-interleaving!\n", ctrl_num);
 881                         }
 882                         break;
 883                 case FSL_DDR_CS2_CS3:
 884 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 885                         if (pdimm[0].n_ranks < 4) {
 886                                 popts->ba_intlv_ctl = 0;
 887                                 printf("Not enough bank(chip-select) for CS2+CS3 "
 888                                         "on controller %d, force non-interleaving!\n", ctrl_num);
 889                         }
 890 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 891                         if (pdimm[1].n_ranks < 2) {
 892                                 popts->ba_intlv_ctl = 0;
 893                                 printf("Not enough bank(chip-select) for CS2+CS3 "
 894                                         "on controller %d, force non-interleaving!\n", ctrl_num);
 895                         }
 896 #endif
 897                         break;
 898                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 899 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 900                         if (pdimm[0].n_ranks < 4) {
 901                                 popts->ba_intlv_ctl = 0;
 902                                 printf("Not enough bank(CS) for CS0+CS1 and "
 903                                         "CS2+CS3 on controller %d, "
 904                                         "force non-interleaving!\n", ctrl_num);
 905                         }
 906 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 907                         if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
 908                                 popts->ba_intlv_ctl = 0;
 909                                 printf("Not enough bank(CS) for CS0+CS1 and "
 910                                         "CS2+CS3 on controller %d, "
 911                                         "force non-interleaving!\n", ctrl_num);
 912                         }
 913 #endif
 914                         break;
 915                 default:
 916                         popts->ba_intlv_ctl = 0;
 917                         break;
 918                 }
 919         }
 920
 921         if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
 922                 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
 923                         popts->addr_hash = 0;
 924                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
 925                                                "true", buf))
 926                         popts->addr_hash = 1;
 927         }
 928
 929         if (pdimm[0].n_ranks == 4)
 930                 popts->quad_rank_present = 1;
 931
 932         ddr_freq = get_ddr_freq(0) / 1000000;
 933         if (popts->registered_dimm_en) {
 934                 popts->rcw_override = 1;
 935                 popts->rcw_1 = 0x000a5a00;
 936                 if (ddr_freq <= 800)
 937                         popts->rcw_2 = 0x00000000;
 938                 else if (ddr_freq <= 1066)
 939                         popts->rcw_2 = 0x00100000;
 940                 else if (ddr_freq <= 1333)
 941                         popts->rcw_2 = 0x00200000;
 942                 else
 943                         popts->rcw_2 = 0x00300000;
 944         }
 945
 946         fsl_ddr_board_options(popts, pdimm, ctrl_num);
 947
 948         return 0;
 949 }
 950
 951 void check_interleaving_options(fsl_ddr_info_t *pinfo)
 952 {
 953         int i, j, check_n_ranks, intlv_fixed = 0;
 954         unsigned long long check_rank_density;
 955         /*
 956          * Check if all controllers are configured for memory
 957          * controller interleaving. Identical dimms are recommended. At least
 958          * the size should be checked.
 959          */
 960         j = 0;
 961         check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
 962         check_rank_density = pinfo->dimm_params[0][0].rank_density;
 963         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 964                 if ((pinfo->memctl_opts[i].memctl_interleaving) && \
 965                     (check_rank_density == pinfo->dimm_params[i][0].rank_density) && \
 966                     (check_n_ranks == pinfo->dimm_params[i][0].n_ranks)) {
 967                         j++;
 968                 }
 969         }
 970         if (j != CONFIG_NUM_DDR_CONTROLLERS) {
 971                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 972                         if (pinfo->memctl_opts[i].memctl_interleaving) {
 973                                 pinfo->memctl_opts[i].memctl_interleaving = 0;
 974                                 intlv_fixed = 1;
 975                         }
 976                 if (intlv_fixed)
 977                         printf("Not all DIMMs are identical in size. "
 978                                 "Memory controller interleaving disabled.\n");
 979         }
 980 }
 981
 982 int fsl_use_spd(void)
 983 {
 984         int use_spd = 0;
 985
 986 #ifdef CONFIG_DDR_SPD
 987         char buffer[HWCONFIG_BUFFER_SIZE];
 988         char *buf = NULL;
 989
 990         /*
 991          * Extract hwconfig from environment since we have not properly setup
 992          * the environment but need it for ddr config params
 993          */
 994         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 995                 buf = buffer;
 996
 997         /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
 998         if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
 999                 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1000                         use_spd = 1;
1001                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
1002                                                "fixed", buf))
1003                         use_spd = 0;
1004                 else
1005                         use_spd = 1;
1006         } else
1007                 use_spd = 1;
1008 #endif
1009
1010         return use_spd;
1011 }