git.sur5r.net Git - u-boot/blob - arch/powerpc/cpu/mpc8xxx/ddr/options.c

   1 /*
   2  * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 #include <common.h>
  11 #include <hwconfig.h>
  12 #include <asm/fsl_ddr_sdram.h>
  13
  14 #include "ddr.h"
  15
  16 /*
  17  * Use our own stack based buffer before relocation to allow accessing longer
  18  * hwconfig strings that might be in the environment before we've relocated.
  19  * This is pretty fragile on both the use of stack and if the buffer is big
  20  * enough. However we will get a warning from getenv_f for the later.
  21  */
  22
  23 /* Board-specific functions defined in each board's ddr.c */
  24 extern void fsl_ddr_board_options(memctl_options_t *popts,
  25                 dimm_params_t *pdimm,
  26                 unsigned int ctrl_num);
  27
  28 struct dynamic_odt {
  29         unsigned int odt_rd_cfg;
  30         unsigned int odt_wr_cfg;
  31         unsigned int odt_rtt_norm;
  32         unsigned int odt_rtt_wr;
  33 };
  34
  35 #ifdef CONFIG_FSL_DDR3
  36 static const struct dynamic_odt single_Q[4] = {
  37         {       /* cs0 */
  38                 FSL_DDR_ODT_NEVER,
  39                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  40                 DDR3_RTT_20_OHM,
  41                 DDR3_RTT_120_OHM
  42         },
  43         {       /* cs1 */
  44                 FSL_DDR_ODT_NEVER,
  45                 FSL_DDR_ODT_NEVER,      /* tied high */
  46                 DDR3_RTT_OFF,
  47                 DDR3_RTT_120_OHM
  48         },
  49         {       /* cs2 */
  50                 FSL_DDR_ODT_NEVER,
  51                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  52                 DDR3_RTT_20_OHM,
  53                 DDR3_RTT_120_OHM
  54         },
  55         {       /* cs3 */
  56                 FSL_DDR_ODT_NEVER,
  57                 FSL_DDR_ODT_NEVER,      /* tied high */
  58                 DDR3_RTT_OFF,
  59                 DDR3_RTT_120_OHM
  60         }
  61 };
  62
  63 static const struct dynamic_odt single_D[4] = {
  64         {       /* cs0 */
  65                 FSL_DDR_ODT_NEVER,
  66                 FSL_DDR_ODT_ALL,
  67                 DDR3_RTT_40_OHM,
  68                 DDR3_RTT_OFF
  69         },
  70         {       /* cs1 */
  71                 FSL_DDR_ODT_NEVER,
  72                 FSL_DDR_ODT_NEVER,
  73                 DDR3_RTT_OFF,
  74                 DDR3_RTT_OFF
  75         },
  76         {0, 0, 0, 0},
  77         {0, 0, 0, 0}
  78 };
  79
  80 static const struct dynamic_odt single_S[4] = {
  81         {       /* cs0 */
  82                 FSL_DDR_ODT_NEVER,
  83                 FSL_DDR_ODT_ALL,
  84                 DDR3_RTT_40_OHM,
  85                 DDR3_RTT_OFF
  86         },
  87         {0, 0, 0, 0},
  88         {0, 0, 0, 0},
  89         {0, 0, 0, 0},
  90 };
  91
  92 static const struct dynamic_odt dual_DD[4] = {
  93         {       /* cs0 */
  94                 FSL_DDR_ODT_NEVER,
  95                 FSL_DDR_ODT_SAME_DIMM,
  96                 DDR3_RTT_120_OHM,
  97                 DDR3_RTT_OFF
  98         },
  99         {       /* cs1 */
 100                 FSL_DDR_ODT_OTHER_DIMM,
 101                 FSL_DDR_ODT_OTHER_DIMM,
 102                 DDR3_RTT_30_OHM,
 103                 DDR3_RTT_OFF
 104         },
 105         {       /* cs2 */
 106                 FSL_DDR_ODT_NEVER,
 107                 FSL_DDR_ODT_SAME_DIMM,
 108                 DDR3_RTT_120_OHM,
 109                 DDR3_RTT_OFF
 110         },
 111         {       /* cs3 */
 112                 FSL_DDR_ODT_OTHER_DIMM,
 113                 FSL_DDR_ODT_OTHER_DIMM,
 114                 DDR3_RTT_30_OHM,
 115                 DDR3_RTT_OFF
 116         }
 117 };
 118
 119 static const struct dynamic_odt dual_DS[4] = {
 120         {       /* cs0 */
 121                 FSL_DDR_ODT_NEVER,
 122                 FSL_DDR_ODT_SAME_DIMM,
 123                 DDR3_RTT_120_OHM,
 124                 DDR3_RTT_OFF
 125         },
 126         {       /* cs1 */
 127                 FSL_DDR_ODT_OTHER_DIMM,
 128                 FSL_DDR_ODT_OTHER_DIMM,
 129                 DDR3_RTT_30_OHM,
 130                 DDR3_RTT_OFF
 131         },
 132         {       /* cs2 */
 133                 FSL_DDR_ODT_OTHER_DIMM,
 134                 FSL_DDR_ODT_ALL,
 135                 DDR3_RTT_20_OHM,
 136                 DDR3_RTT_120_OHM
 137         },
 138         {0, 0, 0, 0}
 139 };
 140 static const struct dynamic_odt dual_SD[4] = {
 141         {       /* cs0 */
 142                 FSL_DDR_ODT_OTHER_DIMM,
 143                 FSL_DDR_ODT_ALL,
 144                 DDR3_RTT_20_OHM,
 145                 DDR3_RTT_120_OHM
 146         },
 147         {0, 0, 0, 0},
 148         {       /* cs2 */
 149                 FSL_DDR_ODT_NEVER,
 150                 FSL_DDR_ODT_SAME_DIMM,
 151                 DDR3_RTT_120_OHM,
 152                 DDR3_RTT_OFF
 153         },
 154         {       /* cs3 */
 155                 FSL_DDR_ODT_OTHER_DIMM,
 156                 FSL_DDR_ODT_OTHER_DIMM,
 157                 DDR3_RTT_20_OHM,
 158                 DDR3_RTT_OFF
 159         }
 160 };
 161
 162 static const struct dynamic_odt dual_SS[4] = {
 163         {       /* cs0 */
 164                 FSL_DDR_ODT_OTHER_DIMM,
 165                 FSL_DDR_ODT_ALL,
 166                 DDR3_RTT_30_OHM,
 167                 DDR3_RTT_120_OHM
 168         },
 169         {0, 0, 0, 0},
 170         {       /* cs2 */
 171                 FSL_DDR_ODT_OTHER_DIMM,
 172                 FSL_DDR_ODT_ALL,
 173                 DDR3_RTT_30_OHM,
 174                 DDR3_RTT_120_OHM
 175         },
 176         {0, 0, 0, 0}
 177 };
 178
 179 static const struct dynamic_odt dual_D0[4] = {
 180         {       /* cs0 */
 181                 FSL_DDR_ODT_NEVER,
 182                 FSL_DDR_ODT_SAME_DIMM,
 183                 DDR3_RTT_40_OHM,
 184                 DDR3_RTT_OFF
 185         },
 186         {       /* cs1 */
 187                 FSL_DDR_ODT_NEVER,
 188                 FSL_DDR_ODT_NEVER,
 189                 DDR3_RTT_OFF,
 190                 DDR3_RTT_OFF
 191         },
 192         {0, 0, 0, 0},
 193         {0, 0, 0, 0}
 194 };
 195
 196 static const struct dynamic_odt dual_0D[4] = {
 197         {0, 0, 0, 0},
 198         {0, 0, 0, 0},
 199         {       /* cs2 */
 200                 FSL_DDR_ODT_NEVER,
 201                 FSL_DDR_ODT_SAME_DIMM,
 202                 DDR3_RTT_40_OHM,
 203                 DDR3_RTT_OFF
 204         },
 205         {       /* cs3 */
 206                 FSL_DDR_ODT_NEVER,
 207                 FSL_DDR_ODT_NEVER,
 208                 DDR3_RTT_OFF,
 209                 DDR3_RTT_OFF
 210         }
 211 };
 212
 213 static const struct dynamic_odt dual_S0[4] = {
 214         {       /* cs0 */
 215                 FSL_DDR_ODT_NEVER,
 216                 FSL_DDR_ODT_CS,
 217                 DDR3_RTT_40_OHM,
 218                 DDR3_RTT_OFF
 219         },
 220         {0, 0, 0, 0},
 221         {0, 0, 0, 0},
 222         {0, 0, 0, 0}
 223
 224 };
 225
 226 static const struct dynamic_odt dual_0S[4] = {
 227         {0, 0, 0, 0},
 228         {0, 0, 0, 0},
 229         {       /* cs2 */
 230                 FSL_DDR_ODT_NEVER,
 231                 FSL_DDR_ODT_CS,
 232                 DDR3_RTT_40_OHM,
 233                 DDR3_RTT_OFF
 234         },
 235         {0, 0, 0, 0}
 236
 237 };
 238
 239 static const struct dynamic_odt odt_unknown[4] = {
 240         {       /* cs0 */
 241                 FSL_DDR_ODT_NEVER,
 242                 FSL_DDR_ODT_CS,
 243                 DDR3_RTT_120_OHM,
 244                 DDR3_RTT_OFF
 245         },
 246         {       /* cs1 */
 247                 FSL_DDR_ODT_NEVER,
 248                 FSL_DDR_ODT_CS,
 249                 DDR3_RTT_120_OHM,
 250                 DDR3_RTT_OFF
 251         },
 252         {       /* cs2 */
 253                 FSL_DDR_ODT_NEVER,
 254                 FSL_DDR_ODT_CS,
 255                 DDR3_RTT_120_OHM,
 256                 DDR3_RTT_OFF
 257         },
 258         {       /* cs3 */
 259                 FSL_DDR_ODT_NEVER,
 260                 FSL_DDR_ODT_CS,
 261                 DDR3_RTT_120_OHM,
 262                 DDR3_RTT_OFF
 263         }
 264 };
 265 #else   /* CONFIG_FSL_DDR3 */
 266 static const struct dynamic_odt single_Q[4] = {
 267         {0, 0, 0, 0},
 268         {0, 0, 0, 0},
 269         {0, 0, 0, 0},
 270         {0, 0, 0, 0}
 271 };
 272
 273 static const struct dynamic_odt single_D[4] = {
 274         {       /* cs0 */
 275                 FSL_DDR_ODT_NEVER,
 276                 FSL_DDR_ODT_ALL,
 277                 DDR2_RTT_150_OHM,
 278                 DDR2_RTT_OFF
 279         },
 280         {       /* cs1 */
 281                 FSL_DDR_ODT_NEVER,
 282                 FSL_DDR_ODT_NEVER,
 283                 DDR2_RTT_OFF,
 284                 DDR2_RTT_OFF
 285         },
 286         {0, 0, 0, 0},
 287         {0, 0, 0, 0}
 288 };
 289
 290 static const struct dynamic_odt single_S[4] = {
 291         {       /* cs0 */
 292                 FSL_DDR_ODT_NEVER,
 293                 FSL_DDR_ODT_ALL,
 294                 DDR2_RTT_150_OHM,
 295                 DDR2_RTT_OFF
 296         },
 297         {0, 0, 0, 0},
 298         {0, 0, 0, 0},
 299         {0, 0, 0, 0},
 300 };
 301
 302 static const struct dynamic_odt dual_DD[4] = {
 303         {       /* cs0 */
 304                 FSL_DDR_ODT_OTHER_DIMM,
 305                 FSL_DDR_ODT_OTHER_DIMM,
 306                 DDR2_RTT_75_OHM,
 307                 DDR2_RTT_OFF
 308         },
 309         {       /* cs1 */
 310                 FSL_DDR_ODT_NEVER,
 311                 FSL_DDR_ODT_NEVER,
 312                 DDR2_RTT_OFF,
 313                 DDR2_RTT_OFF
 314         },
 315         {       /* cs2 */
 316                 FSL_DDR_ODT_OTHER_DIMM,
 317                 FSL_DDR_ODT_OTHER_DIMM,
 318                 DDR2_RTT_75_OHM,
 319                 DDR2_RTT_OFF
 320         },
 321         {       /* cs3 */
 322                 FSL_DDR_ODT_NEVER,
 323                 FSL_DDR_ODT_NEVER,
 324                 DDR2_RTT_OFF,
 325                 DDR2_RTT_OFF
 326         }
 327 };
 328
 329 static const struct dynamic_odt dual_DS[4] = {
 330         {       /* cs0 */
 331                 FSL_DDR_ODT_OTHER_DIMM,
 332                 FSL_DDR_ODT_OTHER_DIMM,
 333                 DDR2_RTT_75_OHM,
 334                 DDR2_RTT_OFF
 335         },
 336         {       /* cs1 */
 337                 FSL_DDR_ODT_NEVER,
 338                 FSL_DDR_ODT_NEVER,
 339                 DDR2_RTT_OFF,
 340                 DDR2_RTT_OFF
 341         },
 342         {       /* cs2 */
 343                 FSL_DDR_ODT_OTHER_DIMM,
 344                 FSL_DDR_ODT_OTHER_DIMM,
 345                 DDR2_RTT_75_OHM,
 346                 DDR2_RTT_OFF
 347         },
 348         {0, 0, 0, 0}
 349 };
 350
 351 static const struct dynamic_odt dual_SD[4] = {
 352         {       /* cs0 */
 353                 FSL_DDR_ODT_OTHER_DIMM,
 354                 FSL_DDR_ODT_OTHER_DIMM,
 355                 DDR2_RTT_75_OHM,
 356                 DDR2_RTT_OFF
 357         },
 358         {0, 0, 0, 0},
 359         {       /* cs2 */
 360                 FSL_DDR_ODT_OTHER_DIMM,
 361                 FSL_DDR_ODT_OTHER_DIMM,
 362                 DDR2_RTT_75_OHM,
 363                 DDR2_RTT_OFF
 364         },
 365         {       /* cs3 */
 366                 FSL_DDR_ODT_NEVER,
 367                 FSL_DDR_ODT_NEVER,
 368                 DDR2_RTT_OFF,
 369                 DDR2_RTT_OFF
 370         }
 371 };
 372
 373 static const struct dynamic_odt dual_SS[4] = {
 374         {       /* cs0 */
 375                 FSL_DDR_ODT_OTHER_DIMM,
 376                 FSL_DDR_ODT_OTHER_DIMM,
 377                 DDR2_RTT_75_OHM,
 378                 DDR2_RTT_OFF
 379         },
 380         {0, 0, 0, 0},
 381         {       /* cs2 */
 382                 FSL_DDR_ODT_OTHER_DIMM,
 383                 FSL_DDR_ODT_OTHER_DIMM,
 384                 DDR2_RTT_75_OHM,
 385                 DDR2_RTT_OFF
 386         },
 387         {0, 0, 0, 0}
 388 };
 389
 390 static const struct dynamic_odt dual_D0[4] = {
 391         {       /* cs0 */
 392                 FSL_DDR_ODT_NEVER,
 393                 FSL_DDR_ODT_ALL,
 394                 DDR2_RTT_150_OHM,
 395                 DDR2_RTT_OFF
 396         },
 397         {       /* cs1 */
 398                 FSL_DDR_ODT_NEVER,
 399                 FSL_DDR_ODT_NEVER,
 400                 DDR2_RTT_OFF,
 401                 DDR2_RTT_OFF
 402         },
 403         {0, 0, 0, 0},
 404         {0, 0, 0, 0}
 405 };
 406
 407 static const struct dynamic_odt dual_0D[4] = {
 408         {0, 0, 0, 0},
 409         {0, 0, 0, 0},
 410         {       /* cs2 */
 411                 FSL_DDR_ODT_NEVER,
 412                 FSL_DDR_ODT_ALL,
 413                 DDR2_RTT_150_OHM,
 414                 DDR2_RTT_OFF
 415         },
 416         {       /* cs3 */
 417                 FSL_DDR_ODT_NEVER,
 418                 FSL_DDR_ODT_NEVER,
 419                 DDR2_RTT_OFF,
 420                 DDR2_RTT_OFF
 421         }
 422 };
 423
 424 static const struct dynamic_odt dual_S0[4] = {
 425         {       /* cs0 */
 426                 FSL_DDR_ODT_NEVER,
 427                 FSL_DDR_ODT_CS,
 428                 DDR2_RTT_150_OHM,
 429                 DDR2_RTT_OFF
 430         },
 431         {0, 0, 0, 0},
 432         {0, 0, 0, 0},
 433         {0, 0, 0, 0}
 434
 435 };
 436
 437 static const struct dynamic_odt dual_0S[4] = {
 438         {0, 0, 0, 0},
 439         {0, 0, 0, 0},
 440         {       /* cs2 */
 441                 FSL_DDR_ODT_NEVER,
 442                 FSL_DDR_ODT_CS,
 443                 DDR2_RTT_150_OHM,
 444                 DDR2_RTT_OFF
 445         },
 446         {0, 0, 0, 0}
 447
 448 };
 449
 450 static const struct dynamic_odt odt_unknown[4] = {
 451         {       /* cs0 */
 452                 FSL_DDR_ODT_NEVER,
 453                 FSL_DDR_ODT_CS,
 454                 DDR2_RTT_75_OHM,
 455                 DDR2_RTT_OFF
 456         },
 457         {       /* cs1 */
 458                 FSL_DDR_ODT_NEVER,
 459                 FSL_DDR_ODT_NEVER,
 460                 DDR2_RTT_OFF,
 461                 DDR2_RTT_OFF
 462         },
 463         {       /* cs2 */
 464                 FSL_DDR_ODT_NEVER,
 465                 FSL_DDR_ODT_CS,
 466                 DDR2_RTT_75_OHM,
 467                 DDR2_RTT_OFF
 468         },
 469         {       /* cs3 */
 470                 FSL_DDR_ODT_NEVER,
 471                 FSL_DDR_ODT_NEVER,
 472                 DDR2_RTT_OFF,
 473                 DDR2_RTT_OFF
 474         }
 475 };
 476 #endif
 477 unsigned int populate_memctl_options(int all_DIMMs_registered,
 478                         memctl_options_t *popts,
 479                         dimm_params_t *pdimm,
 480                         unsigned int ctrl_num)
 481 {
 482         unsigned int i;
 483         char buffer[HWCONFIG_BUFFER_SIZE];
 484         char *buf = NULL;
 485 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
 486         const struct dynamic_odt *pdodt = odt_unknown;
 487 #endif
 488         ulong ddr_freq;
 489
 490         /*
 491          * Extract hwconfig from environment since we have not properly setup
 492          * the environment but need it for ddr config params
 493          */
 494         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 495                 buf = buffer;
 496
 497 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
 498         /* Chip select options. */
 499         if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
 500                 switch (pdimm[0].n_ranks) {
 501                 case 1:
 502                         pdodt = single_S;
 503                         break;
 504                 case 2:
 505                         pdodt = single_D;
 506                         break;
 507                 case 4:
 508                         pdodt = single_Q;
 509                         break;
 510                 }
 511         } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
 512                 switch (pdimm[0].n_ranks) {
 513 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 514                 case 4:
 515                         pdodt = single_Q;
 516                         if (pdimm[1].n_ranks)
 517                                 printf("Error: Quad- and Dual-rank DIMMs "
 518                                         "cannot be used together\n");
 519                         break;
 520 #endif
 521                 case 2:
 522                         switch (pdimm[1].n_ranks) {
 523                         case 2:
 524                                 pdodt = dual_DD;
 525                                 break;
 526                         case 1:
 527                                 pdodt = dual_DS;
 528                                 break;
 529                         case 0:
 530                                 pdodt = dual_D0;
 531                                 break;
 532                         }
 533                         break;
 534                 case 1:
 535                         switch (pdimm[1].n_ranks) {
 536                         case 2:
 537                                 pdodt = dual_SD;
 538                                 break;
 539                         case 1:
 540                                 pdodt = dual_SS;
 541                                 break;
 542                         case 0:
 543                                 pdodt = dual_S0;
 544                                 break;
 545                         }
 546                         break;
 547                 case 0:
 548                         switch (pdimm[1].n_ranks) {
 549                         case 2:
 550                                 pdodt = dual_0D;
 551                                 break;
 552                         case 1:
 553                                 pdodt = dual_0S;
 554                                 break;
 555                         }
 556                         break;
 557                 }
 558         }
 559 #endif
 560
 561         /* Pick chip-select local options. */
 562         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 563 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
 564                 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
 565                 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
 566                 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
 567                 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
 568 #else
 569                 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
 570                 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
 571 #endif
 572                 popts->cs_local_opts[i].auto_precharge = 0;
 573         }
 574
 575         /* Pick interleaving mode. */
 576
 577         /*
 578          * 0 = no interleaving
 579          * 1 = interleaving between 2 controllers
 580          */
 581         popts->memctl_interleaving = 0;
 582
 583         /*
 584          * 0 = cacheline
 585          * 1 = page
 586          * 2 = (logical) bank
 587          * 3 = superbank (only if CS interleaving is enabled)
 588          */
 589         popts->memctl_interleaving_mode = 0;
 590
 591         /*
 592          * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
 593          * 1: page:      bit to the left of the column bits selects the memctl
 594          * 2: bank:      bit to the left of the bank bits selects the memctl
 595          * 3: superbank: bit to the left of the chip select selects the memctl
 596          *
 597          * NOTE: ba_intlv (rank interleaving) is independent of memory
 598          * controller interleaving; it is only within a memory controller.
 599          * Must use superbank interleaving if rank interleaving is used and
 600          * memory controller interleaving is enabled.
 601          */
 602
 603         /*
 604          * 0 = no
 605          * 0x40 = CS0,CS1
 606          * 0x20 = CS2,CS3
 607          * 0x60 = CS0,CS1 + CS2,CS3
 608          * 0x04 = CS0,CS1,CS2,CS3
 609          */
 610         popts->ba_intlv_ctl = 0;
 611
 612         /* Memory Organization Parameters */
 613         popts->registered_dimm_en = all_DIMMs_registered;
 614
 615         /* Operational Mode Paramters */
 616
 617         /* Pick ECC modes */
 618         popts->ECC_mode = 0;              /* 0 = disabled, 1 = enabled */
 619 #ifdef CONFIG_DDR_ECC
 620         if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
 621                 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
 622                         popts->ECC_mode = 1;
 623         } else
 624                 popts->ECC_mode = 1;
 625 #endif
 626         popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
 627
 628         /*
 629          * Choose DQS config
 630          * 0 for DDR1
 631          * 1 for DDR2
 632          */
 633 #if defined(CONFIG_FSL_DDR1)
 634         popts->DQS_config = 0;
 635 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
 636         popts->DQS_config = 1;
 637 #endif
 638
 639         /* Choose self-refresh during sleep. */
 640         popts->self_refresh_in_sleep = 1;
 641
 642         /* Choose dynamic power management mode. */
 643         popts->dynamic_power = 0;
 644
 645         /*
 646          * check first dimm for primary sdram width
 647          * presuming all dimms are similar
 648          * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
 649          */
 650 #if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
 651         if (pdimm[0].n_ranks != 0) {
 652                 if ((pdimm[0].data_width >= 64) && \
 653                         (pdimm[0].data_width <= 72))
 654                         popts->data_bus_width = 0;
 655                 else if ((pdimm[0].data_width >= 32) || \
 656                         (pdimm[0].data_width <= 40))
 657                         popts->data_bus_width = 1;
 658                 else {
 659                         panic("Error: data width %u is invalid!\n",
 660                                 pdimm[0].data_width);
 661                 }
 662         }
 663 #else
 664         if (pdimm[0].n_ranks != 0) {
 665                 if (pdimm[0].primary_sdram_width == 64)
 666                         popts->data_bus_width = 0;
 667                 else if (pdimm[0].primary_sdram_width == 32)
 668                         popts->data_bus_width = 1;
 669                 else if (pdimm[0].primary_sdram_width == 16)
 670                         popts->data_bus_width = 2;
 671                 else {
 672                         panic("Error: primary sdram width %u is invalid!\n",
 673                                 pdimm[0].primary_sdram_width);
 674                 }
 675         }
 676 #endif
 677
 678         /* Choose burst length. */
 679 #if defined(CONFIG_FSL_DDR3)
 680 #if defined(CONFIG_E500MC)
 681         popts->OTF_burst_chop_en = 0;   /* on-the-fly burst chop disable */
 682         popts->burst_length = DDR_BL8;  /* Fixed 8-beat burst len */
 683 #else
 684         if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
 685                 /* 32-bit or 16-bit bus */
 686                 popts->OTF_burst_chop_en = 0;
 687                 popts->burst_length = DDR_BL8;
 688         } else {
 689                 popts->OTF_burst_chop_en = 1;   /* on-the-fly burst chop */
 690                 popts->burst_length = DDR_OTF;  /* on-the-fly BC4 and BL8 */
 691         }
 692 #endif
 693 #else
 694         popts->burst_length = DDR_BL4;  /* has to be 4 for DDR2 */
 695 #endif
 696
 697         /* Choose ddr controller address mirror mode */
 698 #if defined(CONFIG_FSL_DDR3)
 699         popts->mirrored_dimm = pdimm[0].mirrored_dimm;
 700 #endif
 701
 702         /* Global Timing Parameters. */
 703         debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
 704
 705         /* Pick a caslat override. */
 706         popts->cas_latency_override = 0;
 707         popts->cas_latency_override_value = 3;
 708         if (popts->cas_latency_override) {
 709                 debug("using caslat override value = %u\n",
 710                        popts->cas_latency_override_value);
 711         }
 712
 713         /* Decide whether to use the computed derated latency */
 714         popts->use_derated_caslat = 0;
 715
 716         /* Choose an additive latency. */
 717         popts->additive_latency_override = 0;
 718         popts->additive_latency_override_value = 3;
 719         if (popts->additive_latency_override) {
 720                 debug("using additive latency override value = %u\n",
 721                        popts->additive_latency_override_value);
 722         }
 723
 724         /*
 725          * 2T_EN setting
 726          *
 727          * Factors to consider for 2T_EN:
 728          *      - number of DIMMs installed
 729          *      - number of components, number of active ranks
 730          *      - how much time you want to spend playing around
 731          */
 732         popts->twoT_en = 0;
 733         popts->threeT_en = 0;
 734
 735         /* for RDIMM, address parity enable */
 736         popts->ap_en = 1;
 737
 738         /*
 739          * BSTTOPRE precharge interval
 740          *
 741          * Set this to 0 for global auto precharge
 742          *
 743          * FIXME: Should this be configured in picoseconds?
 744          * Why it should be in ps:  better understanding of this
 745          * relative to actual DRAM timing parameters such as tRAS.
 746          * e.g. tRAS(min) = 40 ns
 747          */
 748         popts->bstopre = 0x100;
 749
 750         /* Minimum CKE pulse width -- tCKE(MIN) */
 751         popts->tCKE_clock_pulse_width_ps
 752                 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
 753
 754         /*
 755          * Window for four activates -- tFAW
 756          *
 757          * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
 758          * FIXME: varies depending upon number of column addresses or data
 759          * FIXME: width, was considering looking at pdimm->primary_sdram_width
 760          */
 761 #if defined(CONFIG_FSL_DDR1)
 762         popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
 763
 764 #elif defined(CONFIG_FSL_DDR2)
 765         /*
 766          * x4/x8;  some datasheets have 35000
 767          * x16 wide columns only?  Use 50000?
 768          */
 769         popts->tFAW_window_four_activates_ps = 37500;
 770
 771 #elif defined(CONFIG_FSL_DDR3)
 772         popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
 773 #endif
 774         popts->zq_en = 0;
 775         popts->wrlvl_en = 0;
 776 #if defined(CONFIG_FSL_DDR3)
 777         /*
 778          * due to ddr3 dimm is fly-by topology
 779          * we suggest to enable write leveling to
 780          * meet the tQDSS under different loading.
 781          */
 782         popts->wrlvl_en = 1;
 783         popts->zq_en = 1;
 784         popts->wrlvl_override = 0;
 785 #endif
 786
 787         /*
 788          * Check interleaving configuration from environment.
 789          * Please refer to doc/README.fsl-ddr for the detail.
 790          *
 791          * If memory controller interleaving is enabled, then the data
 792          * bus widths must be programmed identically for all memory controllers.
 793          *
 794          * XXX: Attempt to set all controllers to the same chip select
 795          * interleaving mode. It will do a best effort to get the
 796          * requested ranks interleaved together such that the result
 797          * should be a subset of the requested configuration.
 798          */
 799 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 800         if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
 801                 goto done;
 802
 803         if (pdimm[0].n_ranks == 0) {
 804                 printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
 805                 popts->memctl_interleaving = 0;
 806                 goto done;
 807         }
 808         popts->memctl_interleaving = 1;
 809         /*
 810          * test null first. if CONFIG_HWCONFIG is not defined
 811          * hwconfig_arg_cmp returns non-zero
 812          */
 813         if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 814                                     "null", buf)) {
 815                 popts->memctl_interleaving = 0;
 816                 debug("memory controller interleaving disabled.\n");
 817         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 818                                         "ctlr_intlv",
 819                                         "cacheline", buf)) {
 820                 popts->memctl_interleaving_mode =
 821                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 822                         0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
 823                 popts->memctl_interleaving =
 824                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 825                         0 : 1;
 826         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 827                                         "ctlr_intlv",
 828                                         "page", buf)) {
 829                 popts->memctl_interleaving_mode =
 830                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 831                         0 : FSL_DDR_PAGE_INTERLEAVING;
 832                 popts->memctl_interleaving =
 833                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 834                         0 : 1;
 835         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 836                                         "ctlr_intlv",
 837                                         "bank", buf)) {
 838                 popts->memctl_interleaving_mode =
 839                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 840                         0 : FSL_DDR_BANK_INTERLEAVING;
 841                 popts->memctl_interleaving =
 842                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 843                         0 : 1;
 844         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 845                                         "ctlr_intlv",
 846                                         "superbank", buf)) {
 847                 popts->memctl_interleaving_mode =
 848                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 849                         0 : FSL_DDR_SUPERBANK_INTERLEAVING;
 850                 popts->memctl_interleaving =
 851                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 852                         0 : 1;
 853 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
 854         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 855                                         "ctlr_intlv",
 856                                         "3way_1KB", buf)) {
 857                 popts->memctl_interleaving_mode =
 858                         FSL_DDR_3WAY_1KB_INTERLEAVING;
 859         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 860                                         "ctlr_intlv",
 861                                         "3way_4KB", buf)) {
 862                 popts->memctl_interleaving_mode =
 863                         FSL_DDR_3WAY_4KB_INTERLEAVING;
 864         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 865                                         "ctlr_intlv",
 866                                         "3way_8KB", buf)) {
 867                 popts->memctl_interleaving_mode =
 868                         FSL_DDR_3WAY_8KB_INTERLEAVING;
 869 #elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
 870         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 871                                         "ctlr_intlv",
 872                                         "4way_1KB", buf)) {
 873                 popts->memctl_interleaving_mode =
 874                         FSL_DDR_4WAY_1KB_INTERLEAVING;
 875         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 876                                         "ctlr_intlv",
 877                                         "4way_4KB", buf)) {
 878                 popts->memctl_interleaving_mode =
 879                         FSL_DDR_4WAY_4KB_INTERLEAVING;
 880         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 881                                         "ctlr_intlv",
 882                                         "4way_8KB", buf)) {
 883                 popts->memctl_interleaving_mode =
 884                         FSL_DDR_4WAY_8KB_INTERLEAVING;
 885 #endif
 886         } else {
 887                 popts->memctl_interleaving = 0;
 888                 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
 889         }
 890 done:
 891 #endif
 892         if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
 893                 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
 894                 /* test null first. if CONFIG_HWCONFIG is not defined,
 895                  * hwconfig_subarg_cmp_f returns non-zero */
 896                 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 897                                             "null", buf))
 898                         debug("bank interleaving disabled.\n");
 899                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 900                                                  "cs0_cs1", buf))
 901                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
 902                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 903                                                  "cs2_cs3", buf))
 904                         popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
 905                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 906                                                  "cs0_cs1_and_cs2_cs3", buf))
 907                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
 908                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 909                                                  "cs0_cs1_cs2_cs3", buf))
 910                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
 911                 else
 912                         printf("hwconfig has unrecognized parameter for bank_intlv.\n");
 913                 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 914                 case FSL_DDR_CS0_CS1_CS2_CS3:
 915 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 916                         if (pdimm[0].n_ranks < 4) {
 917                                 popts->ba_intlv_ctl = 0;
 918                                 printf("Not enough bank(chip-select) for "
 919                                         "CS0+CS1+CS2+CS3 on controller %d, "
 920                                         "interleaving disabled!\n", ctrl_num);
 921                         }
 922 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 923 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 924                         if (pdimm[0].n_ranks == 4)
 925                                 break;
 926 #endif
 927                         if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
 928                                 popts->ba_intlv_ctl = 0;
 929                                 printf("Not enough bank(chip-select) for "
 930                                         "CS0+CS1+CS2+CS3 on controller %d, "
 931                                         "interleaving disabled!\n", ctrl_num);
 932                         }
 933                         if (pdimm[0].capacity != pdimm[1].capacity) {
 934                                 popts->ba_intlv_ctl = 0;
 935                                 printf("Not identical DIMM size for "
 936                                         "CS0+CS1+CS2+CS3 on controller %d, "
 937                                         "interleaving disabled!\n", ctrl_num);
 938                         }
 939 #endif
 940                         break;
 941                 case FSL_DDR_CS0_CS1:
 942                         if (pdimm[0].n_ranks < 2) {
 943                                 popts->ba_intlv_ctl = 0;
 944                                 printf("Not enough bank(chip-select) for "
 945                                         "CS0+CS1 on controller %d, "
 946                                         "interleaving disabled!\n", ctrl_num);
 947                         }
 948                         break;
 949                 case FSL_DDR_CS2_CS3:
 950 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 951                         if (pdimm[0].n_ranks < 4) {
 952                                 popts->ba_intlv_ctl = 0;
 953                                 printf("Not enough bank(chip-select) for CS2+CS3 "
 954                                         "on controller %d, interleaving disabled!\n", ctrl_num);
 955                         }
 956 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 957                         if (pdimm[1].n_ranks < 2) {
 958                                 popts->ba_intlv_ctl = 0;
 959                                 printf("Not enough bank(chip-select) for CS2+CS3 "
 960                                         "on controller %d, interleaving disabled!\n", ctrl_num);
 961                         }
 962 #endif
 963                         break;
 964                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 965 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 966                         if (pdimm[0].n_ranks < 4) {
 967                                 popts->ba_intlv_ctl = 0;
 968                                 printf("Not enough bank(CS) for CS0+CS1 and "
 969                                         "CS2+CS3 on controller %d, "
 970                                         "interleaving disabled!\n", ctrl_num);
 971                         }
 972 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 973                         if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
 974                                 popts->ba_intlv_ctl = 0;
 975                                 printf("Not enough bank(CS) for CS0+CS1 and "
 976                                         "CS2+CS3 on controller %d, "
 977                                         "interleaving disabled!\n", ctrl_num);
 978                         }
 979 #endif
 980                         break;
 981                 default:
 982                         popts->ba_intlv_ctl = 0;
 983                         break;
 984                 }
 985         }
 986
 987         if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
 988                 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
 989                         popts->addr_hash = 0;
 990                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
 991                                                "true", buf))
 992                         popts->addr_hash = 1;
 993         }
 994
 995         if (pdimm[0].n_ranks == 4)
 996                 popts->quad_rank_present = 1;
 997
 998         ddr_freq = get_ddr_freq(0) / 1000000;
 999         if (popts->registered_dimm_en) {
1000                 popts->rcw_override = 1;
1001                 popts->rcw_1 = 0x000a5a00;
1002                 if (ddr_freq <= 800)
1003                         popts->rcw_2 = 0x00000000;
1004                 else if (ddr_freq <= 1066)
1005                         popts->rcw_2 = 0x00100000;
1006                 else if (ddr_freq <= 1333)
1007                         popts->rcw_2 = 0x00200000;
1008                 else
1009                         popts->rcw_2 = 0x00300000;
1010         }
1011
1012         fsl_ddr_board_options(popts, pdimm, ctrl_num);
1013
1014         return 0;
1015 }
1016
1017 void check_interleaving_options(fsl_ddr_info_t *pinfo)
1018 {
1019         int i, j, k, check_n_ranks, intlv_invalid = 0;
1020         unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
1021         unsigned long long check_rank_density;
1022         struct dimm_params_s *dimm;
1023         /*
1024          * Check if all controllers are configured for memory
1025          * controller interleaving. Identical dimms are recommended. At least
1026          * the size, row and col address should be checked.
1027          */
1028         j = 0;
1029         check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
1030         check_rank_density = pinfo->dimm_params[0][0].rank_density;
1031         check_n_row_addr =  pinfo->dimm_params[0][0].n_row_addr;
1032         check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr;
1033         check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode;
1034         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1035                 dimm = &pinfo->dimm_params[i][0];
1036                 if (!pinfo->memctl_opts[i].memctl_interleaving) {
1037                         continue;
1038                 } else if (((check_rank_density != dimm->rank_density) ||
1039                      (check_n_ranks != dimm->n_ranks) ||
1040                      (check_n_row_addr != dimm->n_row_addr) ||
1041                      (check_n_col_addr != dimm->n_col_addr) ||
1042                      (check_intlv !=
1043                         pinfo->memctl_opts[i].memctl_interleaving_mode))){
1044                         intlv_invalid = 1;
1045                         break;
1046                 } else {
1047                         j++;
1048                 }
1049
1050         }
1051         if (intlv_invalid) {
1052                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
1053                         pinfo->memctl_opts[i].memctl_interleaving = 0;
1054                 printf("Not all DIMMs are identical. "
1055                         "Memory controller interleaving disabled.\n");
1056         } else {
1057                 switch (check_intlv) {
1058                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
1059                 case FSL_DDR_PAGE_INTERLEAVING:
1060                 case FSL_DDR_BANK_INTERLEAVING:
1061                 case FSL_DDR_SUPERBANK_INTERLEAVING:
1062                         if (3 == CONFIG_NUM_DDR_CONTROLLERS)
1063                                 k = 2;
1064                         else
1065                                 k = CONFIG_NUM_DDR_CONTROLLERS;
1066                         break;
1067                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
1068                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
1069                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
1070                 case FSL_DDR_4WAY_1KB_INTERLEAVING:
1071                 case FSL_DDR_4WAY_4KB_INTERLEAVING:
1072                 case FSL_DDR_4WAY_8KB_INTERLEAVING:
1073                 default:
1074                         k = CONFIG_NUM_DDR_CONTROLLERS;
1075                         break;
1076                 }
1077                 debug("%d of %d controllers are interleaving.\n", j, k);
1078                 if (j != k) {
1079                         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
1080                                 pinfo->memctl_opts[i].memctl_interleaving = 0;
1081                         printf("Not all controllers have compatible "
1082                                 "interleaving mode. All disabled.\n");
1083                 }
1084         }
1085         debug("Checking interleaving options completed\n");
1086 }
1087
1088 int fsl_use_spd(void)
1089 {
1090         int use_spd = 0;
1091
1092 #ifdef CONFIG_DDR_SPD
1093         char buffer[HWCONFIG_BUFFER_SIZE];
1094         char *buf = NULL;
1095
1096         /*
1097          * Extract hwconfig from environment since we have not properly setup
1098          * the environment but need it for ddr config params
1099          */
1100         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
1101                 buf = buffer;
1102
1103         /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1104         if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1105                 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1106                         use_spd = 1;
1107                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
1108                                                "fixed", buf))
1109                         use_spd = 0;
1110                 else
1111                         use_spd = 1;
1112         } else
1113                 use_spd = 1;
1114 #endif
1115
1116         return use_spd;
1117 }