git.sur5r.net Git - u-boot/blob - arch/powerpc/cpu/mpc8xxx/ddr/options.c

   1 /*
   2  * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 #include <common.h>
  11 #include <hwconfig.h>
  12 #include <asm/fsl_ddr_sdram.h>
  13
  14 #include "ddr.h"
  15
  16 /*
  17  * Use our own stack based buffer before relocation to allow accessing longer
  18  * hwconfig strings that might be in the environment before we've relocated.
  19  * This is pretty fragile on both the use of stack and if the buffer is big
  20  * enough. However we will get a warning from getenv_f for the later.
  21  */
  22 #define HWCONFIG_BUFFER_SIZE    128
  23
  24 /* Board-specific functions defined in each board's ddr.c */
  25 extern void fsl_ddr_board_options(memctl_options_t *popts,
  26                 dimm_params_t *pdimm,
  27                 unsigned int ctrl_num);
  28
  29 unsigned int populate_memctl_options(int all_DIMMs_registered,
  30                         memctl_options_t *popts,
  31                         dimm_params_t *pdimm,
  32                         unsigned int ctrl_num)
  33 {
  34         unsigned int i;
  35         char buffer[HWCONFIG_BUFFER_SIZE];
  36         char *buf = NULL;
  37
  38         /*
  39          * Extract hwconfig from environment since we have not properly setup
  40          * the environment but need it for ddr config params
  41          */
  42         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
  43                 buf = buffer;
  44
  45         /* Chip select options. */
  46
  47         /* Pick chip-select local options. */
  48         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  49                 /* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */
  50
  51                 /* only for single CS? */
  52                 popts->cs_local_opts[i].odt_rd_cfg = 0;
  53
  54                 popts->cs_local_opts[i].odt_wr_cfg = 1;
  55                 popts->cs_local_opts[i].auto_precharge = 0;
  56         }
  57
  58         /* Pick interleaving mode. */
  59
  60         /*
  61          * 0 = no interleaving
  62          * 1 = interleaving between 2 controllers
  63          */
  64         popts->memctl_interleaving = 0;
  65
  66         /*
  67          * 0 = cacheline
  68          * 1 = page
  69          * 2 = (logical) bank
  70          * 3 = superbank (only if CS interleaving is enabled)
  71          */
  72         popts->memctl_interleaving_mode = 0;
  73
  74         /*
  75          * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
  76          * 1: page:      bit to the left of the column bits selects the memctl
  77          * 2: bank:      bit to the left of the bank bits selects the memctl
  78          * 3: superbank: bit to the left of the chip select selects the memctl
  79          *
  80          * NOTE: ba_intlv (rank interleaving) is independent of memory
  81          * controller interleaving; it is only within a memory controller.
  82          * Must use superbank interleaving if rank interleaving is used and
  83          * memory controller interleaving is enabled.
  84          */
  85
  86         /*
  87          * 0 = no
  88          * 0x40 = CS0,CS1
  89          * 0x20 = CS2,CS3
  90          * 0x60 = CS0,CS1 + CS2,CS3
  91          * 0x04 = CS0,CS1,CS2,CS3
  92          */
  93         popts->ba_intlv_ctl = 0;
  94
  95         /* Memory Organization Parameters */
  96         popts->registered_dimm_en = all_DIMMs_registered;
  97
  98         /* Operational Mode Paramters */
  99
 100         /* Pick ECC modes */
 101         popts->ECC_mode = 0;              /* 0 = disabled, 1 = enabled */
 102 #ifdef CONFIG_DDR_ECC
 103         if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
 104                 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
 105                         popts->ECC_mode = 1;
 106         } else
 107                 popts->ECC_mode = 1;
 108 #endif
 109         popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
 110
 111         /*
 112          * Choose DQS config
 113          * 0 for DDR1
 114          * 1 for DDR2
 115          */
 116 #if defined(CONFIG_FSL_DDR1)
 117         popts->DQS_config = 0;
 118 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
 119         popts->DQS_config = 1;
 120 #endif
 121
 122         /* Choose self-refresh during sleep. */
 123         popts->self_refresh_in_sleep = 1;
 124
 125         /* Choose dynamic power management mode. */
 126         popts->dynamic_power = 0;
 127
 128         /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
 129         popts->data_bus_width = 0;
 130
 131         /* Choose burst length. */
 132 #if defined(CONFIG_FSL_DDR3)
 133 #if defined(CONFIG_E500MC)
 134         popts->OTF_burst_chop_en = 0;   /* on-the-fly burst chop disable */
 135         popts->burst_length = DDR_BL8;  /* Fixed 8-beat burst len */
 136 #else
 137         popts->OTF_burst_chop_en = 1;   /* on-the-fly burst chop */
 138         popts->burst_length = DDR_OTF;  /* on-the-fly BC4 and BL8 */
 139 #endif
 140 #else
 141         popts->burst_length = DDR_BL4;  /* has to be 4 for DDR2 */
 142 #endif
 143
 144         /* Choose ddr controller address mirror mode */
 145 #if defined(CONFIG_FSL_DDR3)
 146         popts->mirrored_dimm = pdimm[0].mirrored_dimm;
 147 #endif
 148
 149         /* Global Timing Parameters. */
 150         debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
 151
 152         /* Pick a caslat override. */
 153         popts->cas_latency_override = 0;
 154         popts->cas_latency_override_value = 3;
 155         if (popts->cas_latency_override) {
 156                 debug("using caslat override value = %u\n",
 157                        popts->cas_latency_override_value);
 158         }
 159
 160         /* Decide whether to use the computed derated latency */
 161         popts->use_derated_caslat = 0;
 162
 163         /* Choose an additive latency. */
 164         popts->additive_latency_override = 0;
 165         popts->additive_latency_override_value = 3;
 166         if (popts->additive_latency_override) {
 167                 debug("using additive latency override value = %u\n",
 168                        popts->additive_latency_override_value);
 169         }
 170
 171         /*
 172          * 2T_EN setting
 173          *
 174          * Factors to consider for 2T_EN:
 175          *      - number of DIMMs installed
 176          *      - number of components, number of active ranks
 177          *      - how much time you want to spend playing around
 178          */
 179         popts->twoT_en = 0;
 180         popts->threeT_en = 0;
 181
 182         /*
 183          * BSTTOPRE precharge interval
 184          *
 185          * Set this to 0 for global auto precharge
 186          *
 187          * FIXME: Should this be configured in picoseconds?
 188          * Why it should be in ps:  better understanding of this
 189          * relative to actual DRAM timing parameters such as tRAS.
 190          * e.g. tRAS(min) = 40 ns
 191          */
 192         popts->bstopre = 0x100;
 193
 194         /* Minimum CKE pulse width -- tCKE(MIN) */
 195         popts->tCKE_clock_pulse_width_ps
 196                 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
 197
 198         /*
 199          * Window for four activates -- tFAW
 200          *
 201          * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
 202          * FIXME: varies depending upon number of column addresses or data
 203          * FIXME: width, was considering looking at pdimm->primary_sdram_width
 204          */
 205 #if defined(CONFIG_FSL_DDR1)
 206         popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
 207
 208 #elif defined(CONFIG_FSL_DDR2)
 209         /*
 210          * x4/x8;  some datasheets have 35000
 211          * x16 wide columns only?  Use 50000?
 212          */
 213         popts->tFAW_window_four_activates_ps = 37500;
 214
 215 #elif defined(CONFIG_FSL_DDR3)
 216         popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
 217 #endif
 218         popts->zq_en = 0;
 219         popts->wrlvl_en = 0;
 220 #if defined(CONFIG_FSL_DDR3)
 221         /*
 222          * due to ddr3 dimm is fly-by topology
 223          * we suggest to enable write leveling to
 224          * meet the tQDSS under different loading.
 225          */
 226         popts->wrlvl_en = 1;
 227         popts->zq_en = 1;
 228         popts->wrlvl_override = 0;
 229 #endif
 230
 231         /*
 232          * Check interleaving configuration from environment.
 233          * Please refer to doc/README.fsl-ddr for the detail.
 234          *
 235          * If memory controller interleaving is enabled, then the data
 236          * bus widths must be programmed identically for all memory controllers.
 237          *
 238          * XXX: Attempt to set all controllers to the same chip select
 239          * interleaving mode. It will do a best effort to get the
 240          * requested ranks interleaved together such that the result
 241          * should be a subset of the requested configuration.
 242          */
 243 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 244         if (hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) {
 245                 if (pdimm[0].n_ranks == 0) {
 246                         printf("There is no rank on CS0 for controller %d. Because only"
 247                                 " rank on CS0 and ranks chip-select interleaved with CS0"
 248                                 " are controller interleaved, force non memory "
 249                                 "controller interleaving\n", ctrl_num);
 250                         popts->memctl_interleaving = 0;
 251                 } else {
 252                         popts->memctl_interleaving = 1;
 253                         /*
 254                          * test null first. if CONFIG_HWCONFIG is not defined
 255                          * hwconfig_arg_cmp returns non-zero
 256                          */
 257                         if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 258                                                     "null", buf)) {
 259                                 popts->memctl_interleaving = 0;
 260                                 debug("memory controller interleaving disabled.\n");
 261                         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 262                                                          "ctlr_intlv",
 263                                                          "cacheline", buf))
 264                                 popts->memctl_interleaving_mode =
 265                                         FSL_DDR_CACHE_LINE_INTERLEAVING;
 266                         else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 267                                                        "page", buf))
 268                                 popts->memctl_interleaving_mode =
 269                                         FSL_DDR_PAGE_INTERLEAVING;
 270                         else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 271                                                        "bank", buf))
 272                                 popts->memctl_interleaving_mode =
 273                                         FSL_DDR_BANK_INTERLEAVING;
 274                         else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 275                                                        "superbank", buf))
 276                                 popts->memctl_interleaving_mode =
 277                                         FSL_DDR_SUPERBANK_INTERLEAVING;
 278                         else {
 279                                 popts->memctl_interleaving = 0;
 280                                 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
 281                         }
 282                 }
 283         }
 284 #endif
 285         if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
 286                 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
 287                 /* test null first. if CONFIG_HWCONFIG is not defined,
 288                  * hwconfig_subarg_cmp_f returns non-zero */
 289                 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 290                                             "null", buf))
 291                         debug("bank interleaving disabled.\n");
 292                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 293                                                  "cs0_cs1", buf))
 294                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
 295                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 296                                                  "cs2_cs3", buf))
 297                         popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
 298                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 299                                                  "cs0_cs1_and_cs2_cs3", buf))
 300                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
 301                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 302                                                  "cs0_cs1_cs2_cs3", buf))
 303                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
 304                 else
 305                         printf("hwconfig has unrecognized parameter for bank_intlv.\n");
 306                 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 307                 case FSL_DDR_CS0_CS1_CS2_CS3:
 308 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 309                         if (pdimm[0].n_ranks < 4) {
 310                                 popts->ba_intlv_ctl = 0;
 311                                 printf("Not enough bank(chip-select) for "
 312                                         "CS0+CS1+CS2+CS3 on controller %d, "
 313                                         "force non-interleaving!\n", ctrl_num);
 314                         }
 315 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 316                         if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
 317                                 popts->ba_intlv_ctl = 0;
 318                                 printf("Not enough bank(chip-select) for "
 319                                         "CS0+CS1+CS2+CS3 on controller %d, "
 320                                         "force non-interleaving!\n", ctrl_num);
 321                         }
 322                         if (pdimm[0].capacity != pdimm[1].capacity) {
 323                                 popts->ba_intlv_ctl = 0;
 324                                 printf("Not identical DIMM size for "
 325                                         "CS0+CS1+CS2+CS3 on controller %d, "
 326                                         "force non-interleaving!\n", ctrl_num);
 327                         }
 328 #endif
 329                         break;
 330                 case FSL_DDR_CS0_CS1:
 331                         if (pdimm[0].n_ranks < 2) {
 332                                 popts->ba_intlv_ctl = 0;
 333                                 printf("Not enough bank(chip-select) for "
 334                                         "CS0+CS1 on controller %d, "
 335                                         "force non-interleaving!\n", ctrl_num);
 336                         }
 337                         break;
 338                 case FSL_DDR_CS2_CS3:
 339 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 340                         if (pdimm[0].n_ranks < 4) {
 341                                 popts->ba_intlv_ctl = 0;
 342                                 printf("Not enough bank(chip-select) for CS2+CS3 "
 343                                         "on controller %d, force non-interleaving!\n", ctrl_num);
 344                         }
 345 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 346                         if (pdimm[1].n_ranks < 2) {
 347                                 popts->ba_intlv_ctl = 0;
 348                                 printf("Not enough bank(chip-select) for CS2+CS3 "
 349                                         "on controller %d, force non-interleaving!\n", ctrl_num);
 350                         }
 351 #endif
 352                         break;
 353                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 354 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 355                         if (pdimm[0].n_ranks < 4) {
 356                                 popts->ba_intlv_ctl = 0;
 357                                 printf("Not enough bank(CS) for CS0+CS1 and "
 358                                         "CS2+CS3 on controller %d, "
 359                                         "force non-interleaving!\n", ctrl_num);
 360                         }
 361 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 362                         if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
 363                                 popts->ba_intlv_ctl = 0;
 364                                 printf("Not enough bank(CS) for CS0+CS1 and "
 365                                         "CS2+CS3 on controller %d, "
 366                                         "force non-interleaving!\n", ctrl_num);
 367                         }
 368 #endif
 369                         break;
 370                 default:
 371                         popts->ba_intlv_ctl = 0;
 372                         break;
 373                 }
 374         }
 375
 376         if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
 377                 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
 378                         popts->addr_hash = 0;
 379                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
 380                                                "true", buf))
 381                         popts->addr_hash = 1;
 382         }
 383
 384         if (pdimm[0].n_ranks == 4)
 385                 popts->quad_rank_present = 1;
 386
 387         fsl_ddr_board_options(popts, pdimm, ctrl_num);
 388
 389         return 0;
 390 }
 391
 392 void check_interleaving_options(fsl_ddr_info_t *pinfo)
 393 {
 394         int i, j, check_n_ranks, intlv_fixed = 0;
 395         unsigned long long check_rank_density;
 396         /*
 397          * Check if all controllers are configured for memory
 398          * controller interleaving. Identical dimms are recommended. At least
 399          * the size should be checked.
 400          */
 401         j = 0;
 402         check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
 403         check_rank_density = pinfo->dimm_params[0][0].rank_density;
 404         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 405                 if ((pinfo->memctl_opts[i].memctl_interleaving) && \
 406                     (check_rank_density == pinfo->dimm_params[i][0].rank_density) && \
 407                     (check_n_ranks == pinfo->dimm_params[i][0].n_ranks)) {
 408                         j++;
 409                 }
 410         }
 411         if (j != CONFIG_NUM_DDR_CONTROLLERS) {
 412                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 413                         if (pinfo->memctl_opts[i].memctl_interleaving) {
 414                                 pinfo->memctl_opts[i].memctl_interleaving = 0;
 415                                 intlv_fixed = 1;
 416                         }
 417                 if (intlv_fixed)
 418                         printf("Not all DIMMs are identical in size. "
 419                                 "Memory controller interleaving disabled.\n");
 420         }
 421 }
 422
 423 int fsl_use_spd(void)
 424 {
 425         int use_spd = 0;
 426
 427 #ifdef CONFIG_DDR_SPD
 428         char buffer[HWCONFIG_BUFFER_SIZE];
 429         char *buf = NULL;
 430
 431         /*
 432          * Extract hwconfig from environment since we have not properly setup
 433          * the environment but need it for ddr config params
 434          */
 435         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 436                 buf = buffer;
 437
 438         /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
 439         if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
 440                 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
 441                         use_spd = 1;
 442                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
 443                                                "fixed", buf))
 444                         use_spd = 0;
 445                 else
 446                         use_spd = 1;
 447         } else
 448                 use_spd = 1;
 449 #endif
 450
 451         return use_spd;
 452 }