2 * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
12 #include <asm/fsl_ddr_sdram.h>
17 * Use our own stack based buffer before relocation to allow accessing longer
18 * hwconfig strings that might be in the environment before we've relocated.
19 * This is pretty fragile on both the use of stack and if the buffer is big
20 * enough. However we will get a warning from getenv_f for the later.
22 #define HWCONFIG_BUFFER_SIZE 128
24 /* Board-specific functions defined in each board's ddr.c */
25 extern void fsl_ddr_board_options(memctl_options_t *popts,
27 unsigned int ctrl_num);
30 unsigned int odt_rd_cfg;
31 unsigned int odt_wr_cfg;
32 unsigned int odt_rtt_norm;
33 unsigned int odt_rtt_wr;
36 static const dynamic_odt_t single_Q[4] = {
39 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
45 FSL_DDR_ODT_NEVER, /* tied high */
51 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
57 FSL_DDR_ODT_NEVER, /* tied high */
63 static const dynamic_odt_t single_D[4] = {
80 static const dynamic_odt_t single_S[4] = {
92 static const dynamic_odt_t dual_DD[4] = {
95 FSL_DDR_ODT_SAME_DIMM,
100 FSL_DDR_ODT_OTHER_DIMM,
101 FSL_DDR_ODT_OTHER_DIMM,
107 FSL_DDR_ODT_SAME_DIMM,
112 FSL_DDR_ODT_OTHER_DIMM,
113 FSL_DDR_ODT_OTHER_DIMM,
119 static const dynamic_odt_t dual_DS[4] = {
122 FSL_DDR_ODT_SAME_DIMM,
127 FSL_DDR_ODT_OTHER_DIMM,
128 FSL_DDR_ODT_OTHER_DIMM,
133 FSL_DDR_ODT_OTHER_DIMM,
140 static const dynamic_odt_t dual_SD[4] = {
142 FSL_DDR_ODT_OTHER_DIMM,
150 FSL_DDR_ODT_SAME_DIMM,
155 FSL_DDR_ODT_OTHER_DIMM,
156 FSL_DDR_ODT_OTHER_DIMM,
162 static const dynamic_odt_t dual_SS[4] = {
164 FSL_DDR_ODT_OTHER_DIMM,
171 FSL_DDR_ODT_OTHER_DIMM,
179 static const dynamic_odt_t dual_D0[4] = {
182 FSL_DDR_ODT_SAME_DIMM,
196 static const dynamic_odt_t dual_0D[4] = {
201 FSL_DDR_ODT_SAME_DIMM,
213 static const dynamic_odt_t dual_S0[4] = {
226 static const dynamic_odt_t dual_0S[4] = {
239 static const dynamic_odt_t odt_unknown[4] = {
266 unsigned int populate_memctl_options(int all_DIMMs_registered,
267 memctl_options_t *popts,
268 dimm_params_t *pdimm,
269 unsigned int ctrl_num)
272 char buffer[HWCONFIG_BUFFER_SIZE];
274 const dynamic_odt_t *pdodt = odt_unknown;
277 * Extract hwconfig from environment since we have not properly setup
278 * the environment but need it for ddr config params
280 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
283 /* Chip select options. */
284 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
285 switch (pdimm[0].n_ranks) {
296 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
297 switch (pdimm[0].n_ranks) {
299 switch (pdimm[1].n_ranks) {
312 switch (pdimm[1].n_ranks) {
325 switch (pdimm[1].n_ranks) {
337 /* Pick chip-select local options. */
338 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
339 #if defined(CONFIG_FSL_DDR3)
340 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
341 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
342 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
343 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
345 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
346 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
348 popts->cs_local_opts[i].auto_precharge = 0;
351 /* Pick interleaving mode. */
354 * 0 = no interleaving
355 * 1 = interleaving between 2 controllers
357 popts->memctl_interleaving = 0;
363 * 3 = superbank (only if CS interleaving is enabled)
365 popts->memctl_interleaving_mode = 0;
368 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
369 * 1: page: bit to the left of the column bits selects the memctl
370 * 2: bank: bit to the left of the bank bits selects the memctl
371 * 3: superbank: bit to the left of the chip select selects the memctl
373 * NOTE: ba_intlv (rank interleaving) is independent of memory
374 * controller interleaving; it is only within a memory controller.
375 * Must use superbank interleaving if rank interleaving is used and
376 * memory controller interleaving is enabled.
383 * 0x60 = CS0,CS1 + CS2,CS3
384 * 0x04 = CS0,CS1,CS2,CS3
386 popts->ba_intlv_ctl = 0;
388 /* Memory Organization Parameters */
389 popts->registered_dimm_en = all_DIMMs_registered;
391 /* Operational Mode Paramters */
394 popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
395 #ifdef CONFIG_DDR_ECC
396 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
397 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
402 popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
409 #if defined(CONFIG_FSL_DDR1)
410 popts->DQS_config = 0;
411 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
412 popts->DQS_config = 1;
415 /* Choose self-refresh during sleep. */
416 popts->self_refresh_in_sleep = 1;
418 /* Choose dynamic power management mode. */
419 popts->dynamic_power = 0;
422 * check first dimm for primary sdram width
423 * presuming all dimms are similar
424 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
426 #if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
427 if (pdimm[0].n_ranks != 0) {
428 if ((pdimm[0].data_width >= 64) && \
429 (pdimm[0].data_width <= 72))
430 popts->data_bus_width = 0;
431 else if ((pdimm[0].data_width >= 32) || \
432 (pdimm[0].data_width <= 40))
433 popts->data_bus_width = 1;
435 panic("Error: data width %u is invalid!\n",
436 pdimm[0].data_width);
440 if (pdimm[0].n_ranks != 0) {
441 if (pdimm[0].primary_sdram_width == 64)
442 popts->data_bus_width = 0;
443 else if (pdimm[0].primary_sdram_width == 32)
444 popts->data_bus_width = 1;
445 else if (pdimm[0].primary_sdram_width == 16)
446 popts->data_bus_width = 2;
448 panic("Error: primary sdram width %u is invalid!\n",
449 pdimm[0].primary_sdram_width);
454 /* Choose burst length. */
455 #if defined(CONFIG_FSL_DDR3)
456 #if defined(CONFIG_E500MC)
457 popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
458 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
460 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
461 /* 32-bit or 16-bit bus */
462 popts->OTF_burst_chop_en = 0;
463 popts->burst_length = DDR_BL8;
465 popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
466 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
470 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
473 /* Choose ddr controller address mirror mode */
474 #if defined(CONFIG_FSL_DDR3)
475 popts->mirrored_dimm = pdimm[0].mirrored_dimm;
478 /* Global Timing Parameters. */
479 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
481 /* Pick a caslat override. */
482 popts->cas_latency_override = 0;
483 popts->cas_latency_override_value = 3;
484 if (popts->cas_latency_override) {
485 debug("using caslat override value = %u\n",
486 popts->cas_latency_override_value);
489 /* Decide whether to use the computed derated latency */
490 popts->use_derated_caslat = 0;
492 /* Choose an additive latency. */
493 popts->additive_latency_override = 0;
494 popts->additive_latency_override_value = 3;
495 if (popts->additive_latency_override) {
496 debug("using additive latency override value = %u\n",
497 popts->additive_latency_override_value);
503 * Factors to consider for 2T_EN:
504 * - number of DIMMs installed
505 * - number of components, number of active ranks
506 * - how much time you want to spend playing around
509 popts->threeT_en = 0;
511 /* for RDIMM, address parity enable */
515 * BSTTOPRE precharge interval
517 * Set this to 0 for global auto precharge
519 * FIXME: Should this be configured in picoseconds?
520 * Why it should be in ps: better understanding of this
521 * relative to actual DRAM timing parameters such as tRAS.
522 * e.g. tRAS(min) = 40 ns
524 popts->bstopre = 0x100;
526 /* Minimum CKE pulse width -- tCKE(MIN) */
527 popts->tCKE_clock_pulse_width_ps
528 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
531 * Window for four activates -- tFAW
533 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
534 * FIXME: varies depending upon number of column addresses or data
535 * FIXME: width, was considering looking at pdimm->primary_sdram_width
537 #if defined(CONFIG_FSL_DDR1)
538 popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
540 #elif defined(CONFIG_FSL_DDR2)
542 * x4/x8; some datasheets have 35000
543 * x16 wide columns only? Use 50000?
545 popts->tFAW_window_four_activates_ps = 37500;
547 #elif defined(CONFIG_FSL_DDR3)
548 popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
552 #if defined(CONFIG_FSL_DDR3)
554 * due to ddr3 dimm is fly-by topology
555 * we suggest to enable write leveling to
556 * meet the tQDSS under different loading.
560 popts->wrlvl_override = 0;
564 * Check interleaving configuration from environment.
565 * Please refer to doc/README.fsl-ddr for the detail.
567 * If memory controller interleaving is enabled, then the data
568 * bus widths must be programmed identically for all memory controllers.
570 * XXX: Attempt to set all controllers to the same chip select
571 * interleaving mode. It will do a best effort to get the
572 * requested ranks interleaved together such that the result
573 * should be a subset of the requested configuration.
575 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
576 if (hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) {
577 if (pdimm[0].n_ranks == 0) {
578 printf("There is no rank on CS0 for controller %d. Because only"
579 " rank on CS0 and ranks chip-select interleaved with CS0"
580 " are controller interleaved, force non memory "
581 "controller interleaving\n", ctrl_num);
582 popts->memctl_interleaving = 0;
584 popts->memctl_interleaving = 1;
586 * test null first. if CONFIG_HWCONFIG is not defined
587 * hwconfig_arg_cmp returns non-zero
589 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
591 popts->memctl_interleaving = 0;
592 debug("memory controller interleaving disabled.\n");
593 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
596 popts->memctl_interleaving_mode =
597 FSL_DDR_CACHE_LINE_INTERLEAVING;
598 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
600 popts->memctl_interleaving_mode =
601 FSL_DDR_PAGE_INTERLEAVING;
602 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
604 popts->memctl_interleaving_mode =
605 FSL_DDR_BANK_INTERLEAVING;
606 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
608 popts->memctl_interleaving_mode =
609 FSL_DDR_SUPERBANK_INTERLEAVING;
611 popts->memctl_interleaving = 0;
612 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
617 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
618 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
619 /* test null first. if CONFIG_HWCONFIG is not defined,
620 * hwconfig_subarg_cmp_f returns non-zero */
621 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
623 debug("bank interleaving disabled.\n");
624 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
626 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
627 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
629 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
630 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
631 "cs0_cs1_and_cs2_cs3", buf))
632 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
633 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
634 "cs0_cs1_cs2_cs3", buf))
635 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
637 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
638 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
639 case FSL_DDR_CS0_CS1_CS2_CS3:
640 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
641 if (pdimm[0].n_ranks < 4) {
642 popts->ba_intlv_ctl = 0;
643 printf("Not enough bank(chip-select) for "
644 "CS0+CS1+CS2+CS3 on controller %d, "
645 "force non-interleaving!\n", ctrl_num);
647 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
648 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
649 popts->ba_intlv_ctl = 0;
650 printf("Not enough bank(chip-select) for "
651 "CS0+CS1+CS2+CS3 on controller %d, "
652 "force non-interleaving!\n", ctrl_num);
654 if (pdimm[0].capacity != pdimm[1].capacity) {
655 popts->ba_intlv_ctl = 0;
656 printf("Not identical DIMM size for "
657 "CS0+CS1+CS2+CS3 on controller %d, "
658 "force non-interleaving!\n", ctrl_num);
662 case FSL_DDR_CS0_CS1:
663 if (pdimm[0].n_ranks < 2) {
664 popts->ba_intlv_ctl = 0;
665 printf("Not enough bank(chip-select) for "
666 "CS0+CS1 on controller %d, "
667 "force non-interleaving!\n", ctrl_num);
670 case FSL_DDR_CS2_CS3:
671 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
672 if (pdimm[0].n_ranks < 4) {
673 popts->ba_intlv_ctl = 0;
674 printf("Not enough bank(chip-select) for CS2+CS3 "
675 "on controller %d, force non-interleaving!\n", ctrl_num);
677 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
678 if (pdimm[1].n_ranks < 2) {
679 popts->ba_intlv_ctl = 0;
680 printf("Not enough bank(chip-select) for CS2+CS3 "
681 "on controller %d, force non-interleaving!\n", ctrl_num);
685 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
686 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
687 if (pdimm[0].n_ranks < 4) {
688 popts->ba_intlv_ctl = 0;
689 printf("Not enough bank(CS) for CS0+CS1 and "
690 "CS2+CS3 on controller %d, "
691 "force non-interleaving!\n", ctrl_num);
693 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
694 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
695 popts->ba_intlv_ctl = 0;
696 printf("Not enough bank(CS) for CS0+CS1 and "
697 "CS2+CS3 on controller %d, "
698 "force non-interleaving!\n", ctrl_num);
703 popts->ba_intlv_ctl = 0;
708 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
709 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
710 popts->addr_hash = 0;
711 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
713 popts->addr_hash = 1;
716 if (pdimm[0].n_ranks == 4)
717 popts->quad_rank_present = 1;
719 fsl_ddr_board_options(popts, pdimm, ctrl_num);
724 void check_interleaving_options(fsl_ddr_info_t *pinfo)
726 int i, j, check_n_ranks, intlv_fixed = 0;
727 unsigned long long check_rank_density;
729 * Check if all controllers are configured for memory
730 * controller interleaving. Identical dimms are recommended. At least
731 * the size should be checked.
734 check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
735 check_rank_density = pinfo->dimm_params[0][0].rank_density;
736 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
737 if ((pinfo->memctl_opts[i].memctl_interleaving) && \
738 (check_rank_density == pinfo->dimm_params[i][0].rank_density) && \
739 (check_n_ranks == pinfo->dimm_params[i][0].n_ranks)) {
743 if (j != CONFIG_NUM_DDR_CONTROLLERS) {
744 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
745 if (pinfo->memctl_opts[i].memctl_interleaving) {
746 pinfo->memctl_opts[i].memctl_interleaving = 0;
750 printf("Not all DIMMs are identical in size. "
751 "Memory controller interleaving disabled.\n");
755 int fsl_use_spd(void)
759 #ifdef CONFIG_DDR_SPD
760 char buffer[HWCONFIG_BUFFER_SIZE];
764 * Extract hwconfig from environment since we have not properly setup
765 * the environment but need it for ddr config params
767 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
770 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
771 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
772 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
774 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",