2 * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
12 #include <asm/fsl_ddr_sdram.h>
17 * Use our own stack based buffer before relocation to allow accessing longer
18 * hwconfig strings that might be in the environment before we've relocated.
19 * This is pretty fragile on both the use of stack and if the buffer is big
20 * enough. However we will get a warning from getenv_f for the later.
22 #define HWCONFIG_BUFFER_SIZE 128
24 /* Board-specific functions defined in each board's ddr.c */
25 extern void fsl_ddr_board_options(memctl_options_t *popts,
27 unsigned int ctrl_num);
30 unsigned int odt_rd_cfg;
31 unsigned int odt_wr_cfg;
32 unsigned int odt_rtt_norm;
33 unsigned int odt_rtt_wr;
36 #ifdef CONFIG_FSL_DDR3
37 static const struct dynamic_odt single_Q[4] = {
40 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
46 FSL_DDR_ODT_NEVER, /* tied high */
52 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
58 FSL_DDR_ODT_NEVER, /* tied high */
64 static const struct dynamic_odt single_D[4] = {
81 static const struct dynamic_odt single_S[4] = {
93 static const struct dynamic_odt dual_DD[4] = {
96 FSL_DDR_ODT_SAME_DIMM,
101 FSL_DDR_ODT_OTHER_DIMM,
102 FSL_DDR_ODT_OTHER_DIMM,
108 FSL_DDR_ODT_SAME_DIMM,
113 FSL_DDR_ODT_OTHER_DIMM,
114 FSL_DDR_ODT_OTHER_DIMM,
120 static const struct dynamic_odt dual_DS[4] = {
123 FSL_DDR_ODT_SAME_DIMM,
128 FSL_DDR_ODT_OTHER_DIMM,
129 FSL_DDR_ODT_OTHER_DIMM,
134 FSL_DDR_ODT_OTHER_DIMM,
141 static const struct dynamic_odt dual_SD[4] = {
143 FSL_DDR_ODT_OTHER_DIMM,
151 FSL_DDR_ODT_SAME_DIMM,
156 FSL_DDR_ODT_OTHER_DIMM,
157 FSL_DDR_ODT_OTHER_DIMM,
163 static const struct dynamic_odt dual_SS[4] = {
165 FSL_DDR_ODT_OTHER_DIMM,
172 FSL_DDR_ODT_OTHER_DIMM,
180 static const struct dynamic_odt dual_D0[4] = {
183 FSL_DDR_ODT_SAME_DIMM,
197 static const struct dynamic_odt dual_0D[4] = {
202 FSL_DDR_ODT_SAME_DIMM,
214 static const struct dynamic_odt dual_S0[4] = {
227 static const struct dynamic_odt dual_0S[4] = {
240 static const struct dynamic_odt odt_unknown[4] = {
266 #else /* CONFIG_FSL_DDR3 */
267 static const struct dynamic_odt single_Q[4] = {
274 static const struct dynamic_odt single_D[4] = {
291 static const struct dynamic_odt single_S[4] = {
303 static const struct dynamic_odt dual_DD[4] = {
305 FSL_DDR_ODT_OTHER_DIMM,
306 FSL_DDR_ODT_OTHER_DIMM,
317 FSL_DDR_ODT_OTHER_DIMM,
318 FSL_DDR_ODT_OTHER_DIMM,
330 static const struct dynamic_odt dual_DS[4] = {
332 FSL_DDR_ODT_OTHER_DIMM,
333 FSL_DDR_ODT_OTHER_DIMM,
344 FSL_DDR_ODT_OTHER_DIMM,
345 FSL_DDR_ODT_OTHER_DIMM,
352 static const struct dynamic_odt dual_SD[4] = {
354 FSL_DDR_ODT_OTHER_DIMM,
355 FSL_DDR_ODT_OTHER_DIMM,
361 FSL_DDR_ODT_OTHER_DIMM,
362 FSL_DDR_ODT_OTHER_DIMM,
374 static const struct dynamic_odt dual_SS[4] = {
376 FSL_DDR_ODT_OTHER_DIMM,
377 FSL_DDR_ODT_OTHER_DIMM,
383 FSL_DDR_ODT_OTHER_DIMM,
384 FSL_DDR_ODT_OTHER_DIMM,
391 static const struct dynamic_odt dual_D0[4] = {
408 static const struct dynamic_odt dual_0D[4] = {
425 static const struct dynamic_odt dual_S0[4] = {
438 static const struct dynamic_odt dual_0S[4] = {
451 static const struct dynamic_odt odt_unknown[4] = {
478 unsigned int populate_memctl_options(int all_DIMMs_registered,
479 memctl_options_t *popts,
480 dimm_params_t *pdimm,
481 unsigned int ctrl_num)
484 char buffer[HWCONFIG_BUFFER_SIZE];
486 const struct dynamic_odt *pdodt = odt_unknown;
490 * Extract hwconfig from environment since we have not properly setup
491 * the environment but need it for ddr config params
493 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
496 /* Chip select options. */
497 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
498 switch (pdimm[0].n_ranks) {
509 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
510 switch (pdimm[0].n_ranks) {
512 switch (pdimm[1].n_ranks) {
525 switch (pdimm[1].n_ranks) {
538 switch (pdimm[1].n_ranks) {
550 /* Pick chip-select local options. */
551 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
552 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
553 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
554 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
555 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
556 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
558 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
559 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
561 popts->cs_local_opts[i].auto_precharge = 0;
564 /* Pick interleaving mode. */
567 * 0 = no interleaving
568 * 1 = interleaving between 2 controllers
570 popts->memctl_interleaving = 0;
576 * 3 = superbank (only if CS interleaving is enabled)
578 popts->memctl_interleaving_mode = 0;
581 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
582 * 1: page: bit to the left of the column bits selects the memctl
583 * 2: bank: bit to the left of the bank bits selects the memctl
584 * 3: superbank: bit to the left of the chip select selects the memctl
586 * NOTE: ba_intlv (rank interleaving) is independent of memory
587 * controller interleaving; it is only within a memory controller.
588 * Must use superbank interleaving if rank interleaving is used and
589 * memory controller interleaving is enabled.
596 * 0x60 = CS0,CS1 + CS2,CS3
597 * 0x04 = CS0,CS1,CS2,CS3
599 popts->ba_intlv_ctl = 0;
601 /* Memory Organization Parameters */
602 popts->registered_dimm_en = all_DIMMs_registered;
604 /* Operational Mode Paramters */
607 popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
608 #ifdef CONFIG_DDR_ECC
609 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
610 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
615 popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
622 #if defined(CONFIG_FSL_DDR1)
623 popts->DQS_config = 0;
624 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
625 popts->DQS_config = 1;
628 /* Choose self-refresh during sleep. */
629 popts->self_refresh_in_sleep = 1;
631 /* Choose dynamic power management mode. */
632 popts->dynamic_power = 0;
635 * check first dimm for primary sdram width
636 * presuming all dimms are similar
637 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
639 #if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
640 if (pdimm[0].n_ranks != 0) {
641 if ((pdimm[0].data_width >= 64) && \
642 (pdimm[0].data_width <= 72))
643 popts->data_bus_width = 0;
644 else if ((pdimm[0].data_width >= 32) || \
645 (pdimm[0].data_width <= 40))
646 popts->data_bus_width = 1;
648 panic("Error: data width %u is invalid!\n",
649 pdimm[0].data_width);
653 if (pdimm[0].n_ranks != 0) {
654 if (pdimm[0].primary_sdram_width == 64)
655 popts->data_bus_width = 0;
656 else if (pdimm[0].primary_sdram_width == 32)
657 popts->data_bus_width = 1;
658 else if (pdimm[0].primary_sdram_width == 16)
659 popts->data_bus_width = 2;
661 panic("Error: primary sdram width %u is invalid!\n",
662 pdimm[0].primary_sdram_width);
667 /* Choose burst length. */
668 #if defined(CONFIG_FSL_DDR3)
669 #if defined(CONFIG_E500MC)
670 popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
671 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
673 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
674 /* 32-bit or 16-bit bus */
675 popts->OTF_burst_chop_en = 0;
676 popts->burst_length = DDR_BL8;
678 popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
679 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
683 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
686 /* Choose ddr controller address mirror mode */
687 #if defined(CONFIG_FSL_DDR3)
688 popts->mirrored_dimm = pdimm[0].mirrored_dimm;
691 /* Global Timing Parameters. */
692 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
694 /* Pick a caslat override. */
695 popts->cas_latency_override = 0;
696 popts->cas_latency_override_value = 3;
697 if (popts->cas_latency_override) {
698 debug("using caslat override value = %u\n",
699 popts->cas_latency_override_value);
702 /* Decide whether to use the computed derated latency */
703 popts->use_derated_caslat = 0;
705 /* Choose an additive latency. */
706 popts->additive_latency_override = 0;
707 popts->additive_latency_override_value = 3;
708 if (popts->additive_latency_override) {
709 debug("using additive latency override value = %u\n",
710 popts->additive_latency_override_value);
716 * Factors to consider for 2T_EN:
717 * - number of DIMMs installed
718 * - number of components, number of active ranks
719 * - how much time you want to spend playing around
722 popts->threeT_en = 0;
724 /* for RDIMM, address parity enable */
728 * BSTTOPRE precharge interval
730 * Set this to 0 for global auto precharge
732 * FIXME: Should this be configured in picoseconds?
733 * Why it should be in ps: better understanding of this
734 * relative to actual DRAM timing parameters such as tRAS.
735 * e.g. tRAS(min) = 40 ns
737 popts->bstopre = 0x100;
739 /* Minimum CKE pulse width -- tCKE(MIN) */
740 popts->tCKE_clock_pulse_width_ps
741 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
744 * Window for four activates -- tFAW
746 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
747 * FIXME: varies depending upon number of column addresses or data
748 * FIXME: width, was considering looking at pdimm->primary_sdram_width
750 #if defined(CONFIG_FSL_DDR1)
751 popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
753 #elif defined(CONFIG_FSL_DDR2)
755 * x4/x8; some datasheets have 35000
756 * x16 wide columns only? Use 50000?
758 popts->tFAW_window_four_activates_ps = 37500;
760 #elif defined(CONFIG_FSL_DDR3)
761 popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
765 #if defined(CONFIG_FSL_DDR3)
767 * due to ddr3 dimm is fly-by topology
768 * we suggest to enable write leveling to
769 * meet the tQDSS under different loading.
773 popts->wrlvl_override = 0;
777 * Check interleaving configuration from environment.
778 * Please refer to doc/README.fsl-ddr for the detail.
780 * If memory controller interleaving is enabled, then the data
781 * bus widths must be programmed identically for all memory controllers.
783 * XXX: Attempt to set all controllers to the same chip select
784 * interleaving mode. It will do a best effort to get the
785 * requested ranks interleaved together such that the result
786 * should be a subset of the requested configuration.
788 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
789 if (hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) {
790 if (pdimm[0].n_ranks == 0) {
791 printf("There is no rank on CS0 for controller %d. Because only"
792 " rank on CS0 and ranks chip-select interleaved with CS0"
793 " are controller interleaved, force non memory "
794 "controller interleaving\n", ctrl_num);
795 popts->memctl_interleaving = 0;
797 popts->memctl_interleaving = 1;
799 * test null first. if CONFIG_HWCONFIG is not defined
800 * hwconfig_arg_cmp returns non-zero
802 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
804 popts->memctl_interleaving = 0;
805 debug("memory controller interleaving disabled.\n");
806 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
809 popts->memctl_interleaving_mode =
810 FSL_DDR_CACHE_LINE_INTERLEAVING;
811 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
813 popts->memctl_interleaving_mode =
814 FSL_DDR_PAGE_INTERLEAVING;
815 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
817 popts->memctl_interleaving_mode =
818 FSL_DDR_BANK_INTERLEAVING;
819 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
821 popts->memctl_interleaving_mode =
822 FSL_DDR_SUPERBANK_INTERLEAVING;
824 popts->memctl_interleaving = 0;
825 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
830 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
831 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
832 /* test null first. if CONFIG_HWCONFIG is not defined,
833 * hwconfig_subarg_cmp_f returns non-zero */
834 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
836 debug("bank interleaving disabled.\n");
837 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
839 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
840 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
842 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
843 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
844 "cs0_cs1_and_cs2_cs3", buf))
845 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
846 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
847 "cs0_cs1_cs2_cs3", buf))
848 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
850 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
851 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
852 case FSL_DDR_CS0_CS1_CS2_CS3:
853 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
854 if (pdimm[0].n_ranks < 4) {
855 popts->ba_intlv_ctl = 0;
856 printf("Not enough bank(chip-select) for "
857 "CS0+CS1+CS2+CS3 on controller %d, "
858 "force non-interleaving!\n", ctrl_num);
860 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
861 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
862 popts->ba_intlv_ctl = 0;
863 printf("Not enough bank(chip-select) for "
864 "CS0+CS1+CS2+CS3 on controller %d, "
865 "force non-interleaving!\n", ctrl_num);
867 if (pdimm[0].capacity != pdimm[1].capacity) {
868 popts->ba_intlv_ctl = 0;
869 printf("Not identical DIMM size for "
870 "CS0+CS1+CS2+CS3 on controller %d, "
871 "force non-interleaving!\n", ctrl_num);
875 case FSL_DDR_CS0_CS1:
876 if (pdimm[0].n_ranks < 2) {
877 popts->ba_intlv_ctl = 0;
878 printf("Not enough bank(chip-select) for "
879 "CS0+CS1 on controller %d, "
880 "force non-interleaving!\n", ctrl_num);
883 case FSL_DDR_CS2_CS3:
884 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
885 if (pdimm[0].n_ranks < 4) {
886 popts->ba_intlv_ctl = 0;
887 printf("Not enough bank(chip-select) for CS2+CS3 "
888 "on controller %d, force non-interleaving!\n", ctrl_num);
890 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
891 if (pdimm[1].n_ranks < 2) {
892 popts->ba_intlv_ctl = 0;
893 printf("Not enough bank(chip-select) for CS2+CS3 "
894 "on controller %d, force non-interleaving!\n", ctrl_num);
898 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
899 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
900 if (pdimm[0].n_ranks < 4) {
901 popts->ba_intlv_ctl = 0;
902 printf("Not enough bank(CS) for CS0+CS1 and "
903 "CS2+CS3 on controller %d, "
904 "force non-interleaving!\n", ctrl_num);
906 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
907 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
908 popts->ba_intlv_ctl = 0;
909 printf("Not enough bank(CS) for CS0+CS1 and "
910 "CS2+CS3 on controller %d, "
911 "force non-interleaving!\n", ctrl_num);
916 popts->ba_intlv_ctl = 0;
921 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
922 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
923 popts->addr_hash = 0;
924 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
926 popts->addr_hash = 1;
929 if (pdimm[0].n_ranks == 4)
930 popts->quad_rank_present = 1;
932 ddr_freq = get_ddr_freq(0) / 1000000;
933 if (popts->registered_dimm_en) {
934 popts->rcw_override = 1;
935 popts->rcw_1 = 0x000a5a00;
937 popts->rcw_2 = 0x00000000;
938 else if (ddr_freq <= 1066)
939 popts->rcw_2 = 0x00100000;
940 else if (ddr_freq <= 1333)
941 popts->rcw_2 = 0x00200000;
943 popts->rcw_2 = 0x00300000;
946 fsl_ddr_board_options(popts, pdimm, ctrl_num);
951 void check_interleaving_options(fsl_ddr_info_t *pinfo)
953 int i, j, check_n_ranks, intlv_fixed = 0;
954 unsigned long long check_rank_density;
956 * Check if all controllers are configured for memory
957 * controller interleaving. Identical dimms are recommended. At least
958 * the size should be checked.
961 check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
962 check_rank_density = pinfo->dimm_params[0][0].rank_density;
963 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
964 if ((pinfo->memctl_opts[i].memctl_interleaving) && \
965 (check_rank_density == pinfo->dimm_params[i][0].rank_density) && \
966 (check_n_ranks == pinfo->dimm_params[i][0].n_ranks)) {
970 if (j != CONFIG_NUM_DDR_CONTROLLERS) {
971 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
972 if (pinfo->memctl_opts[i].memctl_interleaving) {
973 pinfo->memctl_opts[i].memctl_interleaving = 0;
977 printf("Not all DIMMs are identical in size. "
978 "Memory controller interleaving disabled.\n");
982 int fsl_use_spd(void)
986 #ifdef CONFIG_DDR_SPD
987 char buffer[HWCONFIG_BUFFER_SIZE];
991 * Extract hwconfig from environment since we have not properly setup
992 * the environment but need it for ddr config params
994 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
997 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
998 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
999 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1001 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",