2 * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
12 #include <asm/fsl_ddr_sdram.h>
17 * Use our own stack based buffer before relocation to allow accessing longer
18 * hwconfig strings that might be in the environment before we've relocated.
19 * This is pretty fragile on both the use of stack and if the buffer is big
20 * enough. However we will get a warning from getenv_f for the later.
22 #define HWCONFIG_BUFFER_SIZE 128
24 /* Board-specific functions defined in each board's ddr.c */
25 extern void fsl_ddr_board_options(memctl_options_t *popts,
27 unsigned int ctrl_num);
30 unsigned int odt_rd_cfg;
31 unsigned int odt_wr_cfg;
32 unsigned int odt_rtt_norm;
33 unsigned int odt_rtt_wr;
36 static const dynamic_odt_t single_Q[4] = {
39 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
45 FSL_DDR_ODT_NEVER, /* tied high */
51 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
57 FSL_DDR_ODT_NEVER, /* tied high */
63 static const dynamic_odt_t single_D[4] = {
80 static const dynamic_odt_t single_S[4] = {
92 static const dynamic_odt_t dual_DD[4] = {
95 FSL_DDR_ODT_SAME_DIMM,
100 FSL_DDR_ODT_OTHER_DIMM,
101 FSL_DDR_ODT_OTHER_DIMM,
107 FSL_DDR_ODT_SAME_DIMM,
112 FSL_DDR_ODT_OTHER_DIMM,
113 FSL_DDR_ODT_OTHER_DIMM,
119 static const dynamic_odt_t dual_DS[4] = {
122 FSL_DDR_ODT_SAME_DIMM,
127 FSL_DDR_ODT_OTHER_DIMM,
128 FSL_DDR_ODT_OTHER_DIMM,
133 FSL_DDR_ODT_OTHER_DIMM,
140 static const dynamic_odt_t dual_SD[4] = {
142 FSL_DDR_ODT_OTHER_DIMM,
150 FSL_DDR_ODT_SAME_DIMM,
155 FSL_DDR_ODT_OTHER_DIMM,
156 FSL_DDR_ODT_OTHER_DIMM,
162 static const dynamic_odt_t dual_SS[4] = {
164 FSL_DDR_ODT_OTHER_DIMM,
171 FSL_DDR_ODT_OTHER_DIMM,
179 static const dynamic_odt_t dual_D0[4] = {
182 FSL_DDR_ODT_SAME_DIMM,
196 static const dynamic_odt_t dual_0D[4] = {
201 FSL_DDR_ODT_SAME_DIMM,
213 static const dynamic_odt_t dual_S0[4] = {
226 static const dynamic_odt_t dual_0S[4] = {
239 static const dynamic_odt_t odt_unknown[4] = {
266 unsigned int populate_memctl_options(int all_DIMMs_registered,
267 memctl_options_t *popts,
268 dimm_params_t *pdimm,
269 unsigned int ctrl_num)
272 char buffer[HWCONFIG_BUFFER_SIZE];
274 const dynamic_odt_t *pdodt = odt_unknown;
277 * Extract hwconfig from environment since we have not properly setup
278 * the environment but need it for ddr config params
280 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
283 /* Chip select options. */
284 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
285 switch (pdimm[0].n_ranks) {
296 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
297 switch (pdimm[0].n_ranks) {
299 switch (pdimm[1].n_ranks) {
312 switch (pdimm[1].n_ranks) {
325 switch (pdimm[1].n_ranks) {
337 /* Pick chip-select local options. */
338 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
339 #if defined(CONFIG_FSL_DDR3)
340 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
341 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
342 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
343 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
345 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
346 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
348 popts->cs_local_opts[i].auto_precharge = 0;
351 /* Pick interleaving mode. */
354 * 0 = no interleaving
355 * 1 = interleaving between 2 controllers
357 popts->memctl_interleaving = 0;
363 * 3 = superbank (only if CS interleaving is enabled)
365 popts->memctl_interleaving_mode = 0;
368 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
369 * 1: page: bit to the left of the column bits selects the memctl
370 * 2: bank: bit to the left of the bank bits selects the memctl
371 * 3: superbank: bit to the left of the chip select selects the memctl
373 * NOTE: ba_intlv (rank interleaving) is independent of memory
374 * controller interleaving; it is only within a memory controller.
375 * Must use superbank interleaving if rank interleaving is used and
376 * memory controller interleaving is enabled.
383 * 0x60 = CS0,CS1 + CS2,CS3
384 * 0x04 = CS0,CS1,CS2,CS3
386 popts->ba_intlv_ctl = 0;
388 /* Memory Organization Parameters */
389 popts->registered_dimm_en = all_DIMMs_registered;
391 /* Operational Mode Paramters */
394 popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
395 #ifdef CONFIG_DDR_ECC
396 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
397 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
402 popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
409 #if defined(CONFIG_FSL_DDR1)
410 popts->DQS_config = 0;
411 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
412 popts->DQS_config = 1;
415 /* Choose self-refresh during sleep. */
416 popts->self_refresh_in_sleep = 1;
418 /* Choose dynamic power management mode. */
419 popts->dynamic_power = 0;
422 * check first dimm for primary sdram width
423 * presuming all dimms are similar
424 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
426 if (pdimm[0].primary_sdram_width == 64)
427 popts->data_bus_width = 0;
428 else if (pdimm[0].primary_sdram_width == 32)
429 popts->data_bus_width = 1;
430 else if (pdimm[0].primary_sdram_width == 16)
431 popts->data_bus_width = 2;
433 panic("Error: invalid primary sdram width!\n");
435 /* Choose burst length. */
436 #if defined(CONFIG_FSL_DDR3)
437 #if defined(CONFIG_E500MC)
438 popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
439 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
441 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
442 /* 32-bit or 16-bit bus */
443 popts->OTF_burst_chop_en = 0;
444 popts->burst_length = DDR_BL8;
446 popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
447 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
451 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
454 /* Choose ddr controller address mirror mode */
455 #if defined(CONFIG_FSL_DDR3)
456 popts->mirrored_dimm = pdimm[0].mirrored_dimm;
459 /* Global Timing Parameters. */
460 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
462 /* Pick a caslat override. */
463 popts->cas_latency_override = 0;
464 popts->cas_latency_override_value = 3;
465 if (popts->cas_latency_override) {
466 debug("using caslat override value = %u\n",
467 popts->cas_latency_override_value);
470 /* Decide whether to use the computed derated latency */
471 popts->use_derated_caslat = 0;
473 /* Choose an additive latency. */
474 popts->additive_latency_override = 0;
475 popts->additive_latency_override_value = 3;
476 if (popts->additive_latency_override) {
477 debug("using additive latency override value = %u\n",
478 popts->additive_latency_override_value);
484 * Factors to consider for 2T_EN:
485 * - number of DIMMs installed
486 * - number of components, number of active ranks
487 * - how much time you want to spend playing around
490 popts->threeT_en = 0;
492 /* for RDIMM, address parity enable */
496 * BSTTOPRE precharge interval
498 * Set this to 0 for global auto precharge
500 * FIXME: Should this be configured in picoseconds?
501 * Why it should be in ps: better understanding of this
502 * relative to actual DRAM timing parameters such as tRAS.
503 * e.g. tRAS(min) = 40 ns
505 popts->bstopre = 0x100;
507 /* Minimum CKE pulse width -- tCKE(MIN) */
508 popts->tCKE_clock_pulse_width_ps
509 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
512 * Window for four activates -- tFAW
514 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
515 * FIXME: varies depending upon number of column addresses or data
516 * FIXME: width, was considering looking at pdimm->primary_sdram_width
518 #if defined(CONFIG_FSL_DDR1)
519 popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
521 #elif defined(CONFIG_FSL_DDR2)
523 * x4/x8; some datasheets have 35000
524 * x16 wide columns only? Use 50000?
526 popts->tFAW_window_four_activates_ps = 37500;
528 #elif defined(CONFIG_FSL_DDR3)
529 popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
533 #if defined(CONFIG_FSL_DDR3)
535 * due to ddr3 dimm is fly-by topology
536 * we suggest to enable write leveling to
537 * meet the tQDSS under different loading.
541 popts->wrlvl_override = 0;
545 * Check interleaving configuration from environment.
546 * Please refer to doc/README.fsl-ddr for the detail.
548 * If memory controller interleaving is enabled, then the data
549 * bus widths must be programmed identically for all memory controllers.
551 * XXX: Attempt to set all controllers to the same chip select
552 * interleaving mode. It will do a best effort to get the
553 * requested ranks interleaved together such that the result
554 * should be a subset of the requested configuration.
556 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
557 if (hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) {
558 if (pdimm[0].n_ranks == 0) {
559 printf("There is no rank on CS0 for controller %d. Because only"
560 " rank on CS0 and ranks chip-select interleaved with CS0"
561 " are controller interleaved, force non memory "
562 "controller interleaving\n", ctrl_num);
563 popts->memctl_interleaving = 0;
565 popts->memctl_interleaving = 1;
567 * test null first. if CONFIG_HWCONFIG is not defined
568 * hwconfig_arg_cmp returns non-zero
570 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
572 popts->memctl_interleaving = 0;
573 debug("memory controller interleaving disabled.\n");
574 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
577 popts->memctl_interleaving_mode =
578 FSL_DDR_CACHE_LINE_INTERLEAVING;
579 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
581 popts->memctl_interleaving_mode =
582 FSL_DDR_PAGE_INTERLEAVING;
583 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
585 popts->memctl_interleaving_mode =
586 FSL_DDR_BANK_INTERLEAVING;
587 else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
589 popts->memctl_interleaving_mode =
590 FSL_DDR_SUPERBANK_INTERLEAVING;
592 popts->memctl_interleaving = 0;
593 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
598 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
599 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
600 /* test null first. if CONFIG_HWCONFIG is not defined,
601 * hwconfig_subarg_cmp_f returns non-zero */
602 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
604 debug("bank interleaving disabled.\n");
605 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
607 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
608 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
610 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
611 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
612 "cs0_cs1_and_cs2_cs3", buf))
613 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
614 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
615 "cs0_cs1_cs2_cs3", buf))
616 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
618 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
619 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
620 case FSL_DDR_CS0_CS1_CS2_CS3:
621 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
622 if (pdimm[0].n_ranks < 4) {
623 popts->ba_intlv_ctl = 0;
624 printf("Not enough bank(chip-select) for "
625 "CS0+CS1+CS2+CS3 on controller %d, "
626 "force non-interleaving!\n", ctrl_num);
628 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
629 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
630 popts->ba_intlv_ctl = 0;
631 printf("Not enough bank(chip-select) for "
632 "CS0+CS1+CS2+CS3 on controller %d, "
633 "force non-interleaving!\n", ctrl_num);
635 if (pdimm[0].capacity != pdimm[1].capacity) {
636 popts->ba_intlv_ctl = 0;
637 printf("Not identical DIMM size for "
638 "CS0+CS1+CS2+CS3 on controller %d, "
639 "force non-interleaving!\n", ctrl_num);
643 case FSL_DDR_CS0_CS1:
644 if (pdimm[0].n_ranks < 2) {
645 popts->ba_intlv_ctl = 0;
646 printf("Not enough bank(chip-select) for "
647 "CS0+CS1 on controller %d, "
648 "force non-interleaving!\n", ctrl_num);
651 case FSL_DDR_CS2_CS3:
652 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
653 if (pdimm[0].n_ranks < 4) {
654 popts->ba_intlv_ctl = 0;
655 printf("Not enough bank(chip-select) for CS2+CS3 "
656 "on controller %d, force non-interleaving!\n", ctrl_num);
658 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
659 if (pdimm[1].n_ranks < 2) {
660 popts->ba_intlv_ctl = 0;
661 printf("Not enough bank(chip-select) for CS2+CS3 "
662 "on controller %d, force non-interleaving!\n", ctrl_num);
666 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
667 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
668 if (pdimm[0].n_ranks < 4) {
669 popts->ba_intlv_ctl = 0;
670 printf("Not enough bank(CS) for CS0+CS1 and "
671 "CS2+CS3 on controller %d, "
672 "force non-interleaving!\n", ctrl_num);
674 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
675 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
676 popts->ba_intlv_ctl = 0;
677 printf("Not enough bank(CS) for CS0+CS1 and "
678 "CS2+CS3 on controller %d, "
679 "force non-interleaving!\n", ctrl_num);
684 popts->ba_intlv_ctl = 0;
689 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
690 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
691 popts->addr_hash = 0;
692 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
694 popts->addr_hash = 1;
697 if (pdimm[0].n_ranks == 4)
698 popts->quad_rank_present = 1;
700 fsl_ddr_board_options(popts, pdimm, ctrl_num);
705 void check_interleaving_options(fsl_ddr_info_t *pinfo)
707 int i, j, check_n_ranks, intlv_fixed = 0;
708 unsigned long long check_rank_density;
710 * Check if all controllers are configured for memory
711 * controller interleaving. Identical dimms are recommended. At least
712 * the size should be checked.
715 check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
716 check_rank_density = pinfo->dimm_params[0][0].rank_density;
717 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
718 if ((pinfo->memctl_opts[i].memctl_interleaving) && \
719 (check_rank_density == pinfo->dimm_params[i][0].rank_density) && \
720 (check_n_ranks == pinfo->dimm_params[i][0].n_ranks)) {
724 if (j != CONFIG_NUM_DDR_CONTROLLERS) {
725 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
726 if (pinfo->memctl_opts[i].memctl_interleaving) {
727 pinfo->memctl_opts[i].memctl_interleaving = 0;
731 printf("Not all DIMMs are identical in size. "
732 "Memory controller interleaving disabled.\n");
736 int fsl_use_spd(void)
740 #ifdef CONFIG_DDR_SPD
741 char buffer[HWCONFIG_BUFFER_SIZE];
745 * Extract hwconfig from environment since we have not properly setup
746 * the environment but need it for ddr config params
748 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
751 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
752 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
753 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
755 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",