2 * Copyright 2008, 2010 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
12 #include <asm/fsl_ddr_sdram.h>
16 /* Board-specific functions defined in each board's ddr.c */
17 extern void fsl_ddr_board_options(memctl_options_t *popts,
19 unsigned int ctrl_num);
21 unsigned int populate_memctl_options(int all_DIMMs_registered,
22 memctl_options_t *popts,
24 unsigned int ctrl_num)
28 /* Chip select options. */
30 /* Pick chip-select local options. */
31 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
32 /* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */
34 /* only for single CS? */
35 popts->cs_local_opts[i].odt_rd_cfg = 0;
37 popts->cs_local_opts[i].odt_wr_cfg = 1;
38 popts->cs_local_opts[i].auto_precharge = 0;
41 /* Pick interleaving mode. */
45 * 1 = interleaving between 2 controllers
47 popts->memctl_interleaving = 0;
53 * 3 = superbank (only if CS interleaving is enabled)
55 popts->memctl_interleaving_mode = 0;
58 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
59 * 1: page: bit to the left of the column bits selects the memctl
60 * 2: bank: bit to the left of the bank bits selects the memctl
61 * 3: superbank: bit to the left of the chip select selects the memctl
63 * NOTE: ba_intlv (rank interleaving) is independent of memory
64 * controller interleaving; it is only within a memory controller.
65 * Must use superbank interleaving if rank interleaving is used and
66 * memory controller interleaving is enabled.
73 * 0x60 = CS0,CS1 + CS2,CS3
74 * 0x04 = CS0,CS1,CS2,CS3
76 popts->ba_intlv_ctl = 0;
78 /* Memory Organization Parameters */
79 popts->registered_dimm_en = all_DIMMs_registered;
81 /* Operational Mode Paramters */
85 popts->ECC_mode = 1; /* 0 = disabled, 1 = enabled */
87 popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
89 popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
96 #if defined(CONFIG_FSL_DDR1)
97 popts->DQS_config = 0;
98 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
99 popts->DQS_config = 1;
102 /* Choose self-refresh during sleep. */
103 popts->self_refresh_in_sleep = 1;
105 /* Choose dynamic power management mode. */
106 popts->dynamic_power = 0;
108 /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
109 popts->data_bus_width = 0;
111 /* Choose burst length. */
112 #if defined(CONFIG_FSL_DDR3)
113 #if defined(CONFIG_E500MC)
114 popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
115 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
117 popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
118 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
121 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
124 /* Choose ddr controller address mirror mode */
125 #if defined(CONFIG_FSL_DDR3)
126 popts->mirrored_dimm = pdimm[0].mirrored_dimm;
129 /* Global Timing Parameters. */
130 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
132 /* Pick a caslat override. */
133 popts->cas_latency_override = 0;
134 popts->cas_latency_override_value = 3;
135 if (popts->cas_latency_override) {
136 debug("using caslat override value = %u\n",
137 popts->cas_latency_override_value);
140 /* Decide whether to use the computed derated latency */
141 popts->use_derated_caslat = 0;
143 /* Choose an additive latency. */
144 popts->additive_latency_override = 0;
145 popts->additive_latency_override_value = 3;
146 if (popts->additive_latency_override) {
147 debug("using additive latency override value = %u\n",
148 popts->additive_latency_override_value);
154 * Factors to consider for 2T_EN:
155 * - number of DIMMs installed
156 * - number of components, number of active ranks
157 * - how much time you want to spend playing around
160 popts->threeT_en = 0;
163 * BSTTOPRE precharge interval
165 * Set this to 0 for global auto precharge
167 * FIXME: Should this be configured in picoseconds?
168 * Why it should be in ps: better understanding of this
169 * relative to actual DRAM timing parameters such as tRAS.
170 * e.g. tRAS(min) = 40 ns
172 popts->bstopre = 0x100;
174 /* Minimum CKE pulse width -- tCKE(MIN) */
175 popts->tCKE_clock_pulse_width_ps
176 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
179 * Window for four activates -- tFAW
181 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
182 * FIXME: varies depending upon number of column addresses or data
183 * FIXME: width, was considering looking at pdimm->primary_sdram_width
185 #if defined(CONFIG_FSL_DDR1)
186 popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
188 #elif defined(CONFIG_FSL_DDR2)
190 * x4/x8; some datasheets have 35000
191 * x16 wide columns only? Use 50000?
193 popts->tFAW_window_four_activates_ps = 37500;
195 #elif defined(CONFIG_FSL_DDR3)
196 popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
200 #if defined(CONFIG_FSL_DDR3)
202 * due to ddr3 dimm is fly-by topology
203 * we suggest to enable write leveling to
204 * meet the tQDSS under different loading.
208 popts->wrlvl_override = 0;
212 * Check interleaving configuration from environment.
213 * Please refer to doc/README.fsl-ddr for the detail.
215 * If memory controller interleaving is enabled, then the data
216 * bus widths must be programmed identically for all memory controllers.
218 * XXX: Attempt to set all controllers to the same chip select
219 * interleaving mode. It will do a best effort to get the
220 * requested ranks interleaved together such that the result
221 * should be a subset of the requested configuration.
223 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
224 if (hwconfig_sub("fsl_ddr", "ctlr_intlv")) {
225 if (pdimm[0].n_ranks == 0) {
226 printf("There is no rank on CS0 for controller %d. Because only"
227 " rank on CS0 and ranks chip-select interleaved with CS0"
228 " are controller interleaved, force non memory "
229 "controller interleaving\n", ctrl_num);
230 popts->memctl_interleaving = 0;
232 popts->memctl_interleaving = 1;
234 * test null first. if CONFIG_HWCONFIG is not defined
235 * hwconfig_arg_cmp returns non-zero
237 if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "null")) {
238 popts->memctl_interleaving = 0;
239 debug("memory controller interleaving disabled.\n");
240 } else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "cacheline"))
241 popts->memctl_interleaving_mode =
242 FSL_DDR_CACHE_LINE_INTERLEAVING;
243 else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "page"))
244 popts->memctl_interleaving_mode =
245 FSL_DDR_PAGE_INTERLEAVING;
246 else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "bank"))
247 popts->memctl_interleaving_mode =
248 FSL_DDR_BANK_INTERLEAVING;
249 else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "superbank"))
250 popts->memctl_interleaving_mode =
251 FSL_DDR_SUPERBANK_INTERLEAVING;
253 popts->memctl_interleaving = 0;
254 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
259 if ((hwconfig_sub("fsl_ddr", "bank_intlv")) &&
260 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
261 /* test null first. if CONFIG_HWCONFIG is not defined,
262 * hwconfig_arg_cmp returns non-zero */
263 if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "null"))
264 debug("bank interleaving disabled.\n");
265 else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1"))
266 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
267 else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs2_cs3"))
268 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
269 else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1_and_cs2_cs3"))
270 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
271 else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1_cs2_cs3"))
272 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
274 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
275 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
276 case FSL_DDR_CS0_CS1_CS2_CS3:
277 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
278 if (pdimm[0].n_ranks < 4) {
279 popts->ba_intlv_ctl = 0;
280 printf("Not enough bank(chip-select) for "
281 "CS0+CS1+CS2+CS3 on controller %d, "
282 "force non-interleaving!\n", ctrl_num);
284 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
285 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
286 popts->ba_intlv_ctl = 0;
287 printf("Not enough bank(chip-select) for "
288 "CS0+CS1+CS2+CS3 on controller %d, "
289 "force non-interleaving!\n", ctrl_num);
291 if (pdimm[0].capacity != pdimm[1].capacity) {
292 popts->ba_intlv_ctl = 0;
293 printf("Not identical DIMM size for "
294 "CS0+CS1+CS2+CS3 on controller %d, "
295 "force non-interleaving!\n", ctrl_num);
299 case FSL_DDR_CS0_CS1:
300 if (pdimm[0].n_ranks < 2) {
301 popts->ba_intlv_ctl = 0;
302 printf("Not enough bank(chip-select) for "
303 "CS0+CS1 on controller %d, "
304 "force non-interleaving!\n", ctrl_num);
307 case FSL_DDR_CS2_CS3:
308 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
309 if (pdimm[0].n_ranks < 4) {
310 popts->ba_intlv_ctl = 0;
311 printf("Not enough bank(chip-select) for CS2+CS3 "
312 "on controller %d, force non-interleaving!\n", ctrl_num);
314 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
315 if (pdimm[1].n_ranks < 2) {
316 popts->ba_intlv_ctl = 0;
317 printf("Not enough bank(chip-select) for CS2+CS3 "
318 "on controller %d, force non-interleaving!\n", ctrl_num);
322 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
323 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
324 if (pdimm[0].n_ranks < 4) {
325 popts->ba_intlv_ctl = 0;
326 printf("Not enough bank(CS) for CS0+CS1 and "
327 "CS2+CS3 on controller %d, "
328 "force non-interleaving!\n", ctrl_num);
330 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
331 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
332 popts->ba_intlv_ctl = 0;
333 printf("Not enough bank(CS) for CS0+CS1 and "
334 "CS2+CS3 on controller %d, "
335 "force non-interleaving!\n", ctrl_num);
340 popts->ba_intlv_ctl = 0;
345 if (hwconfig_sub("fsl_ddr", "addr_hash")) {
346 if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "null"))
347 popts->addr_hash = 0;
348 else if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "true"))
349 popts->addr_hash = 1;
352 if (pdimm[0].n_ranks == 4)
353 popts->quad_rank_present = 1;
355 fsl_ddr_board_options(popts, pdimm, ctrl_num);
360 void check_interleaving_options(fsl_ddr_info_t *pinfo)
362 int i, j, check_n_ranks, intlv_fixed = 0;
363 unsigned long long check_rank_density;
365 * Check if all controllers are configured for memory
366 * controller interleaving. Identical dimms are recommended. At least
367 * the size should be checked.
370 check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
371 check_rank_density = pinfo->dimm_params[0][0].rank_density;
372 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
373 if ((pinfo->memctl_opts[i].memctl_interleaving) && \
374 (check_rank_density == pinfo->dimm_params[i][0].rank_density) && \
375 (check_n_ranks == pinfo->dimm_params[i][0].n_ranks)) {
379 if (j != CONFIG_NUM_DDR_CONTROLLERS) {
380 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
381 if (pinfo->memctl_opts[i].memctl_interleaving) {
382 pinfo->memctl_opts[i].memctl_interleaving = 0;
386 printf("Not all DIMMs are identical in size. "
387 "Memory controller interleaving disabled.\n");