2 * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
12 #include <asm/fsl_ddr_sdram.h>
17 * Use our own stack based buffer before relocation to allow accessing longer
18 * hwconfig strings that might be in the environment before we've relocated.
19 * This is pretty fragile on both the use of stack and if the buffer is big
20 * enough. However we will get a warning from getenv_f for the later.
22 #define HWCONFIG_BUFFER_SIZE 128
24 /* Board-specific functions defined in each board's ddr.c */
25 extern void fsl_ddr_board_options(memctl_options_t *popts,
27 unsigned int ctrl_num);
30 unsigned int odt_rd_cfg;
31 unsigned int odt_wr_cfg;
32 unsigned int odt_rtt_norm;
33 unsigned int odt_rtt_wr;
36 #ifdef CONFIG_FSL_DDR3
37 static const struct dynamic_odt single_Q[4] = {
40 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
46 FSL_DDR_ODT_NEVER, /* tied high */
52 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
58 FSL_DDR_ODT_NEVER, /* tied high */
64 static const struct dynamic_odt single_D[4] = {
81 static const struct dynamic_odt single_S[4] = {
93 static const struct dynamic_odt dual_DD[4] = {
96 FSL_DDR_ODT_SAME_DIMM,
101 FSL_DDR_ODT_OTHER_DIMM,
102 FSL_DDR_ODT_OTHER_DIMM,
108 FSL_DDR_ODT_SAME_DIMM,
113 FSL_DDR_ODT_OTHER_DIMM,
114 FSL_DDR_ODT_OTHER_DIMM,
120 static const struct dynamic_odt dual_DS[4] = {
123 FSL_DDR_ODT_SAME_DIMM,
128 FSL_DDR_ODT_OTHER_DIMM,
129 FSL_DDR_ODT_OTHER_DIMM,
134 FSL_DDR_ODT_OTHER_DIMM,
141 static const struct dynamic_odt dual_SD[4] = {
143 FSL_DDR_ODT_OTHER_DIMM,
151 FSL_DDR_ODT_SAME_DIMM,
156 FSL_DDR_ODT_OTHER_DIMM,
157 FSL_DDR_ODT_OTHER_DIMM,
163 static const struct dynamic_odt dual_SS[4] = {
165 FSL_DDR_ODT_OTHER_DIMM,
172 FSL_DDR_ODT_OTHER_DIMM,
180 static const struct dynamic_odt dual_D0[4] = {
183 FSL_DDR_ODT_SAME_DIMM,
197 static const struct dynamic_odt dual_0D[4] = {
202 FSL_DDR_ODT_SAME_DIMM,
214 static const struct dynamic_odt dual_S0[4] = {
227 static const struct dynamic_odt dual_0S[4] = {
240 static const struct dynamic_odt odt_unknown[4] = {
266 #else /* CONFIG_FSL_DDR3 */
267 static const struct dynamic_odt single_Q[4] = {
274 static const struct dynamic_odt single_D[4] = {
291 static const struct dynamic_odt single_S[4] = {
303 static const struct dynamic_odt dual_DD[4] = {
305 FSL_DDR_ODT_OTHER_DIMM,
306 FSL_DDR_ODT_OTHER_DIMM,
317 FSL_DDR_ODT_OTHER_DIMM,
318 FSL_DDR_ODT_OTHER_DIMM,
330 static const struct dynamic_odt dual_DS[4] = {
332 FSL_DDR_ODT_OTHER_DIMM,
333 FSL_DDR_ODT_OTHER_DIMM,
344 FSL_DDR_ODT_OTHER_DIMM,
345 FSL_DDR_ODT_OTHER_DIMM,
352 static const struct dynamic_odt dual_SD[4] = {
354 FSL_DDR_ODT_OTHER_DIMM,
355 FSL_DDR_ODT_OTHER_DIMM,
361 FSL_DDR_ODT_OTHER_DIMM,
362 FSL_DDR_ODT_OTHER_DIMM,
374 static const struct dynamic_odt dual_SS[4] = {
376 FSL_DDR_ODT_OTHER_DIMM,
377 FSL_DDR_ODT_OTHER_DIMM,
383 FSL_DDR_ODT_OTHER_DIMM,
384 FSL_DDR_ODT_OTHER_DIMM,
391 static const struct dynamic_odt dual_D0[4] = {
408 static const struct dynamic_odt dual_0D[4] = {
425 static const struct dynamic_odt dual_S0[4] = {
438 static const struct dynamic_odt dual_0S[4] = {
451 static const struct dynamic_odt odt_unknown[4] = {
478 unsigned int populate_memctl_options(int all_DIMMs_registered,
479 memctl_options_t *popts,
480 dimm_params_t *pdimm,
481 unsigned int ctrl_num)
484 char buffer[HWCONFIG_BUFFER_SIZE];
486 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
487 const struct dynamic_odt *pdodt = odt_unknown;
492 * Extract hwconfig from environment since we have not properly setup
493 * the environment but need it for ddr config params
495 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
498 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
499 /* Chip select options. */
500 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
501 switch (pdimm[0].n_ranks) {
512 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
513 switch (pdimm[0].n_ranks) {
515 switch (pdimm[1].n_ranks) {
528 switch (pdimm[1].n_ranks) {
541 switch (pdimm[1].n_ranks) {
554 /* Pick chip-select local options. */
555 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
556 #if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
557 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
558 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
559 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
560 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
562 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
563 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
565 popts->cs_local_opts[i].auto_precharge = 0;
568 /* Pick interleaving mode. */
571 * 0 = no interleaving
572 * 1 = interleaving between 2 controllers
574 popts->memctl_interleaving = 0;
580 * 3 = superbank (only if CS interleaving is enabled)
582 popts->memctl_interleaving_mode = 0;
585 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
586 * 1: page: bit to the left of the column bits selects the memctl
587 * 2: bank: bit to the left of the bank bits selects the memctl
588 * 3: superbank: bit to the left of the chip select selects the memctl
590 * NOTE: ba_intlv (rank interleaving) is independent of memory
591 * controller interleaving; it is only within a memory controller.
592 * Must use superbank interleaving if rank interleaving is used and
593 * memory controller interleaving is enabled.
600 * 0x60 = CS0,CS1 + CS2,CS3
601 * 0x04 = CS0,CS1,CS2,CS3
603 popts->ba_intlv_ctl = 0;
605 /* Memory Organization Parameters */
606 popts->registered_dimm_en = all_DIMMs_registered;
608 /* Operational Mode Paramters */
611 popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
612 #ifdef CONFIG_DDR_ECC
613 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
614 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
619 popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
626 #if defined(CONFIG_FSL_DDR1)
627 popts->DQS_config = 0;
628 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
629 popts->DQS_config = 1;
632 /* Choose self-refresh during sleep. */
633 popts->self_refresh_in_sleep = 1;
635 /* Choose dynamic power management mode. */
636 popts->dynamic_power = 0;
639 * check first dimm for primary sdram width
640 * presuming all dimms are similar
641 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
643 #if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
644 if (pdimm[0].n_ranks != 0) {
645 if ((pdimm[0].data_width >= 64) && \
646 (pdimm[0].data_width <= 72))
647 popts->data_bus_width = 0;
648 else if ((pdimm[0].data_width >= 32) || \
649 (pdimm[0].data_width <= 40))
650 popts->data_bus_width = 1;
652 panic("Error: data width %u is invalid!\n",
653 pdimm[0].data_width);
657 if (pdimm[0].n_ranks != 0) {
658 if (pdimm[0].primary_sdram_width == 64)
659 popts->data_bus_width = 0;
660 else if (pdimm[0].primary_sdram_width == 32)
661 popts->data_bus_width = 1;
662 else if (pdimm[0].primary_sdram_width == 16)
663 popts->data_bus_width = 2;
665 panic("Error: primary sdram width %u is invalid!\n",
666 pdimm[0].primary_sdram_width);
671 /* Choose burst length. */
672 #if defined(CONFIG_FSL_DDR3)
673 #if defined(CONFIG_E500MC)
674 popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
675 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
677 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
678 /* 32-bit or 16-bit bus */
679 popts->OTF_burst_chop_en = 0;
680 popts->burst_length = DDR_BL8;
682 popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
683 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
687 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
690 /* Choose ddr controller address mirror mode */
691 #if defined(CONFIG_FSL_DDR3)
692 popts->mirrored_dimm = pdimm[0].mirrored_dimm;
695 /* Global Timing Parameters. */
696 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
698 /* Pick a caslat override. */
699 popts->cas_latency_override = 0;
700 popts->cas_latency_override_value = 3;
701 if (popts->cas_latency_override) {
702 debug("using caslat override value = %u\n",
703 popts->cas_latency_override_value);
706 /* Decide whether to use the computed derated latency */
707 popts->use_derated_caslat = 0;
709 /* Choose an additive latency. */
710 popts->additive_latency_override = 0;
711 popts->additive_latency_override_value = 3;
712 if (popts->additive_latency_override) {
713 debug("using additive latency override value = %u\n",
714 popts->additive_latency_override_value);
720 * Factors to consider for 2T_EN:
721 * - number of DIMMs installed
722 * - number of components, number of active ranks
723 * - how much time you want to spend playing around
726 popts->threeT_en = 0;
728 /* for RDIMM, address parity enable */
732 * BSTTOPRE precharge interval
734 * Set this to 0 for global auto precharge
736 * FIXME: Should this be configured in picoseconds?
737 * Why it should be in ps: better understanding of this
738 * relative to actual DRAM timing parameters such as tRAS.
739 * e.g. tRAS(min) = 40 ns
741 popts->bstopre = 0x100;
743 /* Minimum CKE pulse width -- tCKE(MIN) */
744 popts->tCKE_clock_pulse_width_ps
745 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
748 * Window for four activates -- tFAW
750 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
751 * FIXME: varies depending upon number of column addresses or data
752 * FIXME: width, was considering looking at pdimm->primary_sdram_width
754 #if defined(CONFIG_FSL_DDR1)
755 popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
757 #elif defined(CONFIG_FSL_DDR2)
759 * x4/x8; some datasheets have 35000
760 * x16 wide columns only? Use 50000?
762 popts->tFAW_window_four_activates_ps = 37500;
764 #elif defined(CONFIG_FSL_DDR3)
765 popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
769 #if defined(CONFIG_FSL_DDR3)
771 * due to ddr3 dimm is fly-by topology
772 * we suggest to enable write leveling to
773 * meet the tQDSS under different loading.
777 popts->wrlvl_override = 0;
781 * Check interleaving configuration from environment.
782 * Please refer to doc/README.fsl-ddr for the detail.
784 * If memory controller interleaving is enabled, then the data
785 * bus widths must be programmed identically for all memory controllers.
787 * XXX: Attempt to set all controllers to the same chip select
788 * interleaving mode. It will do a best effort to get the
789 * requested ranks interleaved together such that the result
790 * should be a subset of the requested configuration.
792 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
793 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
796 if (pdimm[0].n_ranks == 0) {
797 printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
798 popts->memctl_interleaving = 0;
801 popts->memctl_interleaving = 1;
803 * test null first. if CONFIG_HWCONFIG is not defined
804 * hwconfig_arg_cmp returns non-zero
806 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
808 popts->memctl_interleaving = 0;
809 debug("memory controller interleaving disabled.\n");
810 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
813 popts->memctl_interleaving_mode =
814 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
815 0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
816 popts->memctl_interleaving =
817 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
819 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
822 popts->memctl_interleaving_mode =
823 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
824 0 : FSL_DDR_PAGE_INTERLEAVING;
825 popts->memctl_interleaving =
826 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
828 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
831 popts->memctl_interleaving_mode =
832 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
833 0 : FSL_DDR_BANK_INTERLEAVING;
834 popts->memctl_interleaving =
835 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
837 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
840 popts->memctl_interleaving_mode =
841 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
842 0 : FSL_DDR_SUPERBANK_INTERLEAVING;
843 popts->memctl_interleaving =
844 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
846 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
847 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
850 popts->memctl_interleaving_mode =
851 FSL_DDR_3WAY_1KB_INTERLEAVING;
852 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
855 popts->memctl_interleaving_mode =
856 FSL_DDR_3WAY_4KB_INTERLEAVING;
857 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
860 popts->memctl_interleaving_mode =
861 FSL_DDR_3WAY_8KB_INTERLEAVING;
862 #elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
863 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
866 popts->memctl_interleaving_mode =
867 FSL_DDR_4WAY_1KB_INTERLEAVING;
868 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
871 popts->memctl_interleaving_mode =
872 FSL_DDR_4WAY_4KB_INTERLEAVING;
873 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
876 popts->memctl_interleaving_mode =
877 FSL_DDR_4WAY_8KB_INTERLEAVING;
880 popts->memctl_interleaving = 0;
881 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
885 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
886 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
887 /* test null first. if CONFIG_HWCONFIG is not defined,
888 * hwconfig_subarg_cmp_f returns non-zero */
889 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
891 debug("bank interleaving disabled.\n");
892 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
894 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
895 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
897 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
898 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
899 "cs0_cs1_and_cs2_cs3", buf))
900 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
901 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
902 "cs0_cs1_cs2_cs3", buf))
903 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
905 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
906 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
907 case FSL_DDR_CS0_CS1_CS2_CS3:
908 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
909 if (pdimm[0].n_ranks < 4) {
910 popts->ba_intlv_ctl = 0;
911 printf("Not enough bank(chip-select) for "
912 "CS0+CS1+CS2+CS3 on controller %d, "
913 "interleaving disabled!\n", ctrl_num);
915 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
916 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
917 popts->ba_intlv_ctl = 0;
918 printf("Not enough bank(chip-select) for "
919 "CS0+CS1+CS2+CS3 on controller %d, "
920 "interleaving disabled!\n", ctrl_num);
922 if (pdimm[0].capacity != pdimm[1].capacity) {
923 popts->ba_intlv_ctl = 0;
924 printf("Not identical DIMM size for "
925 "CS0+CS1+CS2+CS3 on controller %d, "
926 "interleaving disabled!\n", ctrl_num);
930 case FSL_DDR_CS0_CS1:
931 if (pdimm[0].n_ranks < 2) {
932 popts->ba_intlv_ctl = 0;
933 printf("Not enough bank(chip-select) for "
934 "CS0+CS1 on controller %d, "
935 "interleaving disabled!\n", ctrl_num);
938 case FSL_DDR_CS2_CS3:
939 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
940 if (pdimm[0].n_ranks < 4) {
941 popts->ba_intlv_ctl = 0;
942 printf("Not enough bank(chip-select) for CS2+CS3 "
943 "on controller %d, interleaving disabled!\n", ctrl_num);
945 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
946 if (pdimm[1].n_ranks < 2) {
947 popts->ba_intlv_ctl = 0;
948 printf("Not enough bank(chip-select) for CS2+CS3 "
949 "on controller %d, interleaving disabled!\n", ctrl_num);
953 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
954 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
955 if (pdimm[0].n_ranks < 4) {
956 popts->ba_intlv_ctl = 0;
957 printf("Not enough bank(CS) for CS0+CS1 and "
958 "CS2+CS3 on controller %d, "
959 "interleaving disabled!\n", ctrl_num);
961 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
962 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
963 popts->ba_intlv_ctl = 0;
964 printf("Not enough bank(CS) for CS0+CS1 and "
965 "CS2+CS3 on controller %d, "
966 "interleaving disabled!\n", ctrl_num);
971 popts->ba_intlv_ctl = 0;
976 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
977 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
978 popts->addr_hash = 0;
979 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
981 popts->addr_hash = 1;
984 if (pdimm[0].n_ranks == 4)
985 popts->quad_rank_present = 1;
987 ddr_freq = get_ddr_freq(0) / 1000000;
988 if (popts->registered_dimm_en) {
989 popts->rcw_override = 1;
990 popts->rcw_1 = 0x000a5a00;
992 popts->rcw_2 = 0x00000000;
993 else if (ddr_freq <= 1066)
994 popts->rcw_2 = 0x00100000;
995 else if (ddr_freq <= 1333)
996 popts->rcw_2 = 0x00200000;
998 popts->rcw_2 = 0x00300000;
1001 fsl_ddr_board_options(popts, pdimm, ctrl_num);
1006 void check_interleaving_options(fsl_ddr_info_t *pinfo)
1008 int i, j, k, check_n_ranks, intlv_invalid = 0;
1009 unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
1010 unsigned long long check_rank_density;
1011 struct dimm_params_s *dimm;
1013 * Check if all controllers are configured for memory
1014 * controller interleaving. Identical dimms are recommended. At least
1015 * the size, row and col address should be checked.
1018 check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
1019 check_rank_density = pinfo->dimm_params[0][0].rank_density;
1020 check_n_row_addr = pinfo->dimm_params[0][0].n_row_addr;
1021 check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr;
1022 check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode;
1023 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1024 dimm = &pinfo->dimm_params[i][0];
1025 if (!pinfo->memctl_opts[i].memctl_interleaving) {
1027 } else if (((check_rank_density != dimm->rank_density) ||
1028 (check_n_ranks != dimm->n_ranks) ||
1029 (check_n_row_addr != dimm->n_row_addr) ||
1030 (check_n_col_addr != dimm->n_col_addr) ||
1032 pinfo->memctl_opts[i].memctl_interleaving_mode))){
1040 if (intlv_invalid) {
1041 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
1042 pinfo->memctl_opts[i].memctl_interleaving = 0;
1043 printf("Not all DIMMs are identical. "
1044 "Memory controller interleaving disabled.\n");
1046 switch (check_intlv) {
1047 case FSL_DDR_CACHE_LINE_INTERLEAVING:
1048 case FSL_DDR_PAGE_INTERLEAVING:
1049 case FSL_DDR_BANK_INTERLEAVING:
1050 case FSL_DDR_SUPERBANK_INTERLEAVING:
1051 if (3 == CONFIG_NUM_DDR_CONTROLLERS)
1054 k = CONFIG_NUM_DDR_CONTROLLERS;
1056 case FSL_DDR_3WAY_1KB_INTERLEAVING:
1057 case FSL_DDR_3WAY_4KB_INTERLEAVING:
1058 case FSL_DDR_3WAY_8KB_INTERLEAVING:
1059 case FSL_DDR_4WAY_1KB_INTERLEAVING:
1060 case FSL_DDR_4WAY_4KB_INTERLEAVING:
1061 case FSL_DDR_4WAY_8KB_INTERLEAVING:
1063 k = CONFIG_NUM_DDR_CONTROLLERS;
1066 debug("%d of %d controllers are interleaving.\n", j, k);
1068 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
1069 pinfo->memctl_opts[i].memctl_interleaving = 0;
1070 printf("Not all controllers have compatible "
1071 "interleaving mode. All disabled.\n");
1074 debug("Checking interleaving options completed\n");
1077 int fsl_use_spd(void)
1081 #ifdef CONFIG_DDR_SPD
1082 char buffer[HWCONFIG_BUFFER_SIZE];
1086 * Extract hwconfig from environment since we have not properly setup
1087 * the environment but need it for ddr config params
1089 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
1092 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1093 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1094 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1096 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",