git.sur5r.net Git - u-boot/blob - arch/powerpc/cpu/mpc8xxx/ddr/options.c

   1 /*
   2  * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 #include <common.h>
  11 #include <hwconfig.h>
  12 #include <asm/fsl_ddr_sdram.h>
  13
  14 #include "ddr.h"
  15
  16 /*
  17  * Use our own stack based buffer before relocation to allow accessing longer
  18  * hwconfig strings that might be in the environment before we've relocated.
  19  * This is pretty fragile on both the use of stack and if the buffer is big
  20  * enough. However we will get a warning from getenv_f for the later.
  21  */
  22 #define HWCONFIG_BUFFER_SIZE    128
  23
  24 /* Board-specific functions defined in each board's ddr.c */
  25 extern void fsl_ddr_board_options(memctl_options_t *popts,
  26                 dimm_params_t *pdimm,
  27                 unsigned int ctrl_num);
  28
  29 typedef struct {
  30         unsigned int odt_rd_cfg;
  31         unsigned int odt_wr_cfg;
  32         unsigned int odt_rtt_norm;
  33         unsigned int odt_rtt_wr;
  34 } dynamic_odt_t;
  35
  36 static const dynamic_odt_t single_Q[4] = {
  37         {       /* cs0 */
  38                 FSL_DDR_ODT_NEVER,
  39                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  40                 DDR3_RTT_20_OHM,
  41                 DDR3_RTT_120_OHM
  42         },
  43         {       /* cs1 */
  44                 FSL_DDR_ODT_NEVER,
  45                 FSL_DDR_ODT_NEVER,      /* tied high */
  46                 DDR3_RTT_OFF,
  47                 DDR3_RTT_120_OHM
  48         },
  49         {       /* cs2 */
  50                 FSL_DDR_ODT_NEVER,
  51                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  52                 DDR3_RTT_20_OHM,
  53                 DDR3_RTT_120_OHM
  54         },
  55         {       /* cs3 */
  56                 FSL_DDR_ODT_NEVER,
  57                 FSL_DDR_ODT_NEVER,      /* tied high */
  58                 DDR3_RTT_OFF,
  59                 DDR3_RTT_120_OHM
  60         }
  61 };
  62
  63 static const dynamic_odt_t single_D[4] = {
  64         {       /* cs0 */
  65                 FSL_DDR_ODT_NEVER,
  66                 FSL_DDR_ODT_ALL,
  67                 DDR3_RTT_40_OHM,
  68                 DDR3_RTT_OFF
  69         },
  70         {       /* cs1 */
  71                 FSL_DDR_ODT_NEVER,
  72                 FSL_DDR_ODT_NEVER,
  73                 DDR3_RTT_OFF,
  74                 DDR3_RTT_OFF
  75         },
  76         {0, 0, 0, 0},
  77         {0, 0, 0, 0}
  78 };
  79
  80 static const dynamic_odt_t single_S[4] = {
  81         {       /* cs0 */
  82                 FSL_DDR_ODT_NEVER,
  83                 FSL_DDR_ODT_ALL,
  84                 DDR3_RTT_40_OHM,
  85                 DDR3_RTT_OFF
  86         },
  87         {0, 0, 0, 0},
  88         {0, 0, 0, 0},
  89         {0, 0, 0, 0},
  90 };
  91
  92 static const dynamic_odt_t dual_DD[4] = {
  93         {       /* cs0 */
  94                 FSL_DDR_ODT_NEVER,
  95                 FSL_DDR_ODT_SAME_DIMM,
  96                 DDR3_RTT_120_OHM,
  97                 DDR3_RTT_OFF
  98         },
  99         {       /* cs1 */
 100                 FSL_DDR_ODT_OTHER_DIMM,
 101                 FSL_DDR_ODT_OTHER_DIMM,
 102                 DDR3_RTT_30_OHM,
 103                 DDR3_RTT_OFF
 104         },
 105         {       /* cs2 */
 106                 FSL_DDR_ODT_NEVER,
 107                 FSL_DDR_ODT_SAME_DIMM,
 108                 DDR3_RTT_120_OHM,
 109                 DDR3_RTT_OFF
 110         },
 111         {       /* cs3 */
 112                 FSL_DDR_ODT_OTHER_DIMM,
 113                 FSL_DDR_ODT_OTHER_DIMM,
 114                 DDR3_RTT_30_OHM,
 115                 DDR3_RTT_OFF
 116         }
 117 };
 118
 119 static const dynamic_odt_t dual_DS[4] = {
 120         {       /* cs0 */
 121                 FSL_DDR_ODT_NEVER,
 122                 FSL_DDR_ODT_SAME_DIMM,
 123                 DDR3_RTT_120_OHM,
 124                 DDR3_RTT_OFF
 125         },
 126         {       /* cs1 */
 127                 FSL_DDR_ODT_OTHER_DIMM,
 128                 FSL_DDR_ODT_OTHER_DIMM,
 129                 DDR3_RTT_30_OHM,
 130                 DDR3_RTT_OFF
 131         },
 132         {       /* cs2 */
 133                 FSL_DDR_ODT_OTHER_DIMM,
 134                 FSL_DDR_ODT_ALL,
 135                 DDR3_RTT_20_OHM,
 136                 DDR3_RTT_120_OHM
 137         },
 138         {0, 0, 0, 0}
 139 };
 140 static const dynamic_odt_t dual_SD[4] = {
 141         {       /* cs0 */
 142                 FSL_DDR_ODT_OTHER_DIMM,
 143                 FSL_DDR_ODT_ALL,
 144                 DDR3_RTT_20_OHM,
 145                 DDR3_RTT_120_OHM
 146         },
 147         {0, 0, 0, 0},
 148         {       /* cs2 */
 149                 FSL_DDR_ODT_NEVER,
 150                 FSL_DDR_ODT_SAME_DIMM,
 151                 DDR3_RTT_120_OHM,
 152                 DDR3_RTT_OFF
 153         },
 154         {       /* cs3 */
 155                 FSL_DDR_ODT_OTHER_DIMM,
 156                 FSL_DDR_ODT_OTHER_DIMM,
 157                 DDR3_RTT_20_OHM,
 158                 DDR3_RTT_OFF
 159         }
 160 };
 161
 162 static const dynamic_odt_t dual_SS[4] = {
 163         {       /* cs0 */
 164                 FSL_DDR_ODT_OTHER_DIMM,
 165                 FSL_DDR_ODT_ALL,
 166                 DDR3_RTT_30_OHM,
 167                 DDR3_RTT_120_OHM
 168         },
 169         {0, 0, 0, 0},
 170         {       /* cs2 */
 171                 FSL_DDR_ODT_OTHER_DIMM,
 172                 FSL_DDR_ODT_ALL,
 173                 DDR3_RTT_30_OHM,
 174                 DDR3_RTT_120_OHM
 175         },
 176         {0, 0, 0, 0}
 177 };
 178
 179 static const dynamic_odt_t dual_D0[4] = {
 180         {       /* cs0 */
 181                 FSL_DDR_ODT_NEVER,
 182                 FSL_DDR_ODT_SAME_DIMM,
 183                 DDR3_RTT_40_OHM,
 184                 DDR3_RTT_OFF
 185         },
 186         {       /* cs1 */
 187                 FSL_DDR_ODT_NEVER,
 188                 FSL_DDR_ODT_NEVER,
 189                 DDR3_RTT_OFF,
 190                 DDR3_RTT_OFF
 191         },
 192         {0, 0, 0, 0},
 193         {0, 0, 0, 0}
 194 };
 195
 196 static const dynamic_odt_t dual_0D[4] = {
 197         {0, 0, 0, 0},
 198         {0, 0, 0, 0},
 199         {       /* cs2 */
 200                 FSL_DDR_ODT_NEVER,
 201                 FSL_DDR_ODT_SAME_DIMM,
 202                 DDR3_RTT_40_OHM,
 203                 DDR3_RTT_OFF
 204         },
 205         {       /* cs3 */
 206                 FSL_DDR_ODT_NEVER,
 207                 FSL_DDR_ODT_NEVER,
 208                 DDR3_RTT_OFF,
 209                 DDR3_RTT_OFF
 210         }
 211 };
 212
 213 static const dynamic_odt_t dual_S0[4] = {
 214         {       /* cs0 */
 215                 FSL_DDR_ODT_NEVER,
 216                 FSL_DDR_ODT_CS,
 217                 DDR3_RTT_40_OHM,
 218                 DDR3_RTT_OFF
 219         },
 220         {0, 0, 0, 0},
 221         {0, 0, 0, 0},
 222         {0, 0, 0, 0}
 223
 224 };
 225
 226 static const dynamic_odt_t dual_0S[4] = {
 227         {0, 0, 0, 0},
 228         {0, 0, 0, 0},
 229         {       /* cs2 */
 230                 FSL_DDR_ODT_NEVER,
 231                 FSL_DDR_ODT_CS,
 232                 DDR3_RTT_40_OHM,
 233                 DDR3_RTT_OFF
 234         },
 235         {0, 0, 0, 0}
 236
 237 };
 238
 239 static const dynamic_odt_t odt_unknown[4] = {
 240         {       /* cs0 */
 241                 FSL_DDR_ODT_NEVER,
 242                 FSL_DDR_ODT_CS,
 243                 DDR3_RTT_120_OHM,
 244                 DDR3_RTT_OFF
 245         },
 246         {       /* cs1 */
 247                 FSL_DDR_ODT_NEVER,
 248                 FSL_DDR_ODT_CS,
 249                 DDR3_RTT_120_OHM,
 250                 DDR3_RTT_OFF
 251         },
 252         {       /* cs2 */
 253                 FSL_DDR_ODT_NEVER,
 254                 FSL_DDR_ODT_CS,
 255                 DDR3_RTT_120_OHM,
 256                 DDR3_RTT_OFF
 257         },
 258         {       /* cs3 */
 259                 FSL_DDR_ODT_NEVER,
 260                 FSL_DDR_ODT_CS,
 261                 DDR3_RTT_120_OHM,
 262                 DDR3_RTT_OFF
 263         }
 264 };
 265
 266 unsigned int populate_memctl_options(int all_DIMMs_registered,
 267                         memctl_options_t *popts,
 268                         dimm_params_t *pdimm,
 269                         unsigned int ctrl_num)
 270 {
 271         unsigned int i;
 272         char buffer[HWCONFIG_BUFFER_SIZE];
 273         char *buf = NULL;
 274         const dynamic_odt_t *pdodt = odt_unknown;
 275         ulong ddr_freq;
 276
 277         /*
 278          * Extract hwconfig from environment since we have not properly setup
 279          * the environment but need it for ddr config params
 280          */
 281         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 282                 buf = buffer;
 283
 284         /* Chip select options. */
 285         if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
 286                 switch (pdimm[0].n_ranks) {
 287                 case 1:
 288                         pdodt = single_S;
 289                         break;
 290                 case 2:
 291                         pdodt = single_D;
 292                         break;
 293                 case 4:
 294                         pdodt = single_Q;
 295                         break;
 296                 }
 297         } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
 298                 switch (pdimm[0].n_ranks) {
 299                 case 2:
 300                         switch (pdimm[1].n_ranks) {
 301                         case 2:
 302                                 pdodt = dual_DD;
 303                                 break;
 304                         case 1:
 305                                 pdodt = dual_DS;
 306                                 break;
 307                         case 0:
 308                                 pdodt = dual_D0;
 309                                 break;
 310                         }
 311                         break;
 312                 case 1:
 313                         switch (pdimm[1].n_ranks) {
 314                         case 2:
 315                                 pdodt = dual_SD;
 316                                 break;
 317                         case 1:
 318                                 pdodt = dual_SS;
 319                                 break;
 320                         case 0:
 321                                 pdodt = dual_S0;
 322                                 break;
 323                         }
 324                         break;
 325                 case 0:
 326                         switch (pdimm[1].n_ranks) {
 327                         case 2:
 328                                 pdodt = dual_0D;
 329                                 break;
 330                         case 1:
 331                                 pdodt = dual_0S;
 332                                 break;
 333                         }
 334                         break;
 335                 }
 336         }
 337
 338         /* Pick chip-select local options. */
 339         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 340 #if defined(CONFIG_FSL_DDR3)
 341                 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
 342                 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
 343                 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
 344                 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
 345 #else
 346                 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
 347                 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
 348 #endif
 349                 popts->cs_local_opts[i].auto_precharge = 0;
 350         }
 351
 352         /* Pick interleaving mode. */
 353
 354         /*
 355          * 0 = no interleaving
 356          * 1 = interleaving between 2 controllers
 357          */
 358         popts->memctl_interleaving = 0;
 359
 360         /*
 361          * 0 = cacheline
 362          * 1 = page
 363          * 2 = (logical) bank
 364          * 3 = superbank (only if CS interleaving is enabled)
 365          */
 366         popts->memctl_interleaving_mode = 0;
 367
 368         /*
 369          * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
 370          * 1: page:      bit to the left of the column bits selects the memctl
 371          * 2: bank:      bit to the left of the bank bits selects the memctl
 372          * 3: superbank: bit to the left of the chip select selects the memctl
 373          *
 374          * NOTE: ba_intlv (rank interleaving) is independent of memory
 375          * controller interleaving; it is only within a memory controller.
 376          * Must use superbank interleaving if rank interleaving is used and
 377          * memory controller interleaving is enabled.
 378          */
 379
 380         /*
 381          * 0 = no
 382          * 0x40 = CS0,CS1
 383          * 0x20 = CS2,CS3
 384          * 0x60 = CS0,CS1 + CS2,CS3
 385          * 0x04 = CS0,CS1,CS2,CS3
 386          */
 387         popts->ba_intlv_ctl = 0;
 388
 389         /* Memory Organization Parameters */
 390         popts->registered_dimm_en = all_DIMMs_registered;
 391
 392         /* Operational Mode Paramters */
 393
 394         /* Pick ECC modes */
 395         popts->ECC_mode = 0;              /* 0 = disabled, 1 = enabled */
 396 #ifdef CONFIG_DDR_ECC
 397         if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
 398                 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
 399                         popts->ECC_mode = 1;
 400         } else
 401                 popts->ECC_mode = 1;
 402 #endif
 403         popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
 404
 405         /*
 406          * Choose DQS config
 407          * 0 for DDR1
 408          * 1 for DDR2
 409          */
 410 #if defined(CONFIG_FSL_DDR1)
 411         popts->DQS_config = 0;
 412 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
 413         popts->DQS_config = 1;
 414 #endif
 415
 416         /* Choose self-refresh during sleep. */
 417         popts->self_refresh_in_sleep = 1;
 418
 419         /* Choose dynamic power management mode. */
 420         popts->dynamic_power = 0;
 421
 422         /*
 423          * check first dimm for primary sdram width
 424          * presuming all dimms are similar
 425          * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
 426          */
 427 #if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
 428         if (pdimm[0].n_ranks != 0) {
 429                 if ((pdimm[0].data_width >= 64) && \
 430                         (pdimm[0].data_width <= 72))
 431                         popts->data_bus_width = 0;
 432                 else if ((pdimm[0].data_width >= 32) || \
 433                         (pdimm[0].data_width <= 40))
 434                         popts->data_bus_width = 1;
 435                 else {
 436                         panic("Error: data width %u is invalid!\n",
 437                                 pdimm[0].data_width);
 438                 }
 439         }
 440 #else
 441         if (pdimm[0].n_ranks != 0) {
 442                 if (pdimm[0].primary_sdram_width == 64)
 443                         popts->data_bus_width = 0;
 444                 else if (pdimm[0].primary_sdram_width == 32)
 445                         popts->data_bus_width = 1;
 446                 else if (pdimm[0].primary_sdram_width == 16)
 447                         popts->data_bus_width = 2;
 448                 else {
 449                         panic("Error: primary sdram width %u is invalid!\n",
 450                                 pdimm[0].primary_sdram_width);
 451                 }
 452         }
 453 #endif
 454
 455         /* Choose burst length. */
 456 #if defined(CONFIG_FSL_DDR3)
 457 #if defined(CONFIG_E500MC)
 458         popts->OTF_burst_chop_en = 0;   /* on-the-fly burst chop disable */
 459         popts->burst_length = DDR_BL8;  /* Fixed 8-beat burst len */
 460 #else
 461         if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
 462                 /* 32-bit or 16-bit bus */
 463                 popts->OTF_burst_chop_en = 0;
 464                 popts->burst_length = DDR_BL8;
 465         } else {
 466                 popts->OTF_burst_chop_en = 1;   /* on-the-fly burst chop */
 467                 popts->burst_length = DDR_OTF;  /* on-the-fly BC4 and BL8 */
 468         }
 469 #endif
 470 #else
 471         popts->burst_length = DDR_BL4;  /* has to be 4 for DDR2 */
 472 #endif
 473
 474         /* Choose ddr controller address mirror mode */
 475 #if defined(CONFIG_FSL_DDR3)
 476         popts->mirrored_dimm = pdimm[0].mirrored_dimm;
 477 #endif
 478
 479         /* Global Timing Parameters. */
 480         debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
 481
 482         /* Pick a caslat override. */
 483         popts->cas_latency_override = 0;
 484         popts->cas_latency_override_value = 3;
 485         if (popts->cas_latency_override) {
 486                 debug("using caslat override value = %u\n",
 487                        popts->cas_latency_override_value);
 488         }
 489
 490         /* Decide whether to use the computed derated latency */
 491         popts->use_derated_caslat = 0;
 492
 493         /* Choose an additive latency. */
 494         popts->additive_latency_override = 0;
 495         popts->additive_latency_override_value = 3;
 496         if (popts->additive_latency_override) {
 497                 debug("using additive latency override value = %u\n",
 498                        popts->additive_latency_override_value);
 499         }
 500
 501         /*
 502          * 2T_EN setting
 503          *
 504          * Factors to consider for 2T_EN:
 505          *      - number of DIMMs installed
 506          *      - number of components, number of active ranks
 507          *      - how much time you want to spend playing around
 508          */
 509         popts->twoT_en = 0;
 510         popts->threeT_en = 0;
 511
 512         /* for RDIMM, address parity enable */
 513         popts->ap_en = 1;
 514
 515         /*
 516          * BSTTOPRE precharge interval
 517          *
 518          * Set this to 0 for global auto precharge
 519          *
 520          * FIXME: Should this be configured in picoseconds?
 521          * Why it should be in ps:  better understanding of this
 522          * relative to actual DRAM timing parameters such as tRAS.
 523          * e.g. tRAS(min) = 40 ns
 524          */
 525         popts->bstopre = 0x100;
 526
 527         /* Minimum CKE pulse width -- tCKE(MIN) */
 528         popts->tCKE_clock_pulse_width_ps
 529                 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
 530
 531         /*
 532          * Window for four activates -- tFAW
 533          *
 534          * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
 535          * FIXME: varies depending upon number of column addresses or data
 536          * FIXME: width, was considering looking at pdimm->primary_sdram_width
 537          */
 538 #if defined(CONFIG_FSL_DDR1)
 539         popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
 540
 541 #elif defined(CONFIG_FSL_DDR2)
 542         /*
 543          * x4/x8;  some datasheets have 35000
 544          * x16 wide columns only?  Use 50000?
 545          */
 546         popts->tFAW_window_four_activates_ps = 37500;
 547
 548 #elif defined(CONFIG_FSL_DDR3)
 549         popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
 550 #endif
 551         popts->zq_en = 0;
 552         popts->wrlvl_en = 0;
 553 #if defined(CONFIG_FSL_DDR3)
 554         /*
 555          * due to ddr3 dimm is fly-by topology
 556          * we suggest to enable write leveling to
 557          * meet the tQDSS under different loading.
 558          */
 559         popts->wrlvl_en = 1;
 560         popts->zq_en = 1;
 561         popts->wrlvl_override = 0;
 562 #endif
 563
 564         /*
 565          * Check interleaving configuration from environment.
 566          * Please refer to doc/README.fsl-ddr for the detail.
 567          *
 568          * If memory controller interleaving is enabled, then the data
 569          * bus widths must be programmed identically for all memory controllers.
 570          *
 571          * XXX: Attempt to set all controllers to the same chip select
 572          * interleaving mode. It will do a best effort to get the
 573          * requested ranks interleaved together such that the result
 574          * should be a subset of the requested configuration.
 575          */
 576 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 577         if (hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) {
 578                 if (pdimm[0].n_ranks == 0) {
 579                         printf("There is no rank on CS0 for controller %d. Because only"
 580                                 " rank on CS0 and ranks chip-select interleaved with CS0"
 581                                 " are controller interleaved, force non memory "
 582                                 "controller interleaving\n", ctrl_num);
 583                         popts->memctl_interleaving = 0;
 584                 } else {
 585                         popts->memctl_interleaving = 1;
 586                         /*
 587                          * test null first. if CONFIG_HWCONFIG is not defined
 588                          * hwconfig_arg_cmp returns non-zero
 589                          */
 590                         if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 591                                                     "null", buf)) {
 592                                 popts->memctl_interleaving = 0;
 593                                 debug("memory controller interleaving disabled.\n");
 594                         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 595                                                          "ctlr_intlv",
 596                                                          "cacheline", buf))
 597                                 popts->memctl_interleaving_mode =
 598                                         FSL_DDR_CACHE_LINE_INTERLEAVING;
 599                         else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 600                                                        "page", buf))
 601                                 popts->memctl_interleaving_mode =
 602                                         FSL_DDR_PAGE_INTERLEAVING;
 603                         else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 604                                                        "bank", buf))
 605                                 popts->memctl_interleaving_mode =
 606                                         FSL_DDR_BANK_INTERLEAVING;
 607                         else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 608                                                        "superbank", buf))
 609                                 popts->memctl_interleaving_mode =
 610                                         FSL_DDR_SUPERBANK_INTERLEAVING;
 611                         else {
 612                                 popts->memctl_interleaving = 0;
 613                                 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
 614                         }
 615                 }
 616         }
 617 #endif
 618         if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
 619                 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
 620                 /* test null first. if CONFIG_HWCONFIG is not defined,
 621                  * hwconfig_subarg_cmp_f returns non-zero */
 622                 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 623                                             "null", buf))
 624                         debug("bank interleaving disabled.\n");
 625                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 626                                                  "cs0_cs1", buf))
 627                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
 628                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 629                                                  "cs2_cs3", buf))
 630                         popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
 631                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 632                                                  "cs0_cs1_and_cs2_cs3", buf))
 633                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
 634                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 635                                                  "cs0_cs1_cs2_cs3", buf))
 636                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
 637                 else
 638                         printf("hwconfig has unrecognized parameter for bank_intlv.\n");
 639                 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 640                 case FSL_DDR_CS0_CS1_CS2_CS3:
 641 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 642                         if (pdimm[0].n_ranks < 4) {
 643                                 popts->ba_intlv_ctl = 0;
 644                                 printf("Not enough bank(chip-select) for "
 645                                         "CS0+CS1+CS2+CS3 on controller %d, "
 646                                         "force non-interleaving!\n", ctrl_num);
 647                         }
 648 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 649                         if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
 650                                 popts->ba_intlv_ctl = 0;
 651                                 printf("Not enough bank(chip-select) for "
 652                                         "CS0+CS1+CS2+CS3 on controller %d, "
 653                                         "force non-interleaving!\n", ctrl_num);
 654                         }
 655                         if (pdimm[0].capacity != pdimm[1].capacity) {
 656                                 popts->ba_intlv_ctl = 0;
 657                                 printf("Not identical DIMM size for "
 658                                         "CS0+CS1+CS2+CS3 on controller %d, "
 659                                         "force non-interleaving!\n", ctrl_num);
 660                         }
 661 #endif
 662                         break;
 663                 case FSL_DDR_CS0_CS1:
 664                         if (pdimm[0].n_ranks < 2) {
 665                                 popts->ba_intlv_ctl = 0;
 666                                 printf("Not enough bank(chip-select) for "
 667                                         "CS0+CS1 on controller %d, "
 668                                         "force non-interleaving!\n", ctrl_num);
 669                         }
 670                         break;
 671                 case FSL_DDR_CS2_CS3:
 672 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 673                         if (pdimm[0].n_ranks < 4) {
 674                                 popts->ba_intlv_ctl = 0;
 675                                 printf("Not enough bank(chip-select) for CS2+CS3 "
 676                                         "on controller %d, force non-interleaving!\n", ctrl_num);
 677                         }
 678 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 679                         if (pdimm[1].n_ranks < 2) {
 680                                 popts->ba_intlv_ctl = 0;
 681                                 printf("Not enough bank(chip-select) for CS2+CS3 "
 682                                         "on controller %d, force non-interleaving!\n", ctrl_num);
 683                         }
 684 #endif
 685                         break;
 686                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 687 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 688                         if (pdimm[0].n_ranks < 4) {
 689                                 popts->ba_intlv_ctl = 0;
 690                                 printf("Not enough bank(CS) for CS0+CS1 and "
 691                                         "CS2+CS3 on controller %d, "
 692                                         "force non-interleaving!\n", ctrl_num);
 693                         }
 694 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 695                         if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
 696                                 popts->ba_intlv_ctl = 0;
 697                                 printf("Not enough bank(CS) for CS0+CS1 and "
 698                                         "CS2+CS3 on controller %d, "
 699                                         "force non-interleaving!\n", ctrl_num);
 700                         }
 701 #endif
 702                         break;
 703                 default:
 704                         popts->ba_intlv_ctl = 0;
 705                         break;
 706                 }
 707         }
 708
 709         if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
 710                 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
 711                         popts->addr_hash = 0;
 712                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
 713                                                "true", buf))
 714                         popts->addr_hash = 1;
 715         }
 716
 717         if (pdimm[0].n_ranks == 4)
 718                 popts->quad_rank_present = 1;
 719
 720         ddr_freq = get_ddr_freq(0) / 1000000;
 721         if (popts->registered_dimm_en) {
 722                 popts->rcw_override = 1;
 723                 popts->rcw_1 = 0x000a5a00;
 724                 if (ddr_freq <= 800)
 725                         popts->rcw_2 = 0x00000000;
 726                 else if (ddr_freq <= 1066)
 727                         popts->rcw_2 = 0x00100000;
 728                 else if (ddr_freq <= 1333)
 729                         popts->rcw_2 = 0x00200000;
 730                 else
 731                         popts->rcw_2 = 0x00300000;
 732         }
 733
 734         fsl_ddr_board_options(popts, pdimm, ctrl_num);
 735
 736         return 0;
 737 }
 738
 739 void check_interleaving_options(fsl_ddr_info_t *pinfo)
 740 {
 741         int i, j, check_n_ranks, intlv_fixed = 0;
 742         unsigned long long check_rank_density;
 743         /*
 744          * Check if all controllers are configured for memory
 745          * controller interleaving. Identical dimms are recommended. At least
 746          * the size should be checked.
 747          */
 748         j = 0;
 749         check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
 750         check_rank_density = pinfo->dimm_params[0][0].rank_density;
 751         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 752                 if ((pinfo->memctl_opts[i].memctl_interleaving) && \
 753                     (check_rank_density == pinfo->dimm_params[i][0].rank_density) && \
 754                     (check_n_ranks == pinfo->dimm_params[i][0].n_ranks)) {
 755                         j++;
 756                 }
 757         }
 758         if (j != CONFIG_NUM_DDR_CONTROLLERS) {
 759                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 760                         if (pinfo->memctl_opts[i].memctl_interleaving) {
 761                                 pinfo->memctl_opts[i].memctl_interleaving = 0;
 762                                 intlv_fixed = 1;
 763                         }
 764                 if (intlv_fixed)
 765                         printf("Not all DIMMs are identical in size. "
 766                                 "Memory controller interleaving disabled.\n");
 767         }
 768 }
 769
 770 int fsl_use_spd(void)
 771 {
 772         int use_spd = 0;
 773
 774 #ifdef CONFIG_DDR_SPD
 775         char buffer[HWCONFIG_BUFFER_SIZE];
 776         char *buf = NULL;
 777
 778         /*
 779          * Extract hwconfig from environment since we have not properly setup
 780          * the environment but need it for ddr config params
 781          */
 782         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 783                 buf = buffer;
 784
 785         /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
 786         if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
 787                 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
 788                         use_spd = 1;
 789                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
 790                                                "fixed", buf))
 791                         use_spd = 0;
 792                 else
 793                         use_spd = 1;
 794         } else
 795                 use_spd = 1;
 796 #endif
 797
 798         return use_spd;
 799 }