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powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation
[u-boot] / arch / powerpc / cpu / mpc8xxx / ddr / util.c
1 /*
2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8
9 #include <common.h>
10 #include <asm/fsl_law.h>
11 #include <div64.h>
12
13 #include "ddr.h"
14
15 /* To avoid 64-bit full-divides, we factor this here */
16 #define ULL_2E12 2000000000000ULL
17 #define UL_5POW12 244140625UL
18 #define UL_2POW13 (1UL << 13)
19
20 #define ULL_8FS 0xFFFFFFFFULL
21
22 /*
23  * Round up mclk_ps to nearest 1 ps in memory controller code
24  * if the error is 0.5ps or more.
25  *
26  * If an imprecise data rate is too high due to rounding error
27  * propagation, compute a suitably rounded mclk_ps to compute
28  * a working memory controller configuration.
29  */
30 unsigned int get_memory_clk_period_ps(void)
31 {
32         unsigned int data_rate = get_ddr_freq(0);
33         unsigned int result;
34
35         /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
36         unsigned long long rem, mclk_ps = ULL_2E12;
37
38         /* Now perform the big divide, the result fits in 32-bits */
39         rem = do_div(mclk_ps, data_rate);
40         result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
41
42         return result;
43 }
44
45 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
46 unsigned int picos_to_mclk(unsigned int picos)
47 {
48         unsigned long long clks, clks_rem;
49         unsigned long data_rate = get_ddr_freq(0);
50
51         /* Short circuit for zero picos */
52         if (!picos)
53                 return 0;
54
55         /* First multiply the time by the data rate (32x32 => 64) */
56         clks = picos * (unsigned long long)data_rate;
57         /*
58          * Now divide by 5^12 and track the 32-bit remainder, then divide
59          * by 2*(2^12) using shifts (and updating the remainder).
60          */
61         clks_rem = do_div(clks, UL_5POW12);
62         clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
63         clks >>= 13;
64
65         /* If we had a remainder greater than the 1ps error, then round up */
66         if (clks_rem > data_rate)
67                 clks++;
68
69         /* Clamp to the maximum representable value */
70         if (clks > ULL_8FS)
71                 clks = ULL_8FS;
72         return (unsigned int) clks;
73 }
74
75 unsigned int mclk_to_picos(unsigned int mclk)
76 {
77         return get_memory_clk_period_ps() * mclk;
78 }
79
80 void
81 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
82                            unsigned int law_memctl,
83                            unsigned int ctrl_num)
84 {
85         unsigned long long base = memctl_common_params->base_address;
86         unsigned long long size = memctl_common_params->total_mem;
87
88         /*
89          * If no DIMMs on this controller, do not proceed any further.
90          */
91         if (!memctl_common_params->ndimms_present) {
92                 return;
93         }
94
95 #if !defined(CONFIG_PHYS_64BIT)
96         if (base >= CONFIG_MAX_MEM_MAPPED)
97                 return;
98         if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
99                 size = CONFIG_MAX_MEM_MAPPED - base;
100 #endif
101         if (set_ddr_laws(base, size, law_memctl) < 0) {
102                 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
103                         law_memctl);
104                 return ;
105         }
106         debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
107                 base, size, law_memctl);
108 }
109
110 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
111 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
112                          unsigned int memctl_interleaved,
113                          unsigned int ctrl_num);
114
115 void fsl_ddr_set_intl3r(const unsigned int granule_size)
116 {
117 #ifdef CONFIG_E6500
118         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
119         *mcintl3r = 0x80000000 | (granule_size & 0x1f);
120         debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
121 #endif
122 }
123
124 void board_add_ram_info(int use_default)
125 {
126 #if defined(CONFIG_MPC83xx)
127         immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
128         ccsr_ddr_t *ddr = (void *)&immap->ddr;
129 #elif defined(CONFIG_MPC85xx)
130         ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
131 #elif defined(CONFIG_MPC86xx)
132         ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
133 #endif
134 #if     defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
135         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
136 #endif
137 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
138         uint32_t cs0_config = in_be32(&ddr->cs0_config);
139 #endif
140         uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
141         int cas_lat;
142
143 #if CONFIG_NUM_DDR_CONTROLLERS >= 2
144         if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
145                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
146                 sdram_cfg = in_be32(&ddr->sdram_cfg);
147         }
148 #endif
149 #if CONFIG_NUM_DDR_CONTROLLERS >= 3
150         if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
151                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
152                 sdram_cfg = in_be32(&ddr->sdram_cfg);
153         }
154 #endif
155         puts(" (DDR");
156         switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
157                 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
158         case SDRAM_TYPE_DDR1:
159                 puts("1");
160                 break;
161         case SDRAM_TYPE_DDR2:
162                 puts("2");
163                 break;
164         case SDRAM_TYPE_DDR3:
165                 puts("3");
166                 break;
167         default:
168                 puts("?");
169                 break;
170         }
171
172         if (sdram_cfg & SDRAM_CFG_32_BE)
173                 puts(", 32-bit");
174         else if (sdram_cfg & SDRAM_CFG_16_BE)
175                 puts(", 16-bit");
176         else
177                 puts(", 64-bit");
178
179         /* Calculate CAS latency based on timing cfg values */
180         cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
181         if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
182                 cas_lat += (8 << 1);
183         printf(", CL=%d", cas_lat >> 1);
184         if (cas_lat & 0x1)
185                 puts(".5");
186
187         if (sdram_cfg & SDRAM_CFG_ECC_EN)
188                 puts(", ECC on)");
189         else
190                 puts(", ECC off)");
191
192 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
193 #ifdef CONFIG_E6500
194         if (*mcintl3r & 0x80000000) {
195                 puts("\n");
196                 puts("       DDR Controller Interleaving Mode: ");
197                 switch (*mcintl3r & 0x1f) {
198                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
199                         puts("3-way 1KB");
200                         break;
201                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
202                         puts("3-way 4KB");
203                         break;
204                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
205                         puts("3-way 8KB");
206                         break;
207                 default:
208                         puts("3-way UNKNOWN");
209                         break;
210                 }
211         }
212 #endif
213 #endif
214 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
215         if (cs0_config & 0x20000000) {
216                 puts("\n");
217                 puts("       DDR Controller Interleaving Mode: ");
218
219                 switch ((cs0_config >> 24) & 0xf) {
220                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
221                         puts("cache line");
222                         break;
223                 case FSL_DDR_PAGE_INTERLEAVING:
224                         puts("page");
225                         break;
226                 case FSL_DDR_BANK_INTERLEAVING:
227                         puts("bank");
228                         break;
229                 case FSL_DDR_SUPERBANK_INTERLEAVING:
230                         puts("super-bank");
231                         break;
232                 default:
233                         puts("invalid");
234                         break;
235                 }
236         }
237 #endif
238
239         if ((sdram_cfg >> 8) & 0x7f) {
240                 puts("\n");
241                 puts("       DDR Chip-Select Interleaving Mode: ");
242                 switch(sdram_cfg >> 8 & 0x7f) {
243                 case FSL_DDR_CS0_CS1_CS2_CS3:
244                         puts("CS0+CS1+CS2+CS3");
245                         break;
246                 case FSL_DDR_CS0_CS1:
247                         puts("CS0+CS1");
248                         break;
249                 case FSL_DDR_CS2_CS3:
250                         puts("CS2+CS3");
251                         break;
252                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
253                         puts("CS0+CS1 and CS2+CS3");
254                         break;
255                 default:
256                         puts("invalid");
257                         break;
258                 }
259         }
260 }