2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
12 #include <asm/fsl_law.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
19 #ifdef CONFIG_FSL_CORENET
20 #define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
21 #define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
22 #define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
23 #define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
24 #define LAWBAR_SHIFT 0
26 #define LAW_BASE (CONFIG_SYS_IMMR + 0xc08)
27 #define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x + 2)
28 #define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x)
29 #define LAWBAR_SHIFT 12
33 static inline phys_addr_t get_law_base_addr(int idx)
35 #ifdef CONFIG_FSL_CORENET
37 ((u64)in_be32(LAWBARH_ADDR(idx)) << 32) |
38 in_be32(LAWBARL_ADDR(idx));
40 return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT;
44 static inline void set_law_base_addr(int idx, phys_addr_t addr)
46 #ifdef CONFIG_FSL_CORENET
47 out_be32(LAWBARL_ADDR(idx), addr & 0xffffffff);
48 out_be32(LAWBARH_ADDR(idx), (u64)addr >> 32);
50 out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT);
54 void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
56 gd->arch.used_laws |= (1 << idx);
58 out_be32(LAWAR_ADDR(idx), 0);
59 set_law_base_addr(idx, addr);
60 out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz);
62 /* Read back so that we sync the writes */
63 in_be32(LAWAR_ADDR(idx));
66 void disable_law(u8 idx)
68 gd->arch.used_laws &= ~(1 << idx);
70 out_be32(LAWAR_ADDR(idx), 0);
71 set_law_base_addr(idx, 0);
73 /* Read back so that we sync the writes */
74 in_be32(LAWAR_ADDR(idx));
79 #if !defined(CONFIG_NAND_SPL) && \
80 (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
81 static int get_law_entry(u8 i, struct law_entry *e)
85 lawar = in_be32(LAWAR_ADDR(i));
87 if (!(lawar & LAW_EN))
90 e->addr = get_law_base_addr(i);
91 e->size = lawar & 0x3f;
92 e->trgt_id = (lawar >> 20) & 0xff;
98 int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
100 u32 idx = ffz(gd->arch.used_laws);
102 if (idx >= FSL_HW_NUM_LAWS)
105 set_law(idx, addr, sz, id);
110 #if !defined(CONFIG_NAND_SPL) && \
111 (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
112 int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
116 /* we have no LAWs free */
117 if (gd->arch.used_laws == -1)
120 /* grab the last free law */
121 idx = __ilog2(~(gd->arch.used_laws));
123 if (idx >= FSL_HW_NUM_LAWS)
126 set_law(idx, addr, sz, id);
131 struct law_entry find_law(phys_addr_t addr)
133 struct law_entry entry;
141 for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
144 if (!get_law_entry(i, &entry))
147 upper = entry.addr + (2ull << entry.size);
148 if ((addr >= entry.addr) && (addr < upper)) {
157 void print_laws(void)
162 printf("\nLocal Access Window Configuration\n");
163 for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
164 lawar = in_be32(LAWAR_ADDR(i));
165 #ifdef CONFIG_FSL_CORENET
166 printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x",
167 i, in_be32(LAWBARH_ADDR(i)),
168 i, in_be32(LAWBARL_ADDR(i)));
170 printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i)));
172 printf(" LAWAR%02d: 0x%08x\n", i, lawar);
173 printf("\t(EN: %d TGT: 0x%02x SIZE: ",
174 (lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff);
175 print_size(lawar_size(lawar), ")\n");
181 /* use up to 2 LAWs for DDR, used the last available LAWs */
182 int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
184 u64 start_align, law_sz;
188 start_align = 1ull << (LAW_SIZE_32G + 1);
190 start_align = 1ull << (ffs64(start) - 1);
191 law_sz = min(start_align, sz);
192 law_sz_enc = __ilog2_u64(law_sz) - 1;
194 if (set_last_law(start, law_sz_enc, id) < 0)
197 /* recalculate size based on what was actually covered by the law */
198 law_sz = 1ull << __ilog2_u64(law_sz);
200 /* do we still have anything to map */
205 start_align = 1ull << (ffs64(start) - 1);
206 law_sz = min(start_align, sz);
207 law_sz_enc = __ilog2_u64(law_sz) - 1;
209 if (set_last_law(start, law_sz_enc, id) < 0)
215 /* do we still have anything to map */
224 void disable_non_ddr_laws(void)
228 for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
229 u32 lawar = in_be32(LAWAR_ADDR(i));
231 if (lawar & LAW_EN) {
232 id = (lawar & ~LAW_EN) >> 20;
234 case LAW_TRGT_IF_DDR_1:
235 case LAW_TRGT_IF_DDR_2:
236 case LAW_TRGT_IF_DDR_3:
237 case LAW_TRGT_IF_DDR_4:
238 case LAW_TRGT_IF_DDR_INTRLV:
239 case LAW_TRGT_IF_DDR_INTLV_34:
240 case LAW_TRGT_IF_DDR_INTLV_123:
241 case LAW_TRGT_IF_DDR_INTLV_1234:
254 #if FSL_HW_NUM_LAWS < 32
255 gd->arch.used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
256 #elif FSL_HW_NUM_LAWS == 32
257 gd->arch.used_laws = 0;
259 #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
262 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500) && \
263 !defined(CONFIG_E500MC)
264 /* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms,
265 * which is not disabled before transferring the control to uboot.
266 * Disable the LAW 0 entry here.
271 #if !defined(CONFIG_SECURE_BOOT)
273 * if any non DDR LAWs has been created earlier, remove them before
274 * LAW table is parsed.
276 disable_non_ddr_laws();
280 * Any LAWs that were set up before we booted assume they are meant to
281 * be around and mark them used.
283 for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
284 u32 lawar = in_be32(LAWAR_ADDR(i));
287 gd->arch.used_laws |= (1 << i);
290 for (i = 0; i < num_law_entries; i++) {
291 if (law_table[i].index == -1)
292 set_next_law(law_table[i].addr, law_table[i].size,
293 law_table[i].trgt_id);
295 set_law(law_table[i].index, law_table[i].addr,
296 law_table[i].size, law_table[i].trgt_id);
299 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
300 /* check RCW to get which port is used for boot */
301 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
302 u32 bootloc = in_be32(&gur->rcwsr[6]);
304 * in SRIO or PCIE boot we need to set specail LAWs for
305 * SRIO or PCIE interfaces.
307 switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
308 case 0x0: /* boot from PCIE1 */
309 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
312 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
316 case 0x1: /* boot from PCIE2 */
317 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
320 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
324 case 0x2: /* boot from PCIE3 */
325 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
328 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
332 case 0x8: /* boot from SRIO1 */
333 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
336 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
340 case 0x9: /* boot from SRIO2 */
341 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
344 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,