2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <asm/fsl_law.h>
23 #include <asm/fsl_serdes.h>
24 #include <asm/fsl_srio.h>
25 #include <asm/errno.h>
27 #define SRIO_PORT_ACCEPT_ALL 0x10000001
28 #define SRIO_IB_ATMU_AR 0x80f55000
29 #define SRIO_OB_ATMU_AR_MAINT 0x80077000
30 #define SRIO_OB_ATMU_AR_RW 0x80045000
31 #define SRIO_LCSBA1CSR_OFFSET 0x5c
32 #define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
33 #define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
34 #define SRIO_LCSBA1CSR 0x60000000
36 #if defined(CONFIG_FSL_CORENET)
37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
38 #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
39 #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
41 #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
42 #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
44 #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
45 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
46 #elif defined(CONFIG_MPC85xx)
47 #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
48 #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
49 #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
50 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
51 #elif defined(CONFIG_MPC86xx)
52 #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
53 #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
54 #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG
55 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
56 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
58 #error "No defines for DEVDISR_SRIO"
61 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
65 * Description: During port initialization, the SRIO port performs
66 * lane synchronization (detecting valid symbols on a lane) and
67 * lane alignment (coordinating multiple lanes to receive valid data
68 * across lanes). Internal errors in lane synchronization and lane
69 * alignment may cause failure to achieve link initialization at
70 * the configured port width.
71 * An SRIO port configured as a 4x port may see one of these scenarios:
72 * 1. One or more lanes fails to achieve lane synchronization. Depending
73 * on which lanes fail, this may result in downtraining from 4x to 1x
74 * on lane 0, 4x to 1x on lane R (redundant lane).
75 * 2. The link may fail to achieve lane alignment as a 4x, even though
76 * all 4 lanes achieve lane synchronization, and downtrain to a 1x.
77 * An SRIO port configured as a 1x port may fail to complete port
78 * initialization (PnESCSR[PU] never deasserts) because of scenario 1.
79 * Impact: SRIO port may downtrain to 1x, or may fail to complete
80 * link initialization. Once a port completes link initialization
81 * successfully, it will operate normally.
83 static int srio_erratum_a004034(u8 port)
85 serdes_corenet_t *srds_regs;
90 unsigned long long end_tick;
91 struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
93 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
94 conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
95 >> (12 - port * 4)) & 0x3;
96 init_lane = (in_be32((void *)&srio_regs->lp_serial
97 .port[port].pccsr) >> 27) & 0x7;
100 * Start a counter set to ~2 ms after the SERDES reset is
101 * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n
102 * corresponding to the SERDES bank/PLL for the SRIO port).
104 if (in_be32((void *)&srds_regs->bank[0].rstctl)
105 & SRDS_RSTCTL_RSTDONE) {
107 * Poll the port uninitialized status (SRIO PnESCSR[PO]) until
108 * PO=1 or the counter expires. If the counter expires, the
109 * port has failed initialization: go to recover steps. If PO=1
110 * and the desired port width is 1x, go to normal steps. If
111 * PO = 1 and the desired port width is 4x, go to recover steps.
113 end_tick = usec2ticks(2000) + get_ticks();
115 if (in_be32((void *)&srio_regs->lp_serial
116 .port[port].pescsr) & 0x2) {
117 if (conf_lane == 0x1)
120 if (init_lane == 0x2)
126 } while (end_tick > get_ticks());
128 /* recover at most 3 times */
129 for (i = 0; i < 3; i++) {
130 /* Set SRIO PnCCSR[PD]=1 */
131 setbits_be32((void *)&srio_regs->lp_serial
135 * Set SRIO PnPCR[OBDEN] on the host to
136 * enable the discarding of any pending packets.
138 setbits_be32((void *)&srio_regs->impl.port[port].pcr,
142 /* Run sync command */
146 first = serdes_get_first_lane(SRIO2);
148 first = serdes_get_first_lane(SRIO1);
149 if (unlikely(first < 0))
151 if (conf_lane == 0x1)
156 * Set SERDES BnGCRm0[RRST]=0 for each SRIO
159 for (idx = first; idx <= last; idx++)
160 clrbits_be32(&srds_regs->lane[idx].gcr0,
163 * Read SERDES BnGCRm0 for each SRIO
166 for (idx = first; idx <= last; idx++)
167 in_be32(&srds_regs->lane[idx].gcr0);
168 /* Run sync command */
173 * Set SERDES BnGCRm0[RRST]=1 for each SRIO
176 for (idx = first; idx <= last; idx++)
177 setbits_be32(&srds_regs->lane[idx].gcr0,
180 * Read SERDES BnGCRm0 for each SRIO
183 for (idx = first; idx <= last; idx++)
184 in_be32(&srds_regs->lane[idx].gcr0);
185 /* Run sync command */
190 /* Write 1 to clear all bits in SRIO PnSLCSR */
191 out_be32((void *)&srio_regs->impl.port[port].slcsr,
193 /* Clear SRIO PnPCR[OBDEN] on the host */
194 clrbits_be32((void *)&srio_regs->impl.port[port].pcr,
196 /* Set SRIO PnCCSR[PD]=0 */
197 clrbits_be32((void *)&srio_regs->lp_serial
202 /* Poll the state of the port again */
204 (in_be32((void *)&srio_regs->lp_serial
205 .port[port].pccsr) >> 27) & 0x7;
206 if (in_be32((void *)&srio_regs->lp_serial
207 .port[port].pescsr) & 0x2) {
208 if (conf_lane == 0x1)
211 if (init_lane == 0x2)
222 /* Poll PnESCSR[OES] on the host until it is clear */
223 end_tick = usec2ticks(1000000) + get_ticks();
225 if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr)
227 out_be32(((void *)&srio_regs->lp_serial
228 .port[port].pescsr), 0xffffffff);
229 out_be32(((void *)&srio_regs->phys_err
230 .port[port].edcsr), 0);
231 out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0);
234 } while (end_tick > get_ticks());
242 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
243 int srio1_used = 0, srio2_used = 0;
246 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
247 devdisr = &gur->devdisr3;
249 devdisr = &gur->devdisr;
251 if (is_serdes_configured(SRIO1)) {
252 set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
253 law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
256 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
257 if (srio_erratum_a004034(0) < 0)
258 printf("SRIO1: enabled but port error\n");
261 printf("SRIO1: enabled\n");
263 printf("SRIO1: disabled\n");
267 if (is_serdes_configured(SRIO2)) {
268 set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
269 law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
272 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
273 if (srio_erratum_a004034(1) < 0)
274 printf("SRIO2: enabled but port error\n");
277 printf("SRIO2: enabled\n");
280 printf("SRIO2: disabled\n");
284 #ifdef CONFIG_FSL_CORENET
285 /* On FSL_CORENET devices we can disable individual ports */
287 setbits_be32(devdisr, _DEVDISR_SRIO1);
289 setbits_be32(devdisr, _DEVDISR_SRIO2);
292 /* neither port is used - disable everything */
293 if (!srio1_used && !srio2_used) {
294 setbits_be32(devdisr, _DEVDISR_SRIO1);
295 setbits_be32(devdisr, _DEVDISR_SRIO2);
296 setbits_be32(devdisr, _DEVDISR_RMU);
300 #ifdef CONFIG_FSL_CORENET
301 void srio_boot_master(int port)
303 struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
305 /* set port accept-all */
306 out_be32((void *)&srio->impl.port[port - 1].ptaacr,
307 SRIO_PORT_ACCEPT_ALL);
309 debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port);
310 /* configure inbound window for slave's u-boot image */
311 debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
312 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
313 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
314 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
315 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
316 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
317 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
318 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
319 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
320 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
322 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
324 /* configure inbound window for slave's u-boot image */
325 debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
326 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
327 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
328 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
329 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
330 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
331 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
332 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
333 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
334 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
336 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
338 /* configure inbound window for slave's ucode and ENV */
339 debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
340 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
341 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
342 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
343 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
344 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar,
345 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
346 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar,
347 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
348 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar,
350 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
353 void srio_boot_master_release_slave(int port)
355 struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
357 debug("SRIOBOOT - MASTER: "
358 "Check the port status and release slave core ...\n");
360 escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr);
362 if (escsr & 0x10100) {
363 debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
366 debug("SRIOBOOT - MASTER: "
367 "Port [ %d ] is ready, now release slave's core ...\n",
370 * configure outbound window
371 * with maintenance attribute to set slave's LCSBA1CSR
373 out_be32((void *)&srio->atmu.port[port - 1]
374 .outbw[1].rowtar, 0);
375 out_be32((void *)&srio->atmu.port[port - 1]
376 .outbw[1].rowtear, 0);
378 out_be32((void *)&srio->atmu.port[port - 1]
380 CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
382 out_be32((void *)&srio->atmu.port[port - 1]
384 CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
385 out_be32((void *)&srio->atmu.port[port - 1]
387 SRIO_OB_ATMU_AR_MAINT
388 | atmu_size_mask(SRIO_MAINT_WIN_SIZE));
391 * configure outbound window
392 * with R/W attribute to set slave's BRR
394 out_be32((void *)&srio->atmu.port[port - 1]
396 SRIO_LCSBA1CSR >> 9);
397 out_be32((void *)&srio->atmu.port[port - 1]
398 .outbw[2].rowtear, 0);
400 out_be32((void *)&srio->atmu.port[port - 1]
402 (CONFIG_SYS_SRIO2_MEM_PHYS
403 + SRIO_MAINT_WIN_SIZE) >> 12);
405 out_be32((void *)&srio->atmu.port[port - 1]
407 (CONFIG_SYS_SRIO1_MEM_PHYS
408 + SRIO_MAINT_WIN_SIZE) >> 12);
409 out_be32((void *)&srio->atmu.port[port - 1]
412 | atmu_size_mask(SRIO_RW_WIN_SIZE));
415 * Set the LCSBA1CSR register in slave
416 * by the maint-outbound window
419 out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
420 + SRIO_LCSBA1CSR_OFFSET,
422 while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
423 + SRIO_LCSBA1CSR_OFFSET)
427 * And then set the BRR register
428 * to release slave core
430 out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
431 + SRIO_MAINT_WIN_SIZE
432 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
433 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
435 out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
436 + SRIO_LCSBA1CSR_OFFSET,
438 while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
439 + SRIO_LCSBA1CSR_OFFSET)
443 * And then set the BRR register
444 * to release slave core
446 out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
447 + SRIO_MAINT_WIN_SIZE
448 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
449 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
451 debug("SRIOBOOT - MASTER: "
452 "Release slave successfully! Now the slave should start up!\n");
455 debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", port);