2 * (C) Copyright 2006 - 2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 /* define DEBUG for debugging output (obviously ;-)) */
30 #include <asm/ppc4xx.h>
31 #include <asm/processor.h>
33 #include <asm/errno.h>
35 #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
36 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
37 defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE)
39 #include <asm/4xx_pcie.h>
43 PTYPE_LEGACY_ENDPOINT = 0x1,
44 PTYPE_ROOT_PORT = 0x4,
51 static struct pci_controller pcie_hose[CONFIG_SYS_PCIE_NR_PORTS];
54 * Per default, all cards are present, so we need to check if the
57 int __board_pcie_card_present(int port)
61 int board_pcie_card_present(int port)
62 __attribute__((weak, alias("__board_pcie_card_present")));
65 * Some boards have runtime detection of the first and last PCIe
66 * slot used, so let's provide weak default functions for the
69 int __board_pcie_first(void)
73 int board_pcie_first(void)
74 __attribute__((weak, alias("__board_pcie_first")));
76 int __board_pcie_last(void)
78 return CONFIG_SYS_PCIE_NR_PORTS - 1;
80 int board_pcie_last(void)
81 __attribute__((weak, alias("__board_pcie_last")));
83 void __board_pcie_setup_port(int port, int rootpoint)
85 /* noting in this weak default implementation */
87 void board_pcie_setup_port(int port, int rootpoint)
88 __attribute__((weak, alias("__board_pcie_setup_port")));
90 void pcie_setup_hoses(int busno)
92 struct pci_controller *hose;
97 int first = board_pcie_first();
98 int last = board_pcie_last();
101 * Assume we're called after the PCI(X) hose(s) are initialized,
102 * which takes bus ID 0... and therefore start numbering PCIe's
103 * from the next number.
107 for (i = first; i <= last; i++) {
109 * Some boards (e.g. Katmai) can detects via hardware
110 * if a PCIe card is plugged, so let's check this.
112 if (!board_pcie_card_present(i))
115 if (is_end_point(i)) {
116 board_pcie_setup_port(i, 0);
117 ret = ppc4xx_init_pcie_endport(i);
119 board_pcie_setup_port(i, 1);
120 ret = ppc4xx_init_pcie_rootport(i);
125 printf("PCIE%d: initialization as %s failed\n", i,
126 is_end_point(i) ? "endpoint" : "root-complex");
130 hose = &pcie_hose[i];
131 hose->first_busno = bus;
132 hose->last_busno = bus;
133 hose->current_busno = bus;
135 /* setup mem resource */
136 pci_set_region(hose->regions + 0,
137 CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
138 CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
139 CONFIG_SYS_PCIE_MEMSIZE,
141 hose->region_count = 1;
142 pci_register_hose(hose);
144 if (is_end_point(i)) {
145 ppc4xx_setup_pcie_endpoint(hose, i);
147 * Reson for no scanning is endpoint can not generate
148 * upstream configuration accesses.
151 ppc4xx_setup_pcie_rootpoint(hose, i);
152 env = getenv ("pciscandelay");
154 delay = simple_strtoul(env, NULL, 10);
156 printf("Warning, expect noticable delay before "
157 "PCIe scan due to 'pciscandelay' value!\n");
158 mdelay(delay * 1000);
162 * Config access can only go down stream
164 hose->last_busno = pci_hose_scan(hose);
165 bus = hose->last_busno + 1;
170 static int validate_endpoint(struct pci_controller *hose)
172 if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE)
173 return (is_end_point(0));
174 else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE)
175 return (is_end_point(1));
176 #if CONFIG_SYS_PCIE_NR_PORTS > 2
177 else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE)
178 return (is_end_point(2));
184 static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
186 u8 *base = (u8*)hose->cfg_data;
188 /* use local configuration space for the first bus */
189 if (PCI_BUS(devfn) == 0) {
190 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE)
191 base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE;
192 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE)
193 base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE;
194 #if CONFIG_SYS_PCIE_NR_PORTS > 2
195 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE)
196 base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE;
203 static void pcie_dmer_disable(void)
205 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
206 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
207 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
208 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
209 #if CONFIG_SYS_PCIE_NR_PORTS > 2
210 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
211 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
215 static void pcie_dmer_enable(void)
217 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
218 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
219 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
220 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
221 #if CONFIG_SYS_PCIE_NR_PORTS > 2
222 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
223 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
227 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
228 int offset, int len, u32 *val) {
232 if (validate_endpoint(hose))
233 return 0; /* No upstream config access */
236 * Bus numbers are relative to hose->first_busno
238 devfn -= PCI_BDF(hose->first_busno, 0, 0);
241 * NOTICE: configuration space ranges are currenlty mapped only for
242 * the first 16 buses, so such limit must be imposed. In case more
243 * buses are required the TLB settings in board/amcc/<board>/init.S
244 * need to be altered accordingly (one bus takes 1 MB of memory space).
246 if (PCI_BUS(devfn) >= 16)
250 * Only single device/single function is supported for the primary and
251 * secondary buses of the 440SPe host bridge.
253 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
254 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
257 pcie_get_base(hose, devfn);
258 offset += devfn << 4;
261 * Reading from configuration space of non-existing device can
262 * generate transaction errors. For the read duration we suppress
263 * assertion of machine check exceptions to avoid those.
265 pcie_dmer_disable ();
267 debug("%s: cfg_data=%p offset=%08x\n", __func__,
268 hose->cfg_data, offset);
271 *val = in_8(hose->cfg_data + offset);
274 *val = in_le16((u16 *)(hose->cfg_data + offset));
277 *val = in_le32((u32*)(hose->cfg_data + offset));
286 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
287 int offset, int len, u32 val) {
289 if (validate_endpoint(hose))
290 return 0; /* No upstream config access */
293 * Bus numbers are relative to hose->first_busno
295 devfn -= PCI_BDF(hose->first_busno, 0, 0);
298 * Same constraints as in pcie_read_config().
300 if (PCI_BUS(devfn) >= 16)
303 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
304 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
307 pcie_get_base(hose, devfn);
308 offset += devfn << 4;
311 * Suppress MCK exceptions, similar to pcie_read_config()
313 pcie_dmer_disable ();
317 out_8(hose->cfg_data + offset, val);
320 out_le16((u16 *)(hose->cfg_data + offset), val);
323 out_le32((u32 *)(hose->cfg_data + offset), val);
332 int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
337 rv = pcie_read_config(hose, dev, offset, 1, &v);
342 int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
347 rv = pcie_read_config(hose, dev, offset, 2, &v);
352 int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
357 rv = pcie_read_config(hose, dev, offset, 3, &v);
362 int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
364 return pcie_write_config(hose,(u32)dev,offset,1,val);
367 int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
369 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
372 int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
374 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
377 #if defined(CONFIG_440SPE)
378 static void ppc4xx_setup_utl(u32 port) {
380 volatile void *utl_base = NULL;
387 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
388 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
389 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
390 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
394 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
395 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
396 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
397 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
401 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
402 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
403 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
404 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
407 utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
410 * Set buffer allocations and then assert VRB and TXE.
412 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
413 out_be32(utl_base + PEUTL_INTR, 0x02000000);
414 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
415 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
416 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
417 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
418 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
419 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
422 static int check_error(void)
424 u32 valPE0, valPE1, valPE2;
427 /* SDR0_PEGPLLLCT1 reset */
428 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000))
429 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
431 valPE0 = SDR_READ(PESDR0_RCSSET);
432 valPE1 = SDR_READ(PESDR1_RCSSET);
433 valPE2 = SDR_READ(PESDR2_RCSSET);
435 /* SDR0_PExRCSSET rstgu */
436 if (!(valPE0 & 0x01000000) ||
437 !(valPE1 & 0x01000000) ||
438 !(valPE2 & 0x01000000)) {
439 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
443 /* SDR0_PExRCSSET rstdl */
444 if (!(valPE0 & 0x00010000) ||
445 !(valPE1 & 0x00010000) ||
446 !(valPE2 & 0x00010000)) {
447 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
451 /* SDR0_PExRCSSET rstpyn */
452 if ((valPE0 & 0x00001000) ||
453 (valPE1 & 0x00001000) ||
454 (valPE2 & 0x00001000)) {
455 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
459 /* SDR0_PExRCSSET hldplb */
460 if ((valPE0 & 0x10000000) ||
461 (valPE1 & 0x10000000) ||
462 (valPE2 & 0x10000000)) {
463 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
467 /* SDR0_PExRCSSET rdy */
468 if ((valPE0 & 0x00100000) ||
469 (valPE1 & 0x00100000) ||
470 (valPE2 & 0x00100000)) {
471 printf("PCIE: SDR0_PExRCSSET rdy error\n");
475 /* SDR0_PExRCSSET shutdown */
476 if ((valPE0 & 0x00000100) ||
477 (valPE1 & 0x00000100) ||
478 (valPE2 & 0x00000100)) {
479 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
486 * Initialize PCI Express core
488 int ppc4xx_init_pcie(void)
492 /* Set PLL clock receiver to LVPECL */
493 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
496 printf("ERROR: failed to set PCIe reference clock receiver --"
497 "PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1));
502 /* Did resistance calibration work? */
503 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) {
504 printf("ERROR: PCIe resistance calibration failed --"
505 "PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2));
509 /* De-assert reset of PCIe PLL, wait for lock */
510 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
511 udelay(300); /* 300 uS is maximum time lock should take */
514 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
516 udelay(20); /* Wait 20 uS more if needed */
521 printf("ERROR: PCIe PLL VCO output not locked to ref clock --"
522 "PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3));
530 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
531 static void ppc4xx_setup_utl(u32 port)
533 volatile void *utl_base = NULL;
536 * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK
540 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
541 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE));
542 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */
543 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
547 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
548 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)
550 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */
551 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
554 utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
557 * Set buffer allocations and then assert VRB and TXE.
559 out_be32(utl_base + PEUTL_PBCTL, 0x0800000c); /* PLBME, CRRE */
560 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
561 out_be32(utl_base + PEUTL_INTR, 0x02000000);
562 out_be32(utl_base + PEUTL_OPDBSZ, 0x04000000); /* OPD = 512 Bytes */
563 out_be32(utl_base + PEUTL_PBBSZ, 0x00000000); /* Max 512 Bytes */
564 out_be32(utl_base + PEUTL_IPHBSZ, 0x02000000);
565 out_be32(utl_base + PEUTL_IPDBSZ, 0x04000000); /* IPD = 512 Bytes */
566 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
567 out_be32(utl_base + PEUTL_PCTL, 0x80800066); /* VRB,TXE,timeout=default */
571 * TODO: double check PCI express SDR based on the latest user manual
572 * Some registers specified here no longer exist.. has to be
573 * updated based on the final EAS spec.
575 static int check_error(void)
580 valPE0 = SDR_READ(SDRN_PESDR_RCSSET(0));
581 valPE1 = SDR_READ(SDRN_PESDR_RCSSET(1));
583 /* SDR0_PExRCSSET rstgu */
584 if (!(valPE0 & PESDRx_RCSSET_RSTGU) || !(valPE1 & PESDRx_RCSSET_RSTGU)) {
585 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
589 /* SDR0_PExRCSSET rstdl */
590 if (!(valPE0 & PESDRx_RCSSET_RSTDL) || !(valPE1 & PESDRx_RCSSET_RSTDL)) {
591 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
595 /* SDR0_PExRCSSET rstpyn */
596 if ((valPE0 & PESDRx_RCSSET_RSTPYN) || (valPE1 & PESDRx_RCSSET_RSTPYN)) {
597 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
601 /* SDR0_PExRCSSET hldplb */
602 if ((valPE0 & PESDRx_RCSSET_HLDPLB) || (valPE1 & PESDRx_RCSSET_HLDPLB)) {
603 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
607 /* SDR0_PExRCSSET rdy */
608 if ((valPE0 & PESDRx_RCSSET_RDY) || (valPE1 & PESDRx_RCSSET_RDY)) {
609 printf("PCIE: SDR0_PExRCSSET rdy error\n");
617 * Initialize PCI Express core as described in User Manual
618 * TODO: double check PE SDR PLL Register with the updated user manual.
620 int ppc4xx_init_pcie(void)
627 #endif /* CONFIG_460EX */
629 #if defined(CONFIG_405EX)
630 static void ppc4xx_setup_utl(u32 port)
635 * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK
639 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
640 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE);
641 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
642 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
646 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
647 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE);
648 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
649 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
653 utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE;
656 * Set buffer allocations and then assert VRB and TXE.
658 out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000);
659 out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000);
660 out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000);
661 out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000);
662 out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000);
663 out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000);
664 out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000);
665 out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066);
667 out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c);
668 out_be32((u32 *)(utl_base + PEUTL_RCSTA),
669 in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000);
672 int ppc4xx_init_pcie(void)
675 * Nothing to do on 405EX
679 #endif /* CONFIG_405EX */
682 * Board-specific pcie initialization
683 * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed
687 * Initialize various parts of the PCI Express core for our port:
689 * - Set as a root port and enable max width
690 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
691 * - Set up UTL configuration.
692 * - Increase SERDES drive strength to levels suggested by AMCC.
693 * - De-assert RSTPYN, RSTDL and RSTGU.
695 * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it
696 * with default setting 0x11310000. The register has new fields,
697 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
700 #if defined(CONFIG_440SPE)
701 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
707 val = PTYPE_ROOT_PORT << 20;
708 utlset1 = 0x21222222;
710 val = PTYPE_LEGACY_ENDPOINT << 20;
711 utlset1 = 0x20222222;
715 val |= LNKW_X8 << 12;
717 val |= LNKW_X4 << 12;
719 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
720 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
721 if (!ppc440spe_revB())
722 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000);
723 SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000);
724 SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000);
725 SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000);
726 SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000);
728 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
729 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
730 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
731 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
733 SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) &
734 ~(1 << 24 | 1 << 16)) | 1 << 12);
738 #endif /* CONFIG_440SPE */
740 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
741 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
747 val = PTYPE_ROOT_PORT << 20;
749 val = PTYPE_LEGACY_ENDPOINT << 20;
752 val |= LNKW_X1 << 12;
753 utlset1 = 0x20000000;
755 val |= LNKW_X4 << 12;
756 utlset1 = 0x20101101;
759 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
760 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
761 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01210000);
765 SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230);
766 SDR_WRITE(PESDR0_L0DRV, 0x00000130);
767 SDR_WRITE(PESDR0_L0CLK, 0x00000006);
769 SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000);
773 SDR_WRITE(PESDR1_L0CDRCTL, 0x00003230);
774 SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230);
775 SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230);
776 SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230);
777 SDR_WRITE(PESDR1_L0DRV, 0x00000130);
778 SDR_WRITE(PESDR1_L1DRV, 0x00000130);
779 SDR_WRITE(PESDR1_L2DRV, 0x00000130);
780 SDR_WRITE(PESDR1_L3DRV, 0x00000130);
781 SDR_WRITE(PESDR1_L0CLK, 0x00000006);
782 SDR_WRITE(PESDR1_L1CLK, 0x00000006);
783 SDR_WRITE(PESDR1_L2CLK, 0x00000006);
784 SDR_WRITE(PESDR1_L3CLK, 0x00000006);
786 SDR_WRITE(PESDR1_PHY_CTL_RST,0x10000000);
790 SDR_WRITE(SDRN_PESDR_RCSSET(port), SDR_READ(SDRN_PESDR_RCSSET(port)) |
791 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
793 /* Poll for PHY reset */
796 while (!(SDR_READ(PESDR0_RSTSTA) & 0x1))
800 while (!(SDR_READ(PESDR1_RSTSTA) & 0x1))
805 SDR_WRITE(SDRN_PESDR_RCSSET(port),
806 (SDR_READ(SDRN_PESDR_RCSSET(port)) &
807 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
808 PESDRx_RCSSET_RSTPYN);
812 #endif /* CONFIG_440SPE */
814 #if defined(CONFIG_405EX)
815 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
824 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
825 SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000);
826 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000);
827 SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
828 SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
830 /* Assert the PE0_PHY reset */
831 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000);
834 /* deassert the PE0_hotreset */
835 if (is_end_point(port))
836 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000);
838 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
840 /* poll for phy !reset */
841 while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
844 /* deassert the PE0_gpl_utl_reset */
845 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000);
848 mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */
850 mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */
854 #endif /* CONFIG_405EX */
856 int ppc4xx_init_pcie_port_hw(int port, int rootport)
857 __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
860 * We map PCI Express configuration access into the 512MB regions
862 * NOTICE: revB is very strict about PLB real addressess and ranges to
863 * be mapped for config space; it seems to only work with d_nnnn_nnnn
864 * range (hangs the core upon config transaction attempts when set
865 * otherwise) while revA uses c_nnnn_nnnn.
868 * PCIE0: 0xc_4000_0000
869 * PCIE1: 0xc_8000_0000
870 * PCIE2: 0xc_c000_0000
873 * PCIE0: 0xd_0000_0000
874 * PCIE1: 0xd_2000_0000
875 * PCIE2: 0xd_4000_0000
882 * PCIE0: 0xd_0000_0000
883 * PCIE1: 0xd_2000_0000
885 static inline u64 ppc4xx_get_cfgaddr(int port)
887 #if defined(CONFIG_405EX)
889 return (u64)CONFIG_SYS_PCIE0_CFGBASE;
891 return (u64)CONFIG_SYS_PCIE1_CFGBASE;
893 #if defined(CONFIG_440SPE)
894 if (ppc440spe_revB()) {
896 default: /* to satisfy compiler */
898 return 0x0000000d00000000ULL;
900 return 0x0000000d20000000ULL;
902 return 0x0000000d40000000ULL;
906 default: /* to satisfy compiler */
908 return 0x0000000c40000000ULL;
910 return 0x0000000c80000000ULL;
912 return 0x0000000cc0000000ULL;
916 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
918 return 0x0000000d00000000ULL;
920 return 0x0000000d20000000ULL;
925 * 4xx boards as endpoint and root point setup
927 * testing inbound and out bound windows
929 * 4xx boards can be plugged into another 4xx boards or you can get PCI-E
930 * cable which can be used to setup loop back from one port to another port.
931 * Please rememeber that unless there is a endpoint plugged in to root port it
932 * will not initialize. It is the same in case of endpoint , unless there is
933 * root port attached it will not initialize.
935 * In this release of software all the PCI-E ports are configured as either
936 * endpoint or rootpoint.In future we will have support for selective ports
937 * setup as endpoint and root point in single board.
939 * Once your board came up as root point , you can verify by reading
940 * /proc/bus/pci/devices. Where you can see the configuration registers
941 * of endpoint device attached to the port.
943 * Enpoint cofiguration can be verified by connecting 4xx board to any
944 * host or another 4xx board. Then try to scan the device. In case of
945 * linux use "lspci" or appripriate os command.
947 * How do I verify the inbound and out bound windows ? (4xx to 4xx)
948 * in this configuration inbound and outbound windows are setup to access
949 * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
950 * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
951 * This is waere your POM(PLB out bound memory window) mapped. then
952 * read the data from other 4xx board's u-boot prompt at address
953 * 0x9000 0000(SRAM). Data should match.
954 * In case of inbound , write data to u-boot command prompt at 0xb000 0000
955 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
956 * data at 0x9000 0000(SRAM).Data should match.
958 int ppc4xx_init_pcie_port(int port, int rootport)
960 static int core_init;
961 volatile u32 val = 0;
967 if (ppc4xx_init_pcie())
973 * Initialize various parts of the PCI Express core for our port
975 ppc4xx_init_pcie_port_hw(port, rootport);
978 * Notice: the following delay has critical impact on device
979 * initialization - if too short (<50ms) the link doesn't get up.
983 val = SDR_READ(SDRN_PESDR_RCSSTS(port));
984 if (val & (1 << 20)) {
985 printf("PCIE%d: PGRST failed %08x\n", port, val);
992 val = SDR_READ(SDRN_PESDR_LOOP(port));
993 if (!(val & 0x00001000)) {
994 printf("PCIE%d: link is not up.\n", port);
999 * Setup UTL registers - but only on revA!
1000 * We use default settings for revB chip.
1002 if (!ppc440spe_revB())
1003 ppc4xx_setup_utl(port);
1006 * We map PCI Express configuration access into the 512MB regions
1008 addr = ppc4xx_get_cfgaddr(port);
1009 low = U64_TO_U32_LOW(addr);
1010 high = U64_TO_U32_HIGH(addr);
1014 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high);
1015 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low);
1016 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
1019 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high);
1020 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
1021 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
1023 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1025 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
1026 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
1027 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
1033 * Check for VC0 active and assert RDY.
1036 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) {
1037 if (!(attempts--)) {
1038 printf("PCIE%d: VC0 not active\n", port);
1043 SDR_WRITE(SDRN_PESDR_RCSSET(port),
1044 SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20);
1050 int ppc4xx_init_pcie_rootport(int port)
1052 return ppc4xx_init_pcie_port(port, 1);
1055 int ppc4xx_init_pcie_endport(int port)
1057 return ppc4xx_init_pcie_port(port, 0);
1060 void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
1062 volatile void *mbase = NULL;
1065 pcie_read_config_byte,
1066 pcie_read_config_word,
1067 pcie_read_config_dword,
1068 pcie_write_config_byte,
1069 pcie_write_config_word,
1070 pcie_write_config_dword);
1074 mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
1075 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
1078 mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
1079 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
1081 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1083 mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
1084 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
1090 * Set bus numbers on our root port
1092 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
1093 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
1094 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
1097 * Set up outbound translation to hose->mem_space from PLB
1098 * addresses at an offset of 0xd_0000_0000. We set the low
1099 * bits of the mask to 11 to turn off splitting into 8
1100 * subregions and to enable the outbound translation.
1102 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
1103 out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE +
1104 port * CONFIG_SYS_PCIE_MEMSIZE);
1105 debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
1106 in_le32(mbase + PECFG_POM0LAL));
1110 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
1111 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
1112 port * CONFIG_SYS_PCIE_MEMSIZE);
1113 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
1114 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
1115 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1116 debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1117 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
1118 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
1119 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)),
1120 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
1123 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
1124 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
1125 port * CONFIG_SYS_PCIE_MEMSIZE);
1126 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
1127 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
1128 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1129 debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1130 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
1131 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
1132 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
1133 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
1135 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1137 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
1138 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
1139 port * CONFIG_SYS_PCIE_MEMSIZE);
1140 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
1141 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
1142 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1143 debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1144 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
1145 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
1146 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
1147 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
1152 /* Set up 4GB inbound memory window at 0 */
1153 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
1154 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
1155 out_le32(mbase + PECFG_BAR0HMPA, 0x7ffffff);
1156 out_le32(mbase + PECFG_BAR0LMPA, 0);
1158 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1159 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1160 out_le32(mbase + PECFG_PIM0LAL, 0);
1161 out_le32(mbase + PECFG_PIM0LAH, 0);
1162 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1163 out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
1164 out_le32(mbase + PECFG_PIMEN, 0x1);
1166 /* Enable I/O, Mem, and Busmaster cycles */
1167 out_le16((u16 *)(mbase + PCI_COMMAND),
1168 in_le16((u16 *)(mbase + PCI_COMMAND)) |
1169 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1171 /* Set Device and Vendor Id */
1172 out_le16(mbase + 0x200, 0xaaa0 + port);
1173 out_le16(mbase + 0x202, 0xbed0 + port);
1175 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1176 out_le32(mbase + 0x208, 0x06040001);
1178 printf("PCIE%d: successfully set as root-complex\n", port);
1181 int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
1183 volatile void *mbase = NULL;
1187 pcie_read_config_byte,
1188 pcie_read_config_word,
1189 pcie_read_config_dword,
1190 pcie_write_config_byte,
1191 pcie_write_config_word,
1192 pcie_write_config_dword);
1196 mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
1197 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
1200 mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
1201 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
1203 #if defined(CONFIG_SYS_PCIE2_CFGBASE)
1205 mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
1206 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
1212 * Set up outbound translation to hose->mem_space from PLB
1213 * addresses at an offset of 0xd_0000_0000. We set the low
1214 * bits of the mask to 11 to turn off splitting into 8
1215 * subregions and to enable the outbound translation.
1217 out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
1218 out_le32(mbase + PECFG_POM0LAL, 0x00001000);
1222 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
1223 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
1224 port * CONFIG_SYS_PCIE_MEMSIZE);
1225 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
1226 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
1227 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1230 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
1231 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
1232 port * CONFIG_SYS_PCIE_MEMSIZE);
1233 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
1234 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
1235 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1237 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1239 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
1240 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
1241 port * CONFIG_SYS_PCIE_MEMSIZE);
1242 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
1243 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
1244 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1249 /* Set up 64MB inbound memory window at 0 */
1250 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
1251 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
1253 out_le32(mbase + PECFG_PIM01SAH, 0xffffffff);
1254 out_le32(mbase + PECFG_PIM01SAL, 0xfc000000);
1257 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff);
1258 out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64);
1260 /* Disable BAR1 & BAR2 */
1261 out_le32(mbase + PECFG_BAR1MPA, 0);
1262 out_le32(mbase + PECFG_BAR2HMPA, 0);
1263 out_le32(mbase + PECFG_BAR2LMPA, 0);
1265 out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE));
1266 out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE));
1267 out_le32(mbase + PECFG_PIMEN, 0x1);
1269 /* Enable I/O, Mem, and Busmaster cycles */
1270 out_le16((u16 *)(mbase + PCI_COMMAND),
1271 in_le16((u16 *)(mbase + PCI_COMMAND)) |
1272 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1273 out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */
1274 out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */
1276 /* Set Class Code to Processor/PPC */
1277 out_le32(mbase + 0x208, 0x0b200001);
1280 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
1281 if (!(attempts--)) {
1282 printf("PCIE%d: BME not active\n", port);
1288 printf("PCIE%d: successfully set as endpoint\n", port);
1292 #endif /* CONFIG_440SPE && CONFIG_PCI */