2 * (C) Copyright 2000-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
37 #include <asm/cache.h>
38 #include <asm/ppc4xx.h>
41 DECLARE_GLOBAL_DATA_PTR;
43 void board_reset(void);
46 * To provide an interface to detect CPU number for boards that support
47 * more then one CPU, we implement the "weak" default functions here.
51 int __get_cpu_num(void)
53 return NA_OR_UNKNOWN_CPU;
55 int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
57 #if defined(CONFIG_PCI)
58 #if defined(CONFIG_405GP) || \
59 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
60 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
64 static int pci_async_enabled(void)
66 #if defined(CONFIG_405GP)
67 return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
70 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
71 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
72 defined(CONFIG_460EX) || defined(CONFIG_460GT)
75 mfsdr(SDR0_SDSTP1, val);
76 return (val & SDR0_SDSTP1_PAME_MASK);
80 #endif /* CONFIG_PCI */
82 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
83 !defined(CONFIG_405) && !defined(CONFIG_405EX)
84 int pci_arbiter_enabled(void)
86 #if defined(CONFIG_405GP)
87 return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
90 #if defined(CONFIG_405EP)
91 return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
94 #if defined(CONFIG_440GP)
95 return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
98 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
101 mfsdr(SDR0_XCR0, val);
102 return (val & SDR0_XCR0_PAE_MASK);
104 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
105 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
106 defined(CONFIG_460EX) || defined(CONFIG_460GT)
109 mfsdr(SDR0_PCI0, val);
110 return (val & SDR0_PCI0_PAE_MASK);
115 #if defined(CONFIG_405EP)
118 static int i2c_bootrom_enabled(void)
120 #if defined(CONFIG_405EP)
121 return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
125 mfsdr(SDR0_SDCS0, val);
126 return (val & SDR0_SDCS_SDD);
131 #if defined(CONFIG_440GX)
132 #define SDR0_PINSTP_SHIFT 29
133 static char *bootstrap_str[] = {
143 static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
146 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
147 #define SDR0_PINSTP_SHIFT 30
148 static char *bootstrap_str[] = {
154 static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
157 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
158 #define SDR0_PINSTP_SHIFT 29
159 static char *bootstrap_str[] = {
169 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
172 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
173 #define SDR0_PINSTP_SHIFT 29
174 static char *bootstrap_str[] = {
184 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
187 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
188 #define SDR0_PINSTP_SHIFT 29
189 static char *bootstrap_str[] = {
196 "I2C (Addr 0x54)", /* A8 */
197 "I2C (Addr 0x52)", /* A4 */
199 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
202 #if defined(CONFIG_460SX)
203 #define SDR0_PINSTP_SHIFT 29
204 static char *bootstrap_str[] = {
209 "I2C (Addr 0x54)", /* A8 */
210 "I2C (Addr 0x52)", /* A4 */
212 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
215 #if defined(CONFIG_405EZ)
216 #define SDR0_PINSTP_SHIFT 28
217 static char *bootstrap_str[] = {
220 "NAND (512 page, 4 addr cycle)",
224 "NAND (2K page, 5 addr cycle)",
228 "NAND (2K page, 4 addr cycle)",
230 "NAND (512 page, 3 addr cycle)",
235 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
236 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
239 #if defined(CONFIG_405EX)
240 #define SDR0_PINSTP_SHIFT 29
241 static char *bootstrap_str[] = {
251 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
254 #if defined(SDR0_PINSTP_SHIFT)
255 static int bootstrap_option(void)
259 mfsdr(SDR0_PINSTP, val);
260 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
262 #endif /* SDR0_PINSTP_SHIFT */
265 #if defined(CONFIG_440GP)
266 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
268 /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
271 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */
272 mtdcr (CPC0_SYS0, sys0);
273 mtdcr (CPC0_SYS1, sys1);
274 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */
275 mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
279 #endif /* CONFIG_440GP */
284 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
285 uint pvr = get_pvr();
286 ulong clock = gd->cpu_clk;
288 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
292 #if !defined(CONFIG_IOP480)
293 char addstr[64] = "";
297 cpu_num = get_cpu_num();
299 printf("CPU%d: ", cpu_num);
303 get_sys_info(&sys_info);
305 #if defined(CONFIG_XILINX_440)
306 puts("IBM PowerPC ");
308 puts("AMCC PowerPC ");
313 #if !defined(CONFIG_440)
315 puts("405GP Rev. B");
319 puts("405GP Rev. C");
323 puts("405GP Rev. D");
327 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
328 puts("405GP Rev. E");
333 puts("405CR Rev. A");
337 puts("405CR Rev. B");
341 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
342 puts("405CR Rev. C");
347 puts("405GPr Rev. B");
351 puts("405EP Rev. B");
355 puts("405EZ Rev. A");
359 puts("405EX Rev. A");
360 strcpy(addstr, "Security support");
364 puts("405EXr Rev. A");
365 strcpy(addstr, "No Security support");
369 puts("405EX Rev. C");
370 strcpy(addstr, "Security support");
374 puts("405EX Rev. C");
375 strcpy(addstr, "No Security support");
379 puts("405EXr Rev. C");
380 strcpy(addstr, "Security support");
384 puts("405EXr Rev. C");
385 strcpy(addstr, "No Security support");
389 puts("405EX Rev. D");
390 strcpy(addstr, "Security support");
394 puts("405EX Rev. D");
395 strcpy(addstr, "No Security support");
399 puts("405EXr Rev. D");
400 strcpy(addstr, "Security support");
404 puts("405EXr Rev. D");
405 strcpy(addstr, "No Security support");
408 #else /* CONFIG_440 */
410 #if defined(CONFIG_440GP)
412 puts("440GP Rev. B");
413 /* See errata 1.12: CHIP_4 */
414 if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
415 (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
416 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
417 "Resetting chip ...\n");
418 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
419 do_chip_reset ( mfdcr(CPC0_STRP0),
425 puts("440GP Rev. C");
427 #endif /* CONFIG_440GP */
430 puts("440GX Rev. A");
434 puts("440GX Rev. B");
438 puts("440GX Rev. C");
442 puts("440GX Rev. F");
446 puts("440EP Rev. A");
450 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
451 puts("440EP Rev. B");
454 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
455 puts("440EP Rev. C");
457 #endif /* CONFIG_440EP */
460 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
461 puts("440GR Rev. A");
464 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
465 puts("440GR Rev. B");
467 #endif /* CONFIG_440GR */
470 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
471 puts("440EPx Rev. A");
472 strcpy(addstr, "Security/Kasumi support");
475 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
476 puts("440EPx Rev. A");
477 strcpy(addstr, "No Security/Kasumi support");
479 #endif /* CONFIG_440EPX */
482 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
483 puts("440GRx Rev. A");
484 strcpy(addstr, "Security/Kasumi support");
487 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
488 puts("440GRx Rev. A");
489 strcpy(addstr, "No Security/Kasumi support");
491 #endif /* CONFIG_440GRX */
493 case PVR_440SP_6_RAB:
494 puts("440SP Rev. A/B");
495 strcpy(addstr, "RAID 6 support");
499 puts("440SP Rev. A/B");
500 strcpy(addstr, "No RAID 6 support");
504 puts("440SP Rev. C");
505 strcpy(addstr, "RAID 6 support");
509 puts("440SP Rev. C");
510 strcpy(addstr, "No RAID 6 support");
513 case PVR_440SPe_6_RA:
514 puts("440SPe Rev. A");
515 strcpy(addstr, "RAID 6 support");
519 puts("440SPe Rev. A");
520 strcpy(addstr, "No RAID 6 support");
523 case PVR_440SPe_6_RB:
524 puts("440SPe Rev. B");
525 strcpy(addstr, "RAID 6 support");
529 puts("440SPe Rev. B");
530 strcpy(addstr, "No RAID 6 support");
533 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
535 puts("460EX Rev. A");
536 strcpy(addstr, "No Security/Kasumi support");
539 case PVR_460EX_SE_RA:
540 puts("460EX Rev. A");
541 strcpy(addstr, "Security/Kasumi support");
545 puts("460EX Rev. B");
546 mfsdr(SDR0_ECID3, reg);
547 if (reg & 0x00100000)
548 strcpy(addstr, "No Security/Kasumi support");
550 strcpy(addstr, "Security/Kasumi support");
554 puts("460GT Rev. A");
555 strcpy(addstr, "No Security/Kasumi support");
558 case PVR_460GT_SE_RA:
559 puts("460GT Rev. A");
560 strcpy(addstr, "Security/Kasumi support");
564 puts("460GT Rev. B");
565 mfsdr(SDR0_ECID3, reg);
566 if (reg & 0x00100000)
567 strcpy(addstr, "No Security/Kasumi support");
569 strcpy(addstr, "Security/Kasumi support");
574 puts("460SX Rev. A");
575 strcpy(addstr, "Security support");
578 case PVR_460SX_RA_V1:
579 puts("460SX Rev. A");
580 strcpy(addstr, "No Security support");
584 puts("460GX Rev. A");
585 strcpy(addstr, "Security support");
588 case PVR_460GX_RA_V1:
589 puts("460GX Rev. A");
590 strcpy(addstr, "No Security support");
594 puts("440x5 VIRTEX5");
596 #endif /* CONFIG_440 */
599 printf (" UNKNOWN (PVR=%08x)", pvr);
603 printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
605 sys_info.freqPLB / 1000000,
606 get_OPB_freq() / 1000000,
607 sys_info.freqEBC / 1000000);
608 #if defined(CONFIG_PCI) && \
609 (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
610 defined(CONFIG_440GR) || defined(CONFIG_440GRX))
611 printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
616 printf(" %s\n", addstr);
618 #if defined(I2C_BOOTROM)
619 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
620 #endif /* I2C_BOOTROM */
621 #if defined(SDR0_PINSTP_SHIFT)
622 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
623 printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
624 #ifdef CONFIG_NAND_U_BOOT
625 puts(", booting from NAND");
626 #endif /* CONFIG_NAND_U_BOOT */
628 #endif /* SDR0_PINSTP_SHIFT */
630 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
631 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
634 #if defined(CONFIG_PCI) && defined(PCI_ASYNC)
635 if (pci_async_enabled()) {
636 printf (", PCI async ext clock used");
638 printf (", PCI sync clock at %lu MHz",
639 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
643 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
647 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
648 printf (" 16 kB I-Cache 16 kB D-Cache");
649 #elif defined(CONFIG_440)
650 printf (" 32 kB I-Cache 32 kB D-Cache");
652 printf (" 16 kB I-Cache %d kB D-Cache",
653 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
655 #endif /* !defined(CONFIG_IOP480) */
657 #if defined(CONFIG_IOP480)
658 printf ("PLX IOP480 (PVR=%08x)", pvr);
659 printf (" at %s MHz:", strmhz(buf, clock));
660 printf (" %u kB I-Cache", 4);
661 printf (" %u kB D-Cache", 2);
664 #endif /* !defined(CONFIG_405) */
671 int ppc440spe_revB() {
675 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
681 /* ------------------------------------------------------------------------- */
683 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
685 #if defined(CONFIG_BOARD_RESET)
688 #if defined(CONFIG_SYS_4xx_RESET_TYPE)
689 mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
692 * Initiate system reset in debug control register DBCR
694 mtspr(SPRN_DBCR0, 0x30000000);
695 #endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
696 #endif /* defined(CONFIG_BOARD_RESET) */
703 * Get timebase clock frequency
705 unsigned long get_tbclk (void)
707 #if !defined(CONFIG_IOP480)
710 get_sys_info(&sys_info);
711 return (sys_info.freqProcessor);
719 #if defined(CONFIG_WATCHDOG)
720 void watchdog_reset(void)
722 int re_enable = disable_interrupts();
723 reset_4xx_watchdog();
724 if (re_enable) enable_interrupts();
727 void reset_4xx_watchdog(void)
732 mtspr(SPRN_TSR, 0x40000000);
734 #endif /* CONFIG_WATCHDOG */
737 * Initializes on-chip ethernet controllers.
738 * to override, implement board_eth_init()
740 int cpu_eth_init(bd_t *bis)
742 #if defined(CONFIG_PPC4xx_EMAC)
743 ppc_4xx_eth_initialize(bis);