2 * (C) Copyright 2000-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
11 * written or collected and sometimes rewritten by
12 * Magnus Damm <damm@bitsmart.com>
14 * minor modifications by
15 * Wolfgang Denk <wd@denx.de>
21 #include <asm/cache.h>
22 #include <asm/ppc4xx.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 void board_reset(void);
30 * To provide an interface to detect CPU number for boards that support
31 * more then one CPU, we implement the "weak" default functions here.
35 int __get_cpu_num(void)
37 return NA_OR_UNKNOWN_CPU;
39 int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
41 #if defined(CONFIG_PCI)
42 #if defined(CONFIG_405GP) || \
43 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
44 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
48 static int pci_async_enabled(void)
50 #if defined(CONFIG_405GP)
51 return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
54 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
55 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
56 defined(CONFIG_460EX) || defined(CONFIG_460GT)
59 mfsdr(SDR0_SDSTP1, val);
60 return (val & SDR0_SDSTP1_PAME_MASK);
64 #endif /* CONFIG_PCI */
66 #if defined(CONFIG_PCI) && \
67 !defined(CONFIG_405) && !defined(CONFIG_405EX)
68 int pci_arbiter_enabled(void)
70 #if defined(CONFIG_405GP)
71 return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
74 #if defined(CONFIG_405EP)
75 return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
78 #if defined(CONFIG_440GP)
79 return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
82 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
85 mfsdr(SDR0_XCR0, val);
86 return (val & SDR0_XCR0_PAE_MASK);
88 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
89 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
90 defined(CONFIG_460EX) || defined(CONFIG_460GT)
93 mfsdr(SDR0_PCI0, val);
94 return (val & SDR0_PCI0_PAE_MASK);
99 #if defined(CONFIG_405EP)
102 static int i2c_bootrom_enabled(void)
104 #if defined(CONFIG_405EP)
105 return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
109 mfsdr(SDR0_SDCS0, val);
110 return (val & SDR0_SDCS_SDD);
115 #if defined(CONFIG_440GX)
116 #define SDR0_PINSTP_SHIFT 29
117 static char *bootstrap_str[] = {
127 static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
130 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
131 #define SDR0_PINSTP_SHIFT 30
132 static char *bootstrap_str[] = {
138 static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
141 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
142 #define SDR0_PINSTP_SHIFT 29
143 static char *bootstrap_str[] = {
153 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
156 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
157 #define SDR0_PINSTP_SHIFT 29
158 static char *bootstrap_str[] = {
168 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
171 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
172 #define SDR0_PINSTP_SHIFT 29
173 static char *bootstrap_str[] = {
180 "I2C (Addr 0x54)", /* A8 */
181 "I2C (Addr 0x52)", /* A4 */
183 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
186 #if defined(CONFIG_460SX)
187 #define SDR0_PINSTP_SHIFT 29
188 static char *bootstrap_str[] = {
193 "I2C (Addr 0x54)", /* A8 */
194 "I2C (Addr 0x52)", /* A4 */
196 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
199 #if defined(CONFIG_405EZ)
200 #define SDR0_PINSTP_SHIFT 28
201 static char *bootstrap_str[] = {
204 "NAND (512 page, 4 addr cycle)",
208 "NAND (2K page, 5 addr cycle)",
212 "NAND (2K page, 4 addr cycle)",
214 "NAND (512 page, 3 addr cycle)",
219 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
220 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
223 #if defined(CONFIG_405EX)
224 #define SDR0_PINSTP_SHIFT 29
225 static char *bootstrap_str[] = {
235 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
238 #if defined(SDR0_PINSTP_SHIFT)
239 static int bootstrap_option(void)
243 mfsdr(SDR0_PINSTP, val);
244 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
246 #endif /* SDR0_PINSTP_SHIFT */
249 #if defined(CONFIG_440GP)
250 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
252 /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
255 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */
256 mtdcr (CPC0_SYS0, sys0);
257 mtdcr (CPC0_SYS1, sys1);
258 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */
259 mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
263 #endif /* CONFIG_440GP */
268 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
269 uint pvr = get_pvr();
270 ulong clock = gd->cpu_clk;
272 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
276 char addstr[64] = "";
280 cpu_num = get_cpu_num();
282 printf("CPU%d: ", cpu_num);
286 get_sys_info(&sys_info);
288 #if defined(CONFIG_XILINX_440)
289 puts("IBM PowerPC ");
291 puts("AMCC PowerPC ");
296 #if !defined(CONFIG_440)
298 puts("405GP Rev. B");
302 puts("405GP Rev. C");
306 puts("405GP Rev. D");
310 puts("405GP Rev. E");
314 puts("405GPr Rev. B");
318 puts("405EP Rev. B");
322 puts("405EZ Rev. A");
326 puts("405EX Rev. A");
327 strcpy(addstr, "Security support");
331 puts("405EXr Rev. A");
332 strcpy(addstr, "No Security support");
336 puts("405EX Rev. C");
337 strcpy(addstr, "Security support");
341 puts("405EX Rev. C");
342 strcpy(addstr, "No Security support");
346 puts("405EXr Rev. C");
347 strcpy(addstr, "Security support");
351 puts("405EXr Rev. C");
352 strcpy(addstr, "No Security support");
356 puts("405EX Rev. D");
357 strcpy(addstr, "Security support");
361 puts("405EX Rev. D");
362 strcpy(addstr, "No Security support");
366 puts("405EXr Rev. D");
367 strcpy(addstr, "Security support");
371 puts("405EXr Rev. D");
372 strcpy(addstr, "No Security support");
375 #else /* CONFIG_440 */
377 #if defined(CONFIG_440GP)
379 puts("440GP Rev. B");
380 /* See errata 1.12: CHIP_4 */
381 if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
382 (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
383 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
384 "Resetting chip ...\n");
385 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
386 do_chip_reset ( mfdcr(CPC0_STRP0),
392 puts("440GP Rev. C");
394 #endif /* CONFIG_440GP */
397 puts("440GX Rev. A");
401 puts("440GX Rev. B");
405 puts("440GX Rev. C");
409 puts("440GX Rev. F");
413 puts("440EP Rev. A");
417 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
418 puts("440EP Rev. B");
421 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
422 puts("440EP Rev. C");
424 #endif /* CONFIG_440EP */
427 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
428 puts("440GR Rev. A");
431 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
432 puts("440GR Rev. B");
434 #endif /* CONFIG_440GR */
437 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
438 puts("440EPx Rev. A");
439 strcpy(addstr, "Security/Kasumi support");
442 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
443 puts("440EPx Rev. A");
444 strcpy(addstr, "No Security/Kasumi support");
446 #endif /* CONFIG_440EPX */
449 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
450 puts("440GRx Rev. A");
451 strcpy(addstr, "Security/Kasumi support");
454 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
455 puts("440GRx Rev. A");
456 strcpy(addstr, "No Security/Kasumi support");
458 #endif /* CONFIG_440GRX */
460 case PVR_440SP_6_RAB:
461 puts("440SP Rev. A/B");
462 strcpy(addstr, "RAID 6 support");
466 puts("440SP Rev. A/B");
467 strcpy(addstr, "No RAID 6 support");
471 puts("440SP Rev. C");
472 strcpy(addstr, "RAID 6 support");
476 puts("440SP Rev. C");
477 strcpy(addstr, "No RAID 6 support");
480 case PVR_440SPe_6_RA:
481 puts("440SPe Rev. A");
482 strcpy(addstr, "RAID 6 support");
486 puts("440SPe Rev. A");
487 strcpy(addstr, "No RAID 6 support");
490 case PVR_440SPe_6_RB:
491 puts("440SPe Rev. B");
492 strcpy(addstr, "RAID 6 support");
496 puts("440SPe Rev. B");
497 strcpy(addstr, "No RAID 6 support");
500 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
502 puts("460EX Rev. A");
503 strcpy(addstr, "No Security/Kasumi support");
506 case PVR_460EX_SE_RA:
507 puts("460EX Rev. A");
508 strcpy(addstr, "Security/Kasumi support");
512 puts("460EX Rev. B");
513 mfsdr(SDR0_ECID3, reg);
514 if (reg & 0x00100000)
515 strcpy(addstr, "No Security/Kasumi support");
517 strcpy(addstr, "Security/Kasumi support");
521 puts("460GT Rev. A");
522 strcpy(addstr, "No Security/Kasumi support");
525 case PVR_460GT_SE_RA:
526 puts("460GT Rev. A");
527 strcpy(addstr, "Security/Kasumi support");
531 puts("460GT Rev. B");
532 mfsdr(SDR0_ECID3, reg);
533 if (reg & 0x00100000)
534 strcpy(addstr, "No Security/Kasumi support");
536 strcpy(addstr, "Security/Kasumi support");
541 puts("460SX Rev. A");
542 strcpy(addstr, "Security support");
545 case PVR_460SX_RA_V1:
546 puts("460SX Rev. A");
547 strcpy(addstr, "No Security support");
551 puts("460GX Rev. A");
552 strcpy(addstr, "Security support");
555 case PVR_460GX_RA_V1:
556 puts("460GX Rev. A");
557 strcpy(addstr, "No Security support");
560 case PVR_APM821XX_RA:
561 puts("APM821XX Rev. A");
562 strcpy(addstr, "Security support");
566 puts("440x5 VIRTEX5");
568 #endif /* CONFIG_440 */
571 printf (" UNKNOWN (PVR=%08x)", pvr);
575 printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
577 sys_info.freqPLB / 1000000,
578 get_OPB_freq() / 1000000,
579 sys_info.freqEBC / 1000000);
580 #if defined(CONFIG_PCI) && \
581 (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
582 defined(CONFIG_440GR) || defined(CONFIG_440GRX))
583 printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
588 printf(" %s\n", addstr);
590 #if defined(I2C_BOOTROM)
591 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
592 #endif /* I2C_BOOTROM */
593 #if defined(SDR0_PINSTP_SHIFT)
594 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
595 printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
597 #endif /* SDR0_PINSTP_SHIFT */
599 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
600 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
603 #if defined(CONFIG_PCI) && defined(PCI_ASYNC)
604 if (pci_async_enabled()) {
605 printf (", PCI async ext clock used");
607 printf (", PCI sync clock at %lu MHz",
608 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
612 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
616 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
617 printf(" 16 KiB I-Cache 16 KiB D-Cache");
618 #elif defined(CONFIG_440)
619 printf(" 32 KiB I-Cache 32 KiB D-Cache");
621 printf(" 16 KiB I-Cache %d KiB D-Cache",
622 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
625 #endif /* !defined(CONFIG_405) */
632 int ppc440spe_revB() {
636 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
642 /* ------------------------------------------------------------------------- */
644 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
646 #if defined(CONFIG_BOARD_RESET)
649 #if defined(CONFIG_SYS_4xx_RESET_TYPE)
650 mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
653 * Initiate system reset in debug control register DBCR
655 mtspr(SPRN_DBCR0, 0x30000000);
656 #endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
657 #endif /* defined(CONFIG_BOARD_RESET) */
664 * Get timebase clock frequency
666 unsigned long get_tbclk (void)
670 get_sys_info(&sys_info);
671 return (sys_info.freqProcessor);
675 #if defined(CONFIG_WATCHDOG)
676 void watchdog_reset(void)
678 int re_enable = disable_interrupts();
679 reset_4xx_watchdog();
680 if (re_enable) enable_interrupts();
683 void reset_4xx_watchdog(void)
688 mtspr(SPRN_TSR, 0x40000000);
690 #endif /* CONFIG_WATCHDOG */
693 * Initializes on-chip ethernet controllers.
694 * to override, implement board_eth_init()
696 int cpu_eth_init(bd_t *bis)
698 #if defined(CONFIG_PPC4xx_EMAC)
699 ppc_4xx_eth_initialize(bis);